xref: /nrf52832-nimble/rt-thread/libcpu/mips/x1000/x1000_intc.h (revision 104654410c56c573564690304ae786df310c91fc)
1 /*
2  * File      : x1000_intc.h
3  * This file is part of RT-Thread RTOS
4  * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
5  *
6  *  This program is free software; you can redistribute it and/or modify
7  *  it under the terms of the GNU General Public License as published by
8  *  the Free Software Foundation; either version 2 of the License, or
9  *  (at your option) any later version.
10  *
11  *  This program is distributed in the hope that it will be useful,
12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  *  GNU General Public License for more details.
15  *
16  *  You should have received a copy of the GNU General Public License along
17  *  with this program; if not, write to the Free Software Foundation, Inc.,
18  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19  *
20  * Change Logs:
21  * Date           Author       Notes
22  * 2017-02-03     Urey         the first version
23  */
24 
25 #ifndef _X1000_INTC_H_
26 #define _X1000_INTC_H_
27 
28 
29 /*
30  * INTC (Interrupt Controller)
31  */
32 #define INTC_ISR(n)             (INTC_BASE + 0x00 + (n) * 0x20)
33 #define INTC_IMR(n)             (INTC_BASE + 0x04 + (n) * 0x20)
34 #define INTC_IMSR(n)            (INTC_BASE + 0x08 + (n) * 0x20)
35 #define INTC_IMCR(n)            (INTC_BASE + 0x0c + (n) * 0x20)
36 #define INTC_IPR(n)             (INTC_BASE + 0x10 + (n) * 0x20)
37 
38 #define REG_INTC_ISR(n)         REG32(INTC_ISR((n)))
39 #define REG_INTC_IMR(n)         REG32(INTC_IMR((n)))
40 #define REG_INTC_IMSR(n)        REG32(INTC_IMSR((n)))
41 #define REG_INTC_IMCR(n)        REG32(INTC_IMCR((n)))
42 #define REG_INTC_IPR(n)         REG32(INTC_IPR((n)))
43 
44 // interrupt controller interrupts
45 #define IRQ_DMIC                0
46 #define IRQ_AIC0                1
47 #define IRQ_RESERVED2           2
48 #define IRQ_RESERVED3           3
49 #define IRQ_RESERVED4           4
50 #define IRQ_RESERVED5           5
51 #define IRQ_RESERVED6           6
52 #define IRQ_SFC                 7
53 #define IRQ_SSI0                8
54 #define IRQ_RESERVED9           9
55 #define IRQ_PDMA                10
56 #define IRQ_PDMAD               11
57 #define IRQ_RESERVED12          12
58 #define IRQ_RESERVED13          13
59 #define IRQ_GPIO3               14
60 #define IRQ_GPIO2               15
61 #define IRQ_GPIO1               16
62 #define IRQ_GPIO0               17
63 #define IRQ_RESERVED18          18
64 #define IRQ_RESERVED19          19
65 #define IRQ_RESERVED20          20
66 #define IRQ_OTG                 21
67 #define IRQ_RESERVED22          22
68 #define IRQ_AES                 23
69 #define IRQ_RESERVED24          24
70 #define IRQ_TCU2                25
71 #define IRQ_TCU1                26
72 #define IRQ_TCU0                27
73 #define IRQ_RESERVED28          28
74 #define IRQ_RESERVED29          29
75 #define IRQ_CIM                 30
76 #define IRQ_LCD                 31
77 #define IRQ_RTC                 32
78 #define IRQ_RESERVED33          33
79 #define IRQ_RESERVED34          34
80 #define IRQ_RESERVED35          35
81 #define IRQ_MSC1                36
82 #define IRQ_MSC0                37
83 #define IRQ_SCC                 38
84 #define IRQ_RESERVED39          39
85 #define IRQ_PCM0                40
86 #define IRQ_RESERVED41          41
87 #define IRQ_RESERVED42          42
88 #define IRQ_RESERVED43          43
89 #define IRQ_HARB2               44
90 #define IRQ_RESERVED45          45
91 #define IRQ_HARB0               46
92 #define IRQ_CPM                 47
93 #define IRQ_RESERVED48          48
94 #define IRQ_UART2               49
95 #define IRQ_UART1               50
96 #define IRQ_UART0               51
97 #define IRQ_DDR                 52
98 #define IRQ_RESERVED53          53
99 #define IRQ_EFUSE               54
100 #define IRQ_MAC                 55
101 #define IRQ_RESERVED56          56
102 #define IRQ_RESERVED57          57
103 #define IRQ_I2C2                58
104 #define IRQ_I2C1                59
105 #define IRQ_I2C0                60
106 #define IRQ_PDMAM               61
107 #define IRQ_JPEG                62
108 #define IRQ_RESERVED63          63
109 
110 #define IRQ_INTC_MAX            63
111 
112 #ifndef __ASSEMBLY__
113 
114 #define __intc_unmask_irq(n)    (REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))
115 #define __intc_mask_irq(n)      (REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))
116 #define __intc_ack_irq(n)       (REG_INTC_IPR((n)/32) = (1 << ((n)%32)))        /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */
117 
118 #endif /* !__ASSEMBLY__ */
119 
120 #endif /* _X1000_INTC_H_ */
121