37 #define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080 + ((n)/32) * 4)
38 #define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + ((n)/32) * 4)
39 #define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + ((n)/32) * 4)
40 #define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200 + ((n)/32) * 4)
41 #define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + ((n)/32) * 4)
42 #define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300 + ((n)/32) * 4)
43 #define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380 + ((n)/32) * 4)
66     rt_uint32_t mask = 1 << (irq % 32);  in arm_gic_ack()
80     rt_uint32_t mask = 1 << (irq % 32);  in arm_gic_mask()
92     rt_uint32_t mask = 1 << (irq % 32);  in arm_gic_clear_pending()
104     rt_uint32_t mask = 1 << (irq % 32);  in arm_gic_clear_active()
133     rt_uint32_t mask = 1 << (irq % 32);  in arm_gic_umask()
163     for (i = 0; i < _gic_max_irq / 32; i++)  in arm_gic_dump()
167                                        i * 32));  in arm_gic_dump()
170     for (i = 0; i < _gic_max_irq / 32; i++)  in arm_gic_dump()
174                                         i * 32));  in arm_gic_dump()
177     for (i = 0; i < _gic_max_irq / 32; i++)  in arm_gic_dump()
181                                        i * 32));  in arm_gic_dump()
202     _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;  in arm_gic_dist_init()
230     for (i = 32; i < _gic_max_irq; i += 16)  in arm_gic_dist_init()
234     for (i = 32; i < _gic_max_irq; i += 4)  in arm_gic_dist_init()
242     for (i = 0; i < _gic_max_irq; i += 32)  in arm_gic_dist_init()
245     for (i = 0; i < _gic_max_irq; i += 32)  in arm_gic_dist_init()
286                         vector) &= ~(1 << (vector % 32));  in arm_gic_set_group()
291                         vector) |=  (1 << (vector % 32));  in arm_gic_set_group()