1 /*
2 * Copyright (c) 2006-2018, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2013-07-20 Bernard first version
9 * 2014-04-03 Grissiom many enhancements
10 */
11
12 #include <rtthread.h>
13 #include <board.h>
14
15 #include "gic.h"
16 #include "cp15.h"
17
18 struct arm_gic
19 {
20 rt_uint32_t offset;
21
22 rt_uint32_t dist_hw_base;
23 rt_uint32_t cpu_hw_base;
24 };
25 static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
26
27 #define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00)
28 #define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04)
29 #define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08)
30 #define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c)
31 #define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10)
32 #define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14)
33 #define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18)
34
35 #define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000)
36 #define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004)
37 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4)
38 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4)
39 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4)
40 #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4)
41 #define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4)
42 #define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4)
43 #define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4)
44 #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4)
45 #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4)
46 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
47 #define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00)
48 #define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
49 #define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8)
50
51 static unsigned int _gic_max_irq;
52
arm_gic_get_active_irq(rt_uint32_t index)53 int arm_gic_get_active_irq(rt_uint32_t index)
54 {
55 int irq;
56
57 RT_ASSERT(index < ARM_GIC_MAX_NR);
58
59 irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
60 irq += _gic_table[index].offset;
61 return irq;
62 }
63
arm_gic_ack(rt_uint32_t index,int irq)64 void arm_gic_ack(rt_uint32_t index, int irq)
65 {
66 rt_uint32_t mask = 1 << (irq % 32);
67
68 RT_ASSERT(index < ARM_GIC_MAX_NR);
69
70 irq = irq - _gic_table[index].offset;
71 RT_ASSERT(irq >= 0);
72
73 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
74 GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
75 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
76 }
77
arm_gic_mask(rt_uint32_t index,int irq)78 void arm_gic_mask(rt_uint32_t index, int irq)
79 {
80 rt_uint32_t mask = 1 << (irq % 32);
81
82 RT_ASSERT(index < ARM_GIC_MAX_NR);
83
84 irq = irq - _gic_table[index].offset;
85 RT_ASSERT(irq >= 0);
86
87 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
88 }
89
arm_gic_clear_pending(rt_uint32_t index,int irq)90 void arm_gic_clear_pending(rt_uint32_t index, int irq)
91 {
92 rt_uint32_t mask = 1 << (irq % 32);
93
94 RT_ASSERT(index < ARM_GIC_MAX_NR);
95
96 irq = irq - _gic_table[index].offset;
97 RT_ASSERT(irq >= 0);
98
99 GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
100 }
101
arm_gic_clear_active(rt_uint32_t index,int irq)102 void arm_gic_clear_active(rt_uint32_t index, int irq)
103 {
104 rt_uint32_t mask = 1 << (irq % 32);
105
106 RT_ASSERT(index < ARM_GIC_MAX_NR);
107
108 irq = irq - _gic_table[index].offset;
109 RT_ASSERT(irq >= 0);
110
111 GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
112 }
113
arm_gic_set_cpu(rt_uint32_t index,int irq,unsigned int cpumask)114 void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
115 {
116 rt_uint32_t old_tgt;
117
118 RT_ASSERT(index < ARM_GIC_MAX_NR);
119
120 irq = irq - _gic_table[index].offset;
121 RT_ASSERT(irq >= 0);
122
123 old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
124
125 old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
126 old_tgt |= cpumask << ((irq % 4)*8);
127
128 GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
129 }
130
arm_gic_umask(rt_uint32_t index,int irq)131 void arm_gic_umask(rt_uint32_t index, int irq)
132 {
133 rt_uint32_t mask = 1 << (irq % 32);
134
135 RT_ASSERT(index < ARM_GIC_MAX_NR);
136
137 irq = irq - _gic_table[index].offset;
138 RT_ASSERT(irq >= 0);
139
140 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
141 }
142
arm_gic_dump_type(rt_uint32_t index)143 void arm_gic_dump_type(rt_uint32_t index)
144 {
145 unsigned int gic_type;
146
147 gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
148 rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
149 (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
150 _gic_table[index].dist_hw_base,
151 _gic_max_irq,
152 gic_type & (1 << 10) ? "has" : "no",
153 gic_type);
154 }
155
arm_gic_dump(rt_uint32_t index)156 void arm_gic_dump(rt_uint32_t index)
157 {
158 unsigned int i, k;
159
160 k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
161 rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
162 rt_kprintf("--- hw mask ---\n");
163 for (i = 0; i < _gic_max_irq / 32; i++)
164 {
165 rt_kprintf("0x%08x, ",
166 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
167 i * 32));
168 }
169 rt_kprintf("\n--- hw pending ---\n");
170 for (i = 0; i < _gic_max_irq / 32; i++)
171 {
172 rt_kprintf("0x%08x, ",
173 GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
174 i * 32));
175 }
176 rt_kprintf("\n--- hw active ---\n");
177 for (i = 0; i < _gic_max_irq / 32; i++)
178 {
179 rt_kprintf("0x%08x, ",
180 GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
181 i * 32));
182 }
183 rt_kprintf("\n");
184 }
185 #ifdef RT_USING_FINSH
186 #include <finsh.h>
187 FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
188 #endif
189
arm_gic_dist_init(rt_uint32_t index,rt_uint32_t dist_base,int irq_start)190 int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
191 {
192 unsigned int gic_type, i;
193 rt_uint32_t cpumask = 1 << 0;
194
195 RT_ASSERT(index < ARM_GIC_MAX_NR);
196
197 _gic_table[index].dist_hw_base = dist_base;
198 _gic_table[index].offset = irq_start;
199
200 /* Find out how many interrupts are supported. */
201 gic_type = GIC_DIST_TYPE(dist_base);
202 _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
203
204 /*
205 * The GIC only supports up to 1020 interrupt sources.
206 * Limit this to either the architected maximum, or the
207 * platform maximum.
208 */
209 if (_gic_max_irq > 1020)
210 _gic_max_irq = 1020;
211 if (_gic_max_irq > ARM_GIC_NR_IRQS)
212 _gic_max_irq = ARM_GIC_NR_IRQS;
213
214 #ifndef RT_PRETENT_AS_CPU0
215 /* If we are run on the second core, the GIC should have already been setup
216 * by BootStrapProcessor. */
217 if ((rt_cpu_get_smp_id() & 0xF) != 0)
218 return 0;
219 #endif
220 #ifdef RT_USING_VMM
221 return 0;
222 #endif
223
224 cpumask |= cpumask << 8;
225 cpumask |= cpumask << 16;
226
227 GIC_DIST_CTRL(dist_base) = 0x0;
228
229 /* Set all global interrupts to be level triggered, active low. */
230 for (i = 32; i < _gic_max_irq; i += 16)
231 GIC_DIST_CONFIG(dist_base, i) = 0x0;
232
233 /* Set all global interrupts to this CPU only. */
234 for (i = 32; i < _gic_max_irq; i += 4)
235 GIC_DIST_TARGET(dist_base, i) = cpumask;
236
237 /* Set priority on all interrupts. */
238 for (i = 0; i < _gic_max_irq; i += 4)
239 GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
240
241 /* Disable all interrupts. */
242 for (i = 0; i < _gic_max_irq; i += 32)
243 GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
244 /* All interrupts defaults to IGROUP1(IRQ). */
245 for (i = 0; i < _gic_max_irq; i += 32)
246 GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
247
248 /* Enable group0 and group1 interrupt forwarding. */
249 GIC_DIST_CTRL(dist_base) = 0x03;
250
251 return 0;
252 }
253
arm_gic_cpu_init(rt_uint32_t index,rt_uint32_t cpu_base)254 int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
255 {
256 RT_ASSERT(index < ARM_GIC_MAX_NR);
257
258 _gic_table[index].cpu_hw_base = cpu_base;
259
260 #ifndef RT_PRETENT_AS_CPU0
261 /* If we are run on the second core, the GIC should have already been setup
262 * by BootStrapProcessor. */
263 if ((rt_cpu_get_smp_id() & 0xF) != 0)
264 return 0;
265 #endif
266 #ifdef RT_USING_VMM
267 return 0;
268 #endif
269
270 GIC_CPU_PRIMASK(cpu_base) = 0xf0;
271 /* Enable CPU interrupt */
272 GIC_CPU_CTRL(cpu_base) = 0x01;
273
274 return 0;
275 }
276
arm_gic_set_group(rt_uint32_t index,int vector,int group)277 void arm_gic_set_group(rt_uint32_t index, int vector, int group)
278 {
279 /* As for GICv2, there are only group0 and group1. */
280 RT_ASSERT(group <= 1);
281 RT_ASSERT(vector < _gic_max_irq);
282
283 if (group == 0)
284 {
285 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
286 vector) &= ~(1 << (vector % 32));
287 }
288 else if (group == 1)
289 {
290 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
291 vector) |= (1 << (vector % 32));
292 }
293 }
294
arm_gic_trigger(rt_uint32_t index,int target_cpu,int irq)295 void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq)
296 {
297 unsigned int reg;
298
299 RT_ASSERT(irq <= 15);
300 RT_ASSERT(target_cpu <= 255);
301
302 reg = (target_cpu << 16) | irq;
303 GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg;
304 }
305
arm_gic_clear_sgi(rt_uint32_t index,int target_cpu,int irq)306 void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq)
307 {
308 RT_ASSERT(irq <= 15);
309 RT_ASSERT(target_cpu <= 255);
310
311 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = target_cpu << (irq % 4);
312 }
313