1 /*
2 * File : mips_regs.h
3 * This file is part of RT-Thread RTOS
4 * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Change Logs:
21 * Date Author Notes
22 * 2016��9��7�� Urey the first version
23 */
24
25 #ifndef _MIPS_REGS_H_
26 #define _MIPS_REGS_H_
27
28
29 #if !defined(__ASSEMBLY__) && !defined(ASSEMBLY)
30 #include <rtdef.h>
31
32 #define MIPS_REG_NR 32
33 typedef struct {
34 rt_uint32_t regs[MIPS_REG_NR]; /* 32 ��ͨ��Ŀ�ļĴ��� */
35 rt_uint32_t CP0Status; /* CP0 Э������״̬�Ĵ��� */
36 rt_uint32_t CP0DataHI; /* ������λ�Ĵ��� */
37 rt_uint32_t CP0DataLO; /* ������λ�Ĵ��� */
38 rt_uint32_t CP0BadVAddr; /* �����ַ�Ĵ��� */
39 rt_uint32_t CP0Cause; /* �����жϻ����쳣�鿴�ļĴ���*/
40 rt_uint32_t CP0EPC; /* ����������Ĵ��� */
41 } mips_reg_ctx;
42
43 #define MIPS_ARG_REG_NR 4
44 typedef struct
45 {
46 rt_uint32_t args[MIPS_ARG_REG_NR]; /* 4 �������Ĵ��� */
47 } mips_arg_ctx;
48
49 struct linkctx
50 {
51 rt_uint32_t id;
52 struct linkctx *next;
53 };
54
55 struct fpctx
56 {
57 struct linkctx link;
58 rt_uint32_t fcsr;
59 rt_uint32_t reserved;
60 };
61
62
63 struct fp32ctx
64 {
65 struct fpctx fp;
66 union
67 {
68 double d[16]; /* even doubles */
69 float s[32]; /* even singles, padded */
70 };
71 };
72
73 struct fp64ctx
74 {
75 struct fpctx fp;
76 union
77 {
78 double d[32]; /* even doubles, followed by odd doubles */
79 float s[64]; /* even singles, followed by odd singles, padded */
80 };
81 };
82
83 #endif /* !defined(__ASSEMBLY__) && !defined(ASSEMBLY) */
84
85 #define MIPS_STK_CTX_WORD_SIZE 38
86 #define SZREG 4
87 /*********************************************************************************************************
88 MIPS �ļĴ�������
89 *********************************************************************************************************/
90 #define REG_ZERO 0 /* wired zero */
91 #define REG_AT 1 /* assembler temp */
92 #define REG_V0 2 /* return reg 0 */
93 #define REG_V1 3 /* return reg 1 */
94 #define REG_A0 4 /* arg reg 0 */
95 #define REG_A1 5 /* arg reg 1 */
96 #define REG_A2 6 /* arg reg 2 */
97 #define REG_A3 7 /* arg reg 3 */
98 #define REG_T0 8 /* caller saved 0 */
99 #define REG_T1 9 /* caller saved 1 */
100 #define REG_T2 10 /* caller saved 2 */
101 #define REG_T3 11 /* caller saved 3 */
102 #define REG_T4 12 /* caller saved 4 */
103 #define REG_T5 13 /* caller saved 5 */
104 #define REG_T6 14 /* caller saved 6 */
105 #define REG_T7 15 /* caller saved 7 */
106 #define REG_S0 16 /* callee saved 0 */
107 #define REG_S1 17 /* callee saved 1 */
108 #define REG_S2 18 /* callee saved 2 */
109 #define REG_S3 19 /* callee saved 3 */
110 #define REG_S4 20 /* callee saved 4 */
111 #define REG_S5 21 /* callee saved 5 */
112 #define REG_S6 22 /* callee saved 6 */
113 #define REG_S7 23 /* callee saved 7 */
114 #define REG_T8 24 /* caller saved 8 */
115 #define REG_T9 25 /* caller saved 9 */
116 #define REG_K0 26 /* kernel temp 0 */
117 #define REG_K1 27 /* kernel temp 1 */
118 #define REG_GP 28 /* global pointer */
119 #define REG_SP 29 /* stack pointer */
120 #define REG_S8 30 /* callee saved 8 */
121 #define REG_FP REG_S8 /* callee saved 8 */
122 #define REG_RA 31 /* return address */
123
124 #define STK_CTX_SIZE (MIPS_STK_CTX_WORD_SIZE * SZREG)
125 #define STK_OFFSET_SR ((32 + 0) * SZREG)
126 #define STK_OFFSET_HI ((32 + 1) * SZREG)
127 #define STK_OFFSET_LO ((32 + 2) * SZREG)
128 #define STK_OFFSET_BADVADDR ((32 + 3) * SZREG)
129 #define STK_OFFSET_CAUSE ((32 + 4) * SZREG)
130 #define STK_OFFSET_EPC ((32 + 5) * SZREG)
131
132 #define STK_OFFSET_LAST ((MIPS_STK_CTX_WORD_SIZE - 1) * SZREG)
133
134 #define FP32CTX_CSR ((SZREG)*2)
135 #define FP64CTX_CSR ((SZREG)*2)
136
137 #define LINKCTX_ID ((SZREG)*0)
138 #define LINKCTX_NEXT ((SZREG)*1)
139 #define LINKCTX_TYPE_MSA 0x004D5341
140 #define LINKCTX_TYPE_FP32 0x46503332
141 #define LINKCTX_TYPE_FP64 0x46503634
142 #define LINKCTX_TYPE_FMSA 0x463D5341
143 #define LINKCTX_TYPE_DSP 0x00445350
144 #define LINKCTX_TYPE_STKSWP 0x53574150
145 #define LINKCTX_TYPE_XPA 0x00585041
146
147 #define FP32CTX_0 ((SZREG)*4)
148 #define FP32CTX_2 (FP32CTX_0 + (1 * 8))
149 #define FP32CTX_4 (FP32CTX_0 + (2 * 8))
150 #define FP32CTX_6 (FP32CTX_0 + (3 * 8))
151 #define FP32CTX_8 (FP32CTX_0 + (4 * 8))
152 #define FP32CTX_10 (FP32CTX_0 + (5 * 8))
153 #define FP32CTX_12 (FP32CTX_0 + (6 * 8))
154 #define FP32CTX_14 (FP32CTX_0 + (7 * 8))
155 #define FP32CTX_16 (FP32CTX_0 + (8 * 8))
156 #define FP32CTX_18 (FP32CTX_0 + (9 * 8))
157 #define FP32CTX_20 (FP32CTX_0 + (10 * 8))
158 #define FP32CTX_22 (FP32CTX_0 + (11 * 8))
159 #define FP32CTX_24 (FP32CTX_0 + (12 * 8))
160 #define FP32CTX_26 (FP32CTX_0 + (13 * 8))
161 #define FP32CTX_28 (FP32CTX_0 + (14 * 8))
162 #define FP32CTX_30 (FP32CTX_0 + (15 * 8))
163 #define FP32CTX_SIZE (FP32CTX_30 + (17 * 8))
164
165 #define FP64CTX_0 ((SZREG)*4)
166 #define FP64CTX_2 (FP64CTX_0 + (1 * 8))
167 #define FP64CTX_4 (FP64CTX_0 + (2 * 8))
168 #define FP64CTX_6 (FP64CTX_0 + (3 * 8))
169 #define FP64CTX_8 (FP64CTX_0 + (4 * 8))
170 #define FP64CTX_10 (FP64CTX_0 + (5 * 8))
171 #define FP64CTX_12 (FP64CTX_0 + (6 * 8))
172 #define FP64CTX_14 (FP64CTX_0 + (7 * 8))
173 #define FP64CTX_16 (FP64CTX_0 + (8 * 8))
174 #define FP64CTX_18 (FP64CTX_0 + (9 * 8))
175 #define FP64CTX_20 (FP64CTX_0 + (10 * 8))
176 #define FP64CTX_22 (FP64CTX_0 + (11 * 8))
177 #define FP64CTX_24 (FP64CTX_0 + (12 * 8))
178 #define FP64CTX_26 (FP64CTX_0 + (13 * 8))
179 #define FP64CTX_28 (FP64CTX_0 + (14 * 8))
180 #define FP64CTX_30 (FP64CTX_0 + (15 * 8))
181 #define FP64CTX_1 (FP64CTX_30 + (1 * 8))
182 #define FP64CTX_3 (FP64CTX_30 + (2 * 8))
183 #define FP64CTX_5 (FP64CTX_30 + (3 * 8))
184 #define FP64CTX_7 (FP64CTX_30 + (4 * 8))
185 #define FP64CTX_9 (FP64CTX_30 + (5 * 8))
186 #define FP64CTX_11 (FP64CTX_30 + (6 * 8))
187 #define FP64CTX_13 (FP64CTX_30 + (7 * 8))
188 #define FP64CTX_15 (FP64CTX_30 + (8 * 8))
189 #define FP64CTX_17 (FP64CTX_30 + (9 * 8))
190 #define FP64CTX_19 (FP64CTX_30 + (10 * 8))
191 #define FP64CTX_21 (FP64CTX_30 + (11 * 8))
192 #define FP64CTX_23 (FP64CTX_30 + (12 * 8))
193 #define FP64CTX_25 (FP64CTX_30 + (13 * 8))
194 #define FP64CTX_27 (FP64CTX_30 + (14 * 8))
195 #define FP64CTX_29 (FP64CTX_30 + (15 * 8))
196 #define FP64CTX_31 (FP64CTX_30 + (16 * 8))
197 #define FP64CTX_SIZE (FP64CTX_31 + (17 * 8))
198
199 #define FPCTX_SIZE() (mips_getsr() & ST0_FR ? FP64CTX_SIZE : FP32CTX_SIZE)
200
201 /*
202 * The following macros are especially useful for __asm__
203 * inline assembler.
204 */
205 #ifndef __STR
206 #define __STR(x) #x
207 #endif
208 #ifndef STR
209 #define STR(x) __STR(x)
210 #endif
211
212 /*
213 * Configure language
214 */
215 #ifdef __ASSEMBLY__
216 #define _ULCAST_
217 #else
218 #define _ULCAST_ (unsigned long)
219 #endif
220
221 /*
222 * Coprocessor 0 register names
223 */
224 #define CP0_INDEX $0
225 #define CP0_RANDOM $1
226 #define CP0_ENTRYLO0 $2
227 #define CP0_ENTRYLO1 $3
228 #define CP0_CONF $3
229 #define CP0_CONTEXT $4
230 #define CP0_PAGEMASK $5
231 #define CP0_WIRED $6
232 #define CP0_INFO $7
233 #define CP0_BADVADDR $8
234 #define CP0_COUNT $9
235 #define CP0_ENTRYHI $10
236 #define CP0_COMPARE $11
237 #define CP0_STATUS $12
238 #define CP0_CAUSE $13
239 #define CP0_EPC $14
240 #define CP0_PRID $15
241 #define CP0_CONFIG $16
242 #define CP0_LLADDR $17
243 #define CP0_WATCHLO $18
244 #define CP0_WATCHHI $19
245 #define CP0_XCONTEXT $20
246 #define CP0_FRAMEMASK $21
247 #define CP0_DIAGNOSTIC $22
248 #define CP0_DEBUG $23
249 #define CP0_DEPC $24
250 #define CP0_PERFORMANCE $25
251 #define CP0_ECC $26
252 #define CP0_CACHEERR $27
253 #define CP0_TAGLO $28
254 #define CP0_TAGHI $29
255 #define CP0_ERROREPC $30
256 #define CP0_DESAVE $31
257
258 /*
259 * R4640/R4650 cp0 register names. These registers are listed
260 * here only for completeness; without MMU these CPUs are not useable
261 * by Linux. A future ELKS port might take make Linux run on them
262 * though ...
263 */
264 #define CP0_IBASE $0
265 #define CP0_IBOUND $1
266 #define CP0_DBASE $2
267 #define CP0_DBOUND $3
268 #define CP0_CALG $17
269 #define CP0_IWATCH $18
270 #define CP0_DWATCH $19
271
272 /*
273 * Coprocessor 0 Set 1 register names
274 */
275 #define CP0_S1_DERRADDR0 $26
276 #define CP0_S1_DERRADDR1 $27
277 #define CP0_S1_INTCONTROL $20
278
279 /*
280 * TX39 Series
281 */
282 #define CP0_TX39_CACHE $7
283
284 /*
285 * Coprocessor 1 (FPU) register names
286 */
287 #define CP1_REVISION $0
288 #define CP1_STATUS $31
289
290 /*
291 * FPU Status Register Values
292 */
293 /*
294 * Status Register Values
295 */
296
297 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
298 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
299 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
300 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
301 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
302 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
303 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
304 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
305 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
306 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
307
308 /*
309 * X the exception cause indicator
310 * E the exception enable
311 * S the sticky/flag bit
312 */
313 #define FPU_CSR_ALL_X 0x0003f000
314 #define FPU_CSR_UNI_X 0x00020000
315 #define FPU_CSR_INV_X 0x00010000
316 #define FPU_CSR_DIV_X 0x00008000
317 #define FPU_CSR_OVF_X 0x00004000
318 #define FPU_CSR_UDF_X 0x00002000
319 #define FPU_CSR_INE_X 0x00001000
320
321 #define FPU_CSR_ALL_E 0x00000f80
322 #define FPU_CSR_INV_E 0x00000800
323 #define FPU_CSR_DIV_E 0x00000400
324 #define FPU_CSR_OVF_E 0x00000200
325 #define FPU_CSR_UDF_E 0x00000100
326 #define FPU_CSR_INE_E 0x00000080
327
328 #define FPU_CSR_ALL_S 0x0000007c
329 #define FPU_CSR_INV_S 0x00000040
330 #define FPU_CSR_DIV_S 0x00000020
331 #define FPU_CSR_OVF_S 0x00000010
332 #define FPU_CSR_UDF_S 0x00000008
333 #define FPU_CSR_INE_S 0x00000004
334
335 /* rounding mode */
336 #define FPU_CSR_RN 0x0 /* nearest */
337 #define FPU_CSR_RZ 0x1 /* towards zero */
338 #define FPU_CSR_RU 0x2 /* towards +Infinity */
339 #define FPU_CSR_RD 0x3 /* towards -Infinity */
340
341
342 /*
343 * Values for PageMask register
344 */
345 #ifdef CONFIG_CPU_VR41XX
346
347 /* Why doesn't stupidity hurt ... */
348
349 #define PM_1K 0x00000000
350 #define PM_4K 0x00001800
351 #define PM_16K 0x00007800
352 #define PM_64K 0x0001f800
353 #define PM_256K 0x0007f800
354
355 #else
356
357 #define PM_4K 0x00000000
358 #define PM_16K 0x00006000
359 #define PM_64K 0x0001e000
360 #define PM_256K 0x0007e000
361 #define PM_1M 0x001fe000
362 #define PM_4M 0x007fe000
363 #define PM_16M 0x01ffe000
364 #define PM_64M 0x07ffe000
365 #define PM_256M 0x1fffe000
366
367 #endif
368
369 /*
370 * Values used for computation of new tlb entries
371 */
372 #define PL_4K 12
373 #define PL_16K 14
374 #define PL_64K 16
375 #define PL_256K 18
376 #define PL_1M 20
377 #define PL_4M 22
378 #define PL_16M 24
379 #define PL_64M 26
380 #define PL_256M 28
381
382 /*
383 * R4x00 interrupt enable / cause bits
384 */
385 #define IE_SW0 (_ULCAST_(1) << 8)
386 #define IE_SW1 (_ULCAST_(1) << 9)
387 #define IE_IRQ0 (_ULCAST_(1) << 10)
388 #define IE_IRQ1 (_ULCAST_(1) << 11)
389 #define IE_IRQ2 (_ULCAST_(1) << 12)
390 #define IE_IRQ3 (_ULCAST_(1) << 13)
391 #define IE_IRQ4 (_ULCAST_(1) << 14)
392 #define IE_IRQ5 (_ULCAST_(1) << 15)
393
394 /*
395 * R4x00 interrupt cause bits
396 */
397 #define C_SW0 (_ULCAST_(1) << 8)
398 #define C_SW1 (_ULCAST_(1) << 9)
399 #define C_IRQ0 (_ULCAST_(1) << 10)
400 #define C_IRQ1 (_ULCAST_(1) << 11)
401 #define C_IRQ2 (_ULCAST_(1) << 12)
402 #define C_IRQ3 (_ULCAST_(1) << 13)
403 #define C_IRQ4 (_ULCAST_(1) << 14)
404 #define C_IRQ5 (_ULCAST_(1) << 15)
405
406 /*
407 * Bitfields in the R4xx0 cp0 status register
408 */
409 #define ST0_IE 0x00000001
410 #define ST0_EXL 0x00000002
411 #define ST0_ERL 0x00000004
412 #define ST0_KSU 0x00000018
413 # define KSU_USER 0x00000010
414 # define KSU_SUPERVISOR 0x00000008
415 # define KSU_KERNEL 0x00000000
416 #define ST0_UX 0x00000020
417 #define ST0_SX 0x00000040
418 #define ST0_KX 0x00000080
419 #define ST0_DE 0x00010000
420 #define ST0_CE 0x00020000
421
422 /*
423 * Bitfields in the R[23]000 cp0 status register.
424 */
425 #define ST0_IEC 0x00000001
426 #define ST0_KUC 0x00000002
427 #define ST0_IEP 0x00000004
428 #define ST0_KUP 0x00000008
429 #define ST0_IEO 0x00000010
430 #define ST0_KUO 0x00000020
431 /* bits 6 & 7 are reserved on R[23]000 */
432 #define ST0_ISC 0x00010000
433 #define ST0_SWC 0x00020000
434 #define ST0_CM 0x00080000
435
436 /*
437 * Bits specific to the R4640/R4650
438 */
439 #define ST0_UM (_ULCAST_(1) << 4)
440 #define ST0_IL (_ULCAST_(1) << 23)
441 #define ST0_DL (_ULCAST_(1) << 24)
442
443 /*
444 * Bitfields in the TX39 family CP0 Configuration Register 3
445 */
446 #define TX39_CONF_ICS_SHIFT 19
447 #define TX39_CONF_ICS_MASK 0x00380000
448 #define TX39_CONF_ICS_1KB 0x00000000
449 #define TX39_CONF_ICS_2KB 0x00080000
450 #define TX39_CONF_ICS_4KB 0x00100000
451 #define TX39_CONF_ICS_8KB 0x00180000
452 #define TX39_CONF_ICS_16KB 0x00200000
453
454 #define TX39_CONF_DCS_SHIFT 16
455 #define TX39_CONF_DCS_MASK 0x00070000
456 #define TX39_CONF_DCS_1KB 0x00000000
457 #define TX39_CONF_DCS_2KB 0x00010000
458 #define TX39_CONF_DCS_4KB 0x00020000
459 #define TX39_CONF_DCS_8KB 0x00030000
460 #define TX39_CONF_DCS_16KB 0x00040000
461
462 #define TX39_CONF_CWFON 0x00004000
463 #define TX39_CONF_WBON 0x00002000
464 #define TX39_CONF_RF_SHIFT 10
465 #define TX39_CONF_RF_MASK 0x00000c00
466 #define TX39_CONF_DOZE 0x00000200
467 #define TX39_CONF_HALT 0x00000100
468 #define TX39_CONF_LOCK 0x00000080
469 #define TX39_CONF_ICE 0x00000020
470 #define TX39_CONF_DCE 0x00000010
471 #define TX39_CONF_IRSIZE_SHIFT 2
472 #define TX39_CONF_IRSIZE_MASK 0x0000000c
473 #define TX39_CONF_DRSIZE_SHIFT 0
474 #define TX39_CONF_DRSIZE_MASK 0x00000003
475
476 /*
477 * Status register bits available in all MIPS CPUs.
478 */
479 #define ST0_IM 0x0000ff00
480 #define STATUSB_IP0 8
481 #define STATUSF_IP0 (_ULCAST_(1) << 8)
482 #define STATUSB_IP1 9
483 #define STATUSF_IP1 (_ULCAST_(1) << 9)
484 #define STATUSB_IP2 10
485 #define STATUSF_IP2 (_ULCAST_(1) << 10)
486 #define STATUSB_IP3 11
487 #define STATUSF_IP3 (_ULCAST_(1) << 11)
488 #define STATUSB_IP4 12
489 #define STATUSF_IP4 (_ULCAST_(1) << 12)
490 #define STATUSB_IP5 13
491 #define STATUSF_IP5 (_ULCAST_(1) << 13)
492 #define STATUSB_IP6 14
493 #define STATUSF_IP6 (_ULCAST_(1) << 14)
494 #define STATUSB_IP7 15
495 #define STATUSF_IP7 (_ULCAST_(1) << 15)
496 #define STATUSB_IP8 0
497 #define STATUSF_IP8 (_ULCAST_(1) << 0)
498 #define STATUSB_IP9 1
499 #define STATUSF_IP9 (_ULCAST_(1) << 1)
500 #define STATUSB_IP10 2
501 #define STATUSF_IP10 (_ULCAST_(1) << 2)
502 #define STATUSB_IP11 3
503 #define STATUSF_IP11 (_ULCAST_(1) << 3)
504 #define STATUSB_IP12 4
505 #define STATUSF_IP12 (_ULCAST_(1) << 4)
506 #define STATUSB_IP13 5
507 #define STATUSF_IP13 (_ULCAST_(1) << 5)
508 #define STATUSB_IP14 6
509 #define STATUSF_IP14 (_ULCAST_(1) << 6)
510 #define STATUSB_IP15 7
511 #define STATUSF_IP15 (_ULCAST_(1) << 7)
512 #define ST0_CH 0x00040000
513 #define ST0_SR 0x00100000
514 #define ST0_TS 0x00200000
515 #define ST0_BEV 0x00400000
516 #define ST0_RE 0x02000000
517 #define ST0_FR 0x04000000
518 #define ST0_CU 0xf0000000
519 #define ST0_CU0 0x10000000
520 #define ST0_CU1 0x20000000
521 #define ST0_CU1_SHIFT 29
522 #define ST0_CU2 0x40000000
523 #define ST0_CU3 0x80000000
524 #define ST0_XX 0x80000000 /* MIPS IV naming */
525
526 /*
527 * Bitfields and bit numbers in the coprocessor 0 cause register.
528 *
529 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
530 */
531 #define CAUSEB_EXCCODE 2
532 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
533 #define CAUSEB_IP 8
534 #define CAUSEF_IP (_ULCAST_(255) << 8)
535 #define CAUSEB_IP0 8
536 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
537 #define CAUSEB_IP1 9
538 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
539 #define CAUSEB_IP2 10
540 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
541 #define CAUSEB_IP3 11
542 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
543 #define CAUSEB_IP4 12
544 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
545 #define CAUSEB_IP5 13
546 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
547 #define CAUSEB_IP6 14
548 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
549 #define CAUSEB_IP7 15
550 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
551 #define CAUSEB_IV 23
552 #define CAUSEF_IV (_ULCAST_(1) << 23)
553 #define CAUSEB_CE 28
554 #define CAUSEF_CE (_ULCAST_(3) << 28)
555 #define CAUSEB_BD 31
556 #define CAUSEF_BD (_ULCAST_(1) << 31)
557
558 /*
559 * Bits in the coprocessor 0 config register.
560 */
561 /* Generic bits. */
562 #define CONF_CM_CACHABLE_NO_WA 0
563 #define CONF_CM_CACHABLE_WA 1
564 #define CONF_CM_UNCACHED 2
565 #define CONF_CM_CACHABLE_NONCOHERENT 3
566 #define CONF_CM_CACHABLE_CE 4
567 #define CONF_CM_CACHABLE_COW 5
568 #define CONF_CM_CACHABLE_CUW 6
569 #define CONF_CM_CACHABLE_ACCELERATED 7
570 #define CONF_CM_CMASK 7
571 #define CONF_BE (_ULCAST_(1) << 15)
572
573 /* Bits common to various processors. */
574 #define CONF_CU (_ULCAST_(1) << 3)
575 #define CONF_DB (_ULCAST_(1) << 4)
576 #define CONF_IB (_ULCAST_(1) << 5)
577 #define CONF_DC (_ULCAST_(7) << 6)
578 #define CONF_IC (_ULCAST_(7) << 9)
579 #define CONF_EB (_ULCAST_(1) << 13)
580 #define CONF_EM (_ULCAST_(1) << 14)
581 #define CONF_SM (_ULCAST_(1) << 16)
582 #define CONF_SC (_ULCAST_(1) << 17)
583 #define CONF_EW (_ULCAST_(3) << 18)
584 #define CONF_EP (_ULCAST_(15)<< 24)
585 #define CONF_EC (_ULCAST_(7) << 28)
586 #define CONF_CM (_ULCAST_(1) << 31)
587
588 /* Bits specific to the R4xx0. */
589 #define R4K_CONF_SW (_ULCAST_(1) << 20)
590 #define R4K_CONF_SS (_ULCAST_(1) << 21)
591 #define R4K_CONF_SB (_ULCAST_(3) << 22)
592
593 /* Bits specific to the R5000. */
594 #define R5K_CONF_SE (_ULCAST_(1) << 12)
595 #define R5K_CONF_SS (_ULCAST_(3) << 20)
596
597 /* Bits specific to the R10000. */
598 #define R10K_CONF_DN (_ULCAST_(3) << 3)
599 #define R10K_CONF_CT (_ULCAST_(1) << 5)
600 #define R10K_CONF_PE (_ULCAST_(1) << 6)
601 #define R10K_CONF_PM (_ULCAST_(3) << 7)
602 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
603 #define R10K_CONF_SB (_ULCAST_(1) << 13)
604 #define R10K_CONF_SK (_ULCAST_(1) << 14)
605 #define R10K_CONF_SS (_ULCAST_(7) << 16)
606 #define R10K_CONF_SC (_ULCAST_(7) << 19)
607 #define R10K_CONF_DC (_ULCAST_(7) << 26)
608 #define R10K_CONF_IC (_ULCAST_(7) << 29)
609
610 /* Bits specific to the VR41xx. */
611 #define VR41_CONF_CS (_ULCAST_(1) << 12)
612 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
613 #define VR41_CONF_AD (_ULCAST_(1) << 23)
614
615 /* Bits specific to the R30xx. */
616 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
617 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
618 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
619 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
620 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
621 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
622 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
623 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
624 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
625
626 /* Bits specific to the TX49. */
627 #define TX49_CONF_DC (_ULCAST_(1) << 16)
628 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
629 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
630 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
631
632 /* Bits specific to the MIPS32/64 PRA. */
633 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
634 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
635 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
636 #define MIPS_CONF_M (_ULCAST_(1) << 31)
637
638 /*
639 * R10000 performance counter definitions.
640 *
641 * FIXME: The R10000 performance counter opens a nice way to implement CPU
642 * time accounting with a precission of one cycle. I don't have
643 * R10000 silicon but just a manual, so ...
644 */
645
646 /*
647 * Events counted by counter #0
648 */
649 #define CE0_CYCLES 0
650 #define CE0_INSN_ISSUED 1
651 #define CE0_LPSC_ISSUED 2
652 #define CE0_S_ISSUED 3
653 #define CE0_SC_ISSUED 4
654 #define CE0_SC_FAILED 5
655 #define CE0_BRANCH_DECODED 6
656 #define CE0_QW_WB_SECONDARY 7
657 #define CE0_CORRECTED_ECC_ERRORS 8
658 #define CE0_ICACHE_MISSES 9
659 #define CE0_SCACHE_I_MISSES 10
660 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
661 #define CE0_EXT_INTERVENTIONS_REQ 12
662 #define CE0_EXT_INVALIDATE_REQ 13
663 #define CE0_VIRTUAL_COHERENCY_COND 14
664 #define CE0_INSN_GRADUATED 15
665
666 /*
667 * Events counted by counter #1
668 */
669 #define CE1_CYCLES 0
670 #define CE1_INSN_GRADUATED 1
671 #define CE1_LPSC_GRADUATED 2
672 #define CE1_S_GRADUATED 3
673 #define CE1_SC_GRADUATED 4
674 #define CE1_FP_INSN_GRADUATED 5
675 #define CE1_QW_WB_PRIMARY 6
676 #define CE1_TLB_REFILL 7
677 #define CE1_BRANCH_MISSPREDICTED 8
678 #define CE1_DCACHE_MISS 9
679 #define CE1_SCACHE_D_MISSES 10
680 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
681 #define CE1_EXT_INTERVENTION_HITS 12
682 #define CE1_EXT_INVALIDATE_REQ 13
683 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
684 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
685
686 /*
687 * These flags define in which priviledge mode the counters count events
688 */
689 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
690 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
691 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
692 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
693
694 #ifndef __ASSEMBLY__
695
696 #define CAUSE_EXCCODE(x) ((CAUSEF_EXCCODE & (x->cp0_cause)) >> CAUSEB_EXCCODE)
697 #define CAUSE_EPC(x) (x->cp0_epc + (((x->cp0_cause & CAUSEF_BD) >> CAUSEB_BD) << 2))
698
699 /*
700 * Functions to access the r10k performance counter and control registers
701 */
702 #define read_r10k_perf_cntr(counter) \
703 ({ unsigned int __res; \
704 __asm__ __volatile__( \
705 "mfpc\t%0, "STR(counter) \
706 : "=r" (__res)); \
707 __res;})
708
709 #define write_r10k_perf_cntr(counter,val) \
710 __asm__ __volatile__( \
711 "mtpc\t%0, "STR(counter) \
712 : : "r" (val));
713
714 #define read_r10k_perf_cntl(counter) \
715 ({ unsigned int __res; \
716 __asm__ __volatile__( \
717 "mfps\t%0, "STR(counter) \
718 : "=r" (__res)); \
719 __res;})
720
721 #define write_r10k_perf_cntl(counter,val) \
722 __asm__ __volatile__( \
723 "mtps\t%0, "STR(counter) \
724 : : "r" (val));
725
726 /*
727 * Macros to access the system control coprocessor
728 */
729
730 #define __read_32bit_c0_register(source, sel) \
731 ({ int __res; \
732 if (sel == 0) \
733 __asm__ __volatile__( \
734 "mfc0\t%0, " #source "\n\t" \
735 : "=r" (__res)); \
736 else \
737 __asm__ __volatile__( \
738 ".set\tmips32\n\t" \
739 "mfc0\t%0, " #source ", " #sel "\n\t" \
740 ".set\tmips0\n\t" \
741 : "=r" (__res)); \
742 __res; \
743 })
744
745 #define __read_64bit_c0_register(source, sel) \
746 ({ unsigned long __res; \
747 if (sel == 0) \
748 __asm__ __volatile__( \
749 ".set\tmips3\n\t" \
750 "dmfc0\t%0, " #source "\n\t" \
751 ".set\tmips0" \
752 : "=r" (__res)); \
753 else \
754 __asm__ __volatile__( \
755 ".set\tmips64\n\t" \
756 "dmfc0\t%0, " #source ", " #sel "\n\t" \
757 ".set\tmips0" \
758 : "=r" (__res)); \
759 __res; \
760 })
761
762 #define __write_32bit_c0_register(register, sel, value) \
763 do { \
764 if (sel == 0) \
765 __asm__ __volatile__( \
766 "mtc0\t%z0, " #register "\n\t" \
767 : : "Jr" (value)); \
768 else \
769 __asm__ __volatile__( \
770 ".set\tmips32\n\t" \
771 "mtc0\t%z0, " #register ", " #sel "\n\t" \
772 ".set\tmips0" \
773 : : "Jr" (value)); \
774 } while (0)
775
776 #define __write_64bit_c0_register(register, sel, value) \
777 do { \
778 if (sel == 0) \
779 __asm__ __volatile__( \
780 ".set\tmips3\n\t" \
781 "dmtc0\t%z0, " #register "\n\t" \
782 ".set\tmips0" \
783 : : "Jr" (value)); \
784 else \
785 __asm__ __volatile__( \
786 ".set\tmips64\n\t" \
787 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
788 ".set\tmips0" \
789 : : "Jr" (value)); \
790 } while (0)
791
792 #define __read_ulong_c0_register(reg, sel) \
793 ((sizeof(unsigned long) == 4) ? \
794 __read_32bit_c0_register(reg, sel) : \
795 __read_64bit_c0_register(reg, sel))
796
797 #define __write_ulong_c0_register(reg, sel, val) \
798 do { \
799 if (sizeof(unsigned long) == 4) \
800 __write_32bit_c0_register(reg, sel, val); \
801 else \
802 __write_64bit_c0_register(reg, sel, val); \
803 } while (0)
804
805 /*
806 * These versions are only needed for systems with more than 38 bits of
807 * physical address space running the 32-bit kernel. That's none atm :-)
808 */
809 #define __read_64bit_c0_split(source, sel) \
810 ({ \
811 unsigned long long val; \
812 unsigned long flags; \
813 \
814 local_irq_save(flags); \
815 if (sel == 0) \
816 __asm__ __volatile__( \
817 ".set\tmips64\n\t" \
818 "dmfc0\t%M0, " #source "\n\t" \
819 "dsll\t%L0, %M0, 32\n\t" \
820 "dsrl\t%M0, %M0, 32\n\t" \
821 "dsrl\t%L0, %L0, 32\n\t" \
822 ".set\tmips0" \
823 : "=r" (val)); \
824 else \
825 __asm__ __volatile__( \
826 ".set\tmips64\n\t" \
827 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
828 "dsll\t%L0, %M0, 32\n\t" \
829 "dsrl\t%M0, %M0, 32\n\t" \
830 "dsrl\t%L0, %L0, 32\n\t" \
831 ".set\tmips0" \
832 : "=r" (val)); \
833 local_irq_restore(flags); \
834 \
835 val; \
836 })
837
838 #define __write_64bit_c0_split(source, sel, val) \
839 do { \
840 unsigned long flags; \
841 \
842 local_irq_save(flags); \
843 if (sel == 0) \
844 __asm__ __volatile__( \
845 ".set\tmips64\n\t" \
846 "dsll\t%L0, %L0, 32\n\t" \
847 "dsrl\t%L0, %L0, 32\n\t" \
848 "dsll\t%M0, %M0, 32\n\t" \
849 "or\t%L0, %L0, %M0\n\t" \
850 "dmtc0\t%L0, " #source "\n\t" \
851 ".set\tmips0" \
852 : : "r" (val)); \
853 else \
854 __asm__ __volatile__( \
855 ".set\tmips64\n\t" \
856 "dsll\t%L0, %L0, 32\n\t" \
857 "dsrl\t%L0, %L0, 32\n\t" \
858 "dsll\t%M0, %M0, 32\n\t" \
859 "or\t%L0, %L0, %M0\n\t" \
860 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
861 ".set\tmips0" \
862 : : "r" (val)); \
863 local_irq_restore(flags); \
864 } while (0)
865
866 #define read_c0_index() __read_32bit_c0_register($0, 0)
867 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
868
869 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
870 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
871
872 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
873 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
874
875 #define read_c0_conf() __read_32bit_c0_register($3, 0)
876 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
877
878 #define read_c0_context() __read_ulong_c0_register($4, 0)
879 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
880
881 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
882 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
883
884 #define read_c0_wired() __read_32bit_c0_register($6, 0)
885 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
886
887 #define read_c0_info() __read_32bit_c0_register($7, 0)
888
889 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
890 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
891
892 #define read_c0_count() __read_32bit_c0_register($9, 0)
893 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
894
895 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
896 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
897
898 #define read_c0_compare() __read_32bit_c0_register($11, 0)
899 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
900
901 #define read_c0_status() __read_32bit_c0_register($12, 0)
902 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
903
904 #define read_c0_cause() __read_32bit_c0_register($13, 0)
905 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
906
907 #define read_c0_prid() __read_32bit_c0_register($15, 0)
908
909 #define read_c0_config() __read_32bit_c0_register($16, 0)
910 #define read_c0_config1() __read_32bit_c0_register($16, 1)
911 #define read_c0_config2() __read_32bit_c0_register($16, 2)
912 #define read_c0_config3() __read_32bit_c0_register($16, 3)
913 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
914 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
915 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
916 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
917
918 /*
919 * The WatchLo register. There may be upto 8 of them.
920 */
921 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
922 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
923 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
924 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
925 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
926 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
927 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
928 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
929 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
930 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
931 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
932 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
933 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
934 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
935 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
936 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
937
938 /*
939 * The WatchHi register. There may be upto 8 of them.
940 */
941 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
942 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
943 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
944 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
945 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
946 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
947 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
948 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
949
950 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
951 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
952 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
953 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
954 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
955 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
956 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
957 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
958
959 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
960 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
961
962 #define read_c0_intcontrol() __read_32bit_c0_register($20, 1)
963 #define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val)
964
965 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
966 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
967
968 #define read_c0_debug() __read_32bit_c0_register($23, 0)
969 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
970
971 #define read_c0_depc() __read_ulong_c0_register($24, 0)
972 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
973
974 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
975 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
976
977 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
978 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
979
980 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
981
982 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
983 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
984
985 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
986 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
987
988 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
989 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
990
991 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
992 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
993
994 #define read_c0_epc() __read_ulong_c0_register($14, 0)
995 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
996
997 #if 1
998 /*
999 * Macros to access the system control coprocessor
1000 */
1001 #define read_32bit_cp0_register(source) \
1002 ({ int __res; \
1003 __asm__ __volatile__( \
1004 ".set\tpush\n\t" \
1005 ".set\treorder\n\t" \
1006 "mfc0\t%0,"STR(source)"\n\t" \
1007 ".set\tpop" \
1008 : "=r" (__res)); \
1009 __res;})
1010
1011 #define read_32bit_cp0_set1_register(source) \
1012 ({ int __res; \
1013 __asm__ __volatile__( \
1014 ".set\tpush\n\t" \
1015 ".set\treorder\n\t" \
1016 "cfc0\t%0,"STR(source)"\n\t" \
1017 ".set\tpop" \
1018 : "=r" (__res)); \
1019 __res;})
1020
1021 /*
1022 * For now use this only with interrupts disabled!
1023 */
1024 #define read_64bit_cp0_register(source) \
1025 ({ int __res; \
1026 __asm__ __volatile__( \
1027 ".set\tmips3\n\t" \
1028 "dmfc0\t%0,"STR(source)"\n\t" \
1029 ".set\tmips0" \
1030 : "=r" (__res)); \
1031 __res;})
1032
1033 #define write_32bit_cp0_register(register,value) \
1034 __asm__ __volatile__( \
1035 "mtc0\t%0,"STR(register)"\n\t" \
1036 "nop" \
1037 : : "r" (value));
1038
1039 #define write_32bit_cp0_set1_register(register,value) \
1040 __asm__ __volatile__( \
1041 "ctc0\t%0,"STR(register)"\n\t" \
1042 "nop" \
1043 : : "r" (value));
1044
1045 #define write_64bit_cp0_register(register,value) \
1046 __asm__ __volatile__( \
1047 ".set\tmips3\n\t" \
1048 "dmtc0\t%0,"STR(register)"\n\t" \
1049 ".set\tmips0" \
1050 : : "r" (value))
1051
1052 /*
1053 * This should be changed when we get a compiler that support the MIPS32 ISA.
1054 */
1055 #define read_mips32_cp0_config1() \
1056 ({ int __res; \
1057 __asm__ __volatile__( \
1058 ".set\tnoreorder\n\t" \
1059 ".set\tnoat\n\t" \
1060 "#.set\tmips64\n\t" \
1061 "#mfc0\t$1, $16, 1\n\t" \
1062 "#.set\tmips0\n\t" \
1063 ".word\t0x40018001\n\t" \
1064 "move\t%0,$1\n\t" \
1065 ".set\tat\n\t" \
1066 ".set\treorder" \
1067 :"=r" (__res)); \
1068 __res;})
1069
1070 #endif
1071 /*
1072 * Macros to access the floating point coprocessor control registers
1073 */
1074 #define read_32bit_cp1_register(source) \
1075 ({ int __res; \
1076 __asm__ __volatile__( \
1077 ".set\tpush\n\t" \
1078 ".set\treorder\n\t" \
1079 "cfc1\t%0,"STR(source)"\n\t" \
1080 ".set\tpop" \
1081 : "=r" (__res)); \
1082 __res;})
1083
1084 /* TLB operations. */
tlb_probe(void)1085 static inline void tlb_probe(void)
1086 {
1087 __asm__ __volatile__(
1088 ".set noreorder\n\t"
1089 "tlbp\n\t"
1090 ".set reorder");
1091 }
1092
tlb_read(void)1093 static inline void tlb_read(void)
1094 {
1095 __asm__ __volatile__(
1096 ".set noreorder\n\t"
1097 "tlbr\n\t"
1098 ".set reorder");
1099 }
1100
tlb_write_indexed(void)1101 static inline void tlb_write_indexed(void)
1102 {
1103 __asm__ __volatile__(
1104 ".set noreorder\n\t"
1105 "tlbwi\n\t"
1106 ".set reorder");
1107 }
1108
tlb_write_random(void)1109 static inline void tlb_write_random(void)
1110 {
1111 __asm__ __volatile__(
1112 ".set noreorder\n\t"
1113 "tlbwr\n\t"
1114 ".set reorder");
1115 }
1116
1117 /*
1118 * Manipulate bits in a c0 register.
1119 */
1120 #define __BUILD_SET_C0(name,register) \
1121 static inline unsigned int \
1122 set_c0_##name(unsigned int set) \
1123 { \
1124 unsigned int res; \
1125 \
1126 res = read_c0_##name(); \
1127 res |= set; \
1128 write_c0_##name(res); \
1129 \
1130 return res; \
1131 } \
1132 \
1133 static inline unsigned int \
1134 clear_c0_##name(unsigned int clear) \
1135 { \
1136 unsigned int res; \
1137 \
1138 res = read_c0_##name(); \
1139 res &= ~clear; \
1140 write_c0_##name(res); \
1141 \
1142 return res; \
1143 } \
1144 \
1145 static inline unsigned int \
1146 change_c0_##name(unsigned int change, unsigned int new) \
1147 { \
1148 unsigned int res; \
1149 \
1150 res = read_c0_##name(); \
1151 res &= ~change; \
1152 res |= (new & change); \
1153 write_c0_##name(res); \
1154 \
1155 return res; \
1156 }
1157
1158 __BUILD_SET_C0(status,CP0_STATUS)
1159 __BUILD_SET_C0(cause,CP0_CAUSE)
1160 __BUILD_SET_C0(config,CP0_CONFIG)
1161
1162 #define set_cp0_status(x) set_c0_status(x)
1163 #define set_cp0_cause(x) set_c0_cause(x)
1164 #define set_cp0_config(x) set_c0_config(x)
1165
1166 #endif /* !__ASSEMBLY__ */
1167
1168 #endif /* _MIPS_REGS_H_ */
1169