1 /*
2 * File : cpu.c
3 * This file is part of RT-Thread RTOS
4 * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Change Logs:
21 * Date Author Notes
22 * 2016��9��8�� Urey the first version
23 */
24
25
26 #include <rtthread.h>
27 #include <board.h>
28 #include <rthw.h>
29
30 #include "../common/mips.h"
31
32 mips32_core_cfg_t g_mips_core =
33 {
34 .icache_line_size = 32,
35 .icache_size = 16384,
36
37 .dcache_line_size = 32,
38 .dcache_size = 16384,
39
40 .max_tlb_entries = 16, /* max_tlb_entries */
41 };
42
rt_hw_tlb_init(void)43 void rt_hw_tlb_init(void)
44 {
45 //----------------------------------------------------------------------------------
46 //cchappy tlb 0x30000000 to 0xC0000000
47 //----------------------------------------------------------------------------------
48 unsigned int pagemask = 0x007fe000;//0x01ffe000; /* 4MB */
49 /* cached D:allow-W V:valid G */
50 unsigned int entrylo0 = (0x30000000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1;
51 unsigned int entrylo1 = (0x30400000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1;
52 unsigned int entryhi = 0xc0000000; /* kseg2 base */
53 int i;
54 __write_32bit_c0_register($5, 4, 0xa9000000);
55 write_c0_pagemask(pagemask);
56 write_c0_wired(0);
57 /* indexed write 32 tlb entry */
58 for(i = 0; i < 32; i++)
59 {
60 asm (
61 ".macro _ssnop; sll $0, $0, 1; .endm\n\t"
62 ".macro _ehb; sll $0, $0, 3; .endm\n\t"
63 ".macro mtc0_tlbw_hazard; _ssnop; _ssnop; _ehb; .endm\n\t"
64 ".macro tlbw_use_hazard; _ssnop; _ssnop; _ssnop; _ehb; .endm\n\t"
65 "\n\t"
66 "mtc0 %0, $0\n\t" /* write Index */
67 "tlbw_use_hazard\n\t"
68 "mtc0 %1, $5\n\t" /* write PageMask */
69 "mtc0 %2, $10\n\t" /* write EntryHi */
70 "mtc0 %3, $2\n\t" /* write EntryLo0 */
71 "mtc0 %4, $3\n\t" /* write EntryLo1 */
72 "mtc0_tlbw_hazard\n\t"
73 "tlbwi \n\t" /* TLB indexed write */
74 "tlbw_use_hazard\n\t"
75 : : "Jr" (i), "r" (pagemask), "r" (entryhi),
76 "r" (entrylo0), "r" (entrylo1)
77 );
78 entryhi += 0x0800000; /* 32MB */
79 entrylo0 += (0x0800000 >> 6);
80 entrylo1 += (0x0800000 >> 6);
81 }
82 }
83
rt_hw_cache_init(void)84 void rt_hw_cache_init(void)
85 {
86 r4k_cache_flush_all();
87 }
88
89 /**
90 * this function will reset CPU
91 *
92 */
rt_hw_cpu_reset()93 RT_WEAK void rt_hw_cpu_reset()
94 {
95 /* open the watch-dog */
96 REG_WDT_TCSR = WDT_TCSR_EXT_EN;
97 REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024;
98 REG_WDT_TDR = 0x03;
99 REG_WDT_TCNT = 0x00;
100 REG_WDT_TCER |= WDT_TCER_TCEN;
101
102 rt_kprintf("reboot system...\n");
103 rt_hw_interrupt_disable();
104 while (1);
105 }
106
107 /**
108 * this function will shutdown CPU
109 *
110 */
rt_hw_cpu_shutdown()111 RT_WEAK void rt_hw_cpu_shutdown()
112 {
113 rt_kprintf("shutdown...\n");
114 rt_hw_interrupt_disable();
115 while (1);
116 }
117
118 /**
119 * This function finds the first bit set (beginning with the least significant bit)
120 * in value and return the index of that bit.
121 *
122 * Bits are numbered starting at 1 (the least significant bit). A return value of
123 * zero from any of these functions means that the argument was zero.
124 *
125 * @return return the index of the first bit set. If value is 0, then this function
126 * shall return 0.
127 */
__rt_ffs(int value)128 RT_WEAK int __rt_ffs(int value)
129 {
130 return __builtin_ffs(value);
131 }
132