1 /*
2 * File : x1000.h
3 * This file is part of RT-Thread RTOS
4 * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Change Logs:
21 * Date Author Notes
22 * 2015-11-19 Urey the first version
23 */
24
25 #ifndef __X1000_H__
26 #define __X1000_H__
27
28 #include "../common/mips.h"
29
30 #ifndef __ASSEMBLY__
31
32 #define cache_unroll(base,op) \
33 __asm__ __volatile__(" \
34 .set noreorder; \
35 .set mips3; \
36 cache %1, (%0); \
37 .set mips0; \
38 .set reorder" \
39 : \
40 : "r" (base), \
41 "i" (op));
42
43 /* cpu pipeline flush */
jz_sync(void)44 static inline void jz_sync(void)
45 {
46 __asm__ volatile ("sync");
47 }
48
writeb(u8 value,u32 address)49 static inline void writeb(u8 value, u32 address)
50 {
51 *((volatile u8 *) address) = value;
52 }
writew(u16 value,u32 address)53 static inline void writew( u16 value, u32 address)
54 {
55 *((volatile u16 *) address) = value;
56 }
writel(u32 value,u32 address)57 static inline void writel(u32 value, u32 address)
58 {
59 *((volatile u32 *) address) = value;
60 }
61
readb(u32 address)62 static inline u8 readb(u32 address)
63 {
64 return *((volatile u8 *)address);
65 }
66
readw(u32 address)67 static inline u16 readw(u32 address)
68 {
69 return *((volatile u16 *)address);
70 }
71
readl(u32 address)72 static inline u32 readl(u32 address)
73 {
74 return *((volatile u32 *)address);
75 }
76
jz_writeb(u32 address,u8 value)77 static inline void jz_writeb(u32 address, u8 value)
78 {
79 *((volatile u8 *)address) = value;
80 }
81
jz_writew(u32 address,u16 value)82 static inline void jz_writew(u32 address, u16 value)
83 {
84 *((volatile u16 *)address) = value;
85 }
86
jz_writel(u32 address,u32 value)87 static inline void jz_writel(u32 address, u32 value)
88 {
89 *((volatile u32 *)address) = value;
90 }
91
jz_readb(u32 address)92 static inline u8 jz_readb(u32 address)
93 {
94 return *((volatile u8 *)address);
95 }
96
jz_readw(u32 address)97 static inline u16 jz_readw(u32 address)
98 {
99 return *((volatile u16 *)address);
100 }
101
jz_readl(u32 address)102 static inline u32 jz_readl(u32 address)
103 {
104 return *((volatile u32 *)address);
105 }
106
107 #define BIT(n) (0x01u << (n))
108 #define BIT0 (0x01u << 0)
109 #define BIT1 (0x01u << 1)
110 #define BIT2 (0x01u << 2)
111 #define BIT3 (0x01u << 3)
112 #define BIT4 (0x01u << 4)
113 #define BIT5 (0x01u << 5)
114 #define BIT6 (0x01u << 6)
115 #define BIT7 (0x01u << 7)
116 #define BIT8 (0x01u << 8)
117 #define BIT9 (0x01u << 9)
118 #define BIT10 (0x01u << 10)
119 #define BIT11 (0x01u << 11)
120 #define BIT12 (0x01u << 12)
121 #define BIT13 (0x01u << 13)
122 #define BIT14 (0x01u << 14)
123 #define BIT15 (0x01u << 15)
124 #define BIT16 (0x01u << 16)
125 #define BIT17 (0x01u << 17)
126 #define BIT18 (0x01u << 18)
127 #define BIT19 (0x01u << 19)
128 #define BIT20 (0x01u << 20)
129 #define BIT21 (0x01u << 21)
130 #define BIT22 (0x01u << 22)
131 #define BIT23 (0x01u << 23)
132 #define BIT24 (0x01u << 24)
133 #define BIT25 (0x01u << 25)
134 #define BIT26 (0x01u << 26)
135 #define BIT27 (0x01u << 27)
136 #define BIT28 (0x01u << 28)
137 #define BIT29 (0x01u << 29)
138 #define BIT30 (0x01u << 30)
139 #define BIT31 (0x01u << 31)
140
141 /* Generate the bit field mask from msb to lsb */
142 #define BITS_H2L(msb, lsb) ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
143
144
145 /* Get the bit field value from the data which is read from the register */
146 #define get_bf_value(data, lsb, mask) (((data) & (mask)) >> (lsb))
147
148 #endif /* !ASSEMBLY */
149
150
151 //----------------------------------------------------------------------
152 // Register Definitions
153 //
154 /* AHB0 BUS Devices Base */
155 #define HARB0_BASE 0xB3000000
156 #define EMC_BASE 0xB3010000
157 #define DDRC_BASE 0xB3020000
158 #define MDMAC_BASE 0xB3030000
159 #define LCD_BASE 0xB3050000
160 #define TVE_BASE 0xB3050000
161 #define SLCD_BASE 0xB3050000
162 #define CIM_BASE 0xB3060000
163 #define IPU_BASE 0xB3080000
164 /* AHB1 BUS Devices Base */
165 #define HARB1_BASE 0xB3200000
166 #define DMAGP0_BASE 0xB3210000
167 #define DMAGP1_BASE 0xB3220000
168 #define DMAGP2_BASE 0xB3230000
169 #define MC_BASE 0xB3250000
170 #define ME_BASE 0xB3260000
171 #define DEBLK_BASE 0xB3270000
172 #define IDCT_BASE 0xB3280000
173 #define CABAC_BASE 0xB3290000
174 #define TCSM0_BASE 0xB32B0000
175 #define TCSM1_BASE 0xB32C0000
176 #define SRAM_BASE 0xB32D0000
177 /* AHB2 BUS Devices Base */
178 #define HARB2_BASE 0xB3400000
179 #define NEMC_BASE 0xB3410000
180 #define DMAC_BASE 0xB3420000
181 #define UHC_BASE 0xB3430000
182 //#define UDC_BASE 0xB3440000
183 #define SFC_BASE 0xB3440000
184 #define GPS_BASE 0xB3480000
185 #define ETHC_BASE 0xB34B0000
186 #define BCH_BASE 0xB34D0000
187 #define MSC0_BASE 0xB3450000
188 #define MSC1_BASE 0xB3460000
189 #define MSC2_BASE 0xB3470000
190 #define OTG_BASE 0xb3500000
191
192 /* APB BUS Devices Base */
193 #define CPM_BASE 0xB0000000
194 #define INTC_BASE 0xB0001000
195 #define TCU_BASE 0xB0002000
196 #define WDT_BASE 0xB0002000
197 #define OST_BASE 0xB2000000 /* OS Timer */
198 #define RTC_BASE 0xB0003000
199 #define GPIO_BASE 0xB0010000
200 #define AIC_BASE 0xB0020000
201 #define DMIC_BASE 0xB0021000
202 #define ICDC_BASE 0xB0020000
203 #define UART0_BASE 0xB0030000
204 #define UART1_BASE 0xB0031000
205 #define UART2_BASE 0xB0032000
206 #define SCC_BASE 0xB0040000
207 #define SSI0_BASE 0xB0043000
208 #define SSI1_BASE 0xB0044000
209 #define SSI2_BASE 0xB0045000
210 #define I2C0_BASE 0xB0050000
211 #define I2C1_BASE 0xB0051000
212 #define I2C2_BASE 0xB0052000
213 #define PS2_BASE 0xB0060000
214 #define SADC_BASE 0xB0070000
215 #define OWI_BASE 0xB0072000
216 #define TSSI_BASE 0xB0073000
217
218 /* NAND CHIP Base Address*/
219 #define NEMC_CS1_IOBASE 0Xbb000000
220 #define NEMC_CS2_IOBASE 0Xba000000
221 #define NEMC_CS3_IOBASE 0Xb9000000
222 #define NEMC_CS4_IOBASE 0Xb8000000
223 #define NEMC_CS5_IOBASE 0Xb7000000
224 #define NEMC_CS6_IOBASE 0Xb6000000
225
226 /*********************************************************************************************************
227 ** WDT
228 *********************************************************************************************************/
229 #define WDT_TDR (0x00)
230 #define WDT_TCER (0x04)
231 #define WDT_TCNT (0x08)
232 #define WDT_TCSR (0x0C)
233
234 #define REG_WDT_TDR REG16(WDT_BASE + WDT_TDR)
235 #define REG_WDT_TCER REG8(WDT_BASE + WDT_TCER)
236 #define REG_WDT_TCNT REG16(WDT_BASE + WDT_TCNT)
237 #define REG_WDT_TCSR REG16(WDT_BASE + WDT_TCSR)
238
239 #define WDT_TSCR_WDTSC (1 << 16)
240
241 #define WDT_TCSR_PRESCALE_1 (0 << 3)
242 #define WDT_TCSR_PRESCALE_4 (1 << 3)
243 #define WDT_TCSR_PRESCALE_16 (2 << 3)
244 #define WDT_TCSR_PRESCALE_64 (3 << 3)
245 #define WDT_TCSR_PRESCALE_256 (4 << 3)
246 #define WDT_TCSR_PRESCALE_1024 (5 << 3)
247
248 #define WDT_TCSR_EXT_EN (1 << 2)
249 #define WDT_TCSR_RTC_EN (1 << 1)
250 #define WDT_TCSR_PCK_EN (1 << 0)
251
252 #define WDT_TCER_TCEN (1 << 0)
253
254 /* RTC Reg */
255 #define RTC_RTCCR (0x00) /* rw, 32, 0x00000081 */
256 #define RTC_RTCSR (0x04) /* rw, 32, 0x???????? */
257 #define RTC_RTCSAR (0x08) /* rw, 32, 0x???????? */
258 #define RTC_RTCGR (0x0c) /* rw, 32, 0x0??????? */
259 #define RTC_HCR (0x20) /* rw, 32, 0x00000000 */
260 #define RTC_HWFCR (0x24) /* rw, 32, 0x0000???0 */
261 #define RTC_HRCR (0x28) /* rw, 32, 0x00000??0 */
262 #define RTC_HWCR (0x2c) /* rw, 32, 0x00000008 */
263 #define RTC_HWRSR (0x30) /* rw, 32, 0x00000000 */
264 #define RTC_HSPR (0x34) /* rw, 32, 0x???????? */
265 #define RTC_WENR (0x3c) /* rw, 32, 0x00000000 */
266 #define RTC_CKPCR (0x40) /* rw, 32, 0x00000010 */
267 #define RTC_OWIPCR (0x44) /* rw, 32, 0x00000010 */
268 #define RTC_PWRONCR (0x48) /* rw, 32, 0x???????? */
269
270 #define RTCCR_WRDY BIT(7)
271 #define WENR_WEN BIT(31)
272
273 #define RECOVERY_SIGNATURE (0x001a1a)
274 #define REBOOT_SIGNATURE (0x003535)
275 #define UNMSAK_SIGNATURE (0x7c0000)//do not use these bits
276
277
278 #include "x1000_cpm.h"
279 #include "x1000_intc.h"
280 #include "x1000_otg_dwc.h"
281 #include "x1000_aic.h"
282 #include "x1000_slcdc.h"
283
284 #endif /* _JZ_M150_H_ */
285