1*150812a8SEvalZero /* 2*150812a8SEvalZero 3*150812a8SEvalZero Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 4*150812a8SEvalZero 5*150812a8SEvalZero Redistribution and use in source and binary forms, with or without 6*150812a8SEvalZero modification, are permitted provided that the following conditions are met: 7*150812a8SEvalZero 8*150812a8SEvalZero 1. Redistributions of source code must retain the above copyright notice, this 9*150812a8SEvalZero list of conditions and the following disclaimer. 10*150812a8SEvalZero 11*150812a8SEvalZero 2. Redistributions in binary form must reproduce the above copyright 12*150812a8SEvalZero notice, this list of conditions and the following disclaimer in the 13*150812a8SEvalZero documentation and/or other materials provided with the distribution. 14*150812a8SEvalZero 15*150812a8SEvalZero 3. Neither the name of Nordic Semiconductor ASA nor the names of its 16*150812a8SEvalZero contributors may be used to endorse or promote products derived from this 17*150812a8SEvalZero software without specific prior written permission. 18*150812a8SEvalZero 19*150812a8SEvalZero THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20*150812a8SEvalZero AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21*150812a8SEvalZero IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 22*150812a8SEvalZero ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 23*150812a8SEvalZero LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24*150812a8SEvalZero CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25*150812a8SEvalZero SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26*150812a8SEvalZero INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27*150812a8SEvalZero CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28*150812a8SEvalZero ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29*150812a8SEvalZero POSSIBILITY OF SUCH DAMAGE. 30*150812a8SEvalZero 31*150812a8SEvalZero */ 32*150812a8SEvalZero 33*150812a8SEvalZero #ifndef _NRF52832_PERIPHERALS_H 34*150812a8SEvalZero #define _NRF52832_PERIPHERALS_H 35*150812a8SEvalZero 36*150812a8SEvalZero 37*150812a8SEvalZero /* Clock Peripheral */ 38*150812a8SEvalZero #define CLOCK_PRESENT 39*150812a8SEvalZero #define CLOCK_COUNT 1 40*150812a8SEvalZero 41*150812a8SEvalZero /* Power Peripheral */ 42*150812a8SEvalZero #define POWER_PRESENT 43*150812a8SEvalZero #define POWER_COUNT 1 44*150812a8SEvalZero 45*150812a8SEvalZero #define POWER_FEATURE_RAM_REGISTERS_PRESENT 46*150812a8SEvalZero #define POWER_FEATURE_RAM_REGISTERS_COUNT 8 47*150812a8SEvalZero 48*150812a8SEvalZero /* Floating Point Unit */ 49*150812a8SEvalZero #define FPU_PRESENT 50*150812a8SEvalZero #define FPU_COUNT 1 51*150812a8SEvalZero 52*150812a8SEvalZero /* Systick timer */ 53*150812a8SEvalZero #define SYSTICK_PRESENT 54*150812a8SEvalZero #define SYSTICK_COUNT 1 55*150812a8SEvalZero 56*150812a8SEvalZero /* Software Interrupts */ 57*150812a8SEvalZero #define SWI_PRESENT 58*150812a8SEvalZero #define SWI_COUNT 6 59*150812a8SEvalZero 60*150812a8SEvalZero /* Memory Watch Unit */ 61*150812a8SEvalZero #define MWU_PRESENT 62*150812a8SEvalZero #define MWU_COUNT 1 63*150812a8SEvalZero 64*150812a8SEvalZero /* GPIO */ 65*150812a8SEvalZero #define GPIO_PRESENT 66*150812a8SEvalZero #define GPIO_COUNT 1 67*150812a8SEvalZero 68*150812a8SEvalZero #define P0_PIN_NUM 32 69*150812a8SEvalZero 70*150812a8SEvalZero /* MPU and BPROT */ 71*150812a8SEvalZero #define BPROT_PRESENT 72*150812a8SEvalZero 73*150812a8SEvalZero #define BPROT_REGIONS_SIZE 4096 74*150812a8SEvalZero #define BPROT_REGIONS_NUM 128 75*150812a8SEvalZero 76*150812a8SEvalZero /* Radio */ 77*150812a8SEvalZero #define RADIO_PRESENT 78*150812a8SEvalZero #define RADIO_COUNT 1 79*150812a8SEvalZero 80*150812a8SEvalZero #define RADIO_EASYDMA_MAXCNT_SIZE 8 81*150812a8SEvalZero 82*150812a8SEvalZero /* Accelerated Address Resolver */ 83*150812a8SEvalZero #define AAR_PRESENT 84*150812a8SEvalZero #define AAR_COUNT 1 85*150812a8SEvalZero 86*150812a8SEvalZero #define AAR_MAX_IRK_NUM 16 87*150812a8SEvalZero 88*150812a8SEvalZero /* AES Electronic CodeBook mode encryption */ 89*150812a8SEvalZero #define ECB_PRESENT 90*150812a8SEvalZero #define ECB_COUNT 1 91*150812a8SEvalZero 92*150812a8SEvalZero /* AES CCM mode encryption */ 93*150812a8SEvalZero #define CCM_PRESENT 94*150812a8SEvalZero #define CCM_COUNT 1 95*150812a8SEvalZero 96*150812a8SEvalZero /* NFC Tag */ 97*150812a8SEvalZero #define NFCT_PRESENT 98*150812a8SEvalZero #define NFCT_COUNT 1 99*150812a8SEvalZero 100*150812a8SEvalZero #define NFCT_EASYDMA_MAXCNT_SIZE 9 101*150812a8SEvalZero 102*150812a8SEvalZero /* Peripheral to Peripheral Interconnect */ 103*150812a8SEvalZero #define PPI_PRESENT 104*150812a8SEvalZero #define PPI_COUNT 1 105*150812a8SEvalZero 106*150812a8SEvalZero #define PPI_CH_NUM 20 107*150812a8SEvalZero #define PPI_FIXED_CH_NUM 12 108*150812a8SEvalZero #define PPI_GROUP_NUM 6 109*150812a8SEvalZero #define PPI_FEATURE_FORKS_PRESENT 110*150812a8SEvalZero 111*150812a8SEvalZero /* Event Generator Unit */ 112*150812a8SEvalZero #define EGU_PRESENT 113*150812a8SEvalZero #define EGU_COUNT 6 114*150812a8SEvalZero 115*150812a8SEvalZero #define EGU0_CH_NUM 16 116*150812a8SEvalZero #define EGU1_CH_NUM 16 117*150812a8SEvalZero #define EGU2_CH_NUM 16 118*150812a8SEvalZero #define EGU3_CH_NUM 16 119*150812a8SEvalZero #define EGU4_CH_NUM 16 120*150812a8SEvalZero #define EGU5_CH_NUM 16 121*150812a8SEvalZero 122*150812a8SEvalZero /* Timer/Counter */ 123*150812a8SEvalZero #define TIMER_PRESENT 124*150812a8SEvalZero #define TIMER_COUNT 5 125*150812a8SEvalZero 126*150812a8SEvalZero #define TIMER0_MAX_SIZE 32 127*150812a8SEvalZero #define TIMER1_MAX_SIZE 32 128*150812a8SEvalZero #define TIMER2_MAX_SIZE 32 129*150812a8SEvalZero #define TIMER3_MAX_SIZE 32 130*150812a8SEvalZero #define TIMER4_MAX_SIZE 32 131*150812a8SEvalZero 132*150812a8SEvalZero #define TIMER0_CC_NUM 4 133*150812a8SEvalZero #define TIMER1_CC_NUM 4 134*150812a8SEvalZero #define TIMER2_CC_NUM 4 135*150812a8SEvalZero #define TIMER3_CC_NUM 6 136*150812a8SEvalZero #define TIMER4_CC_NUM 6 137*150812a8SEvalZero 138*150812a8SEvalZero /* Real Time Counter */ 139*150812a8SEvalZero #define RTC_PRESENT 140*150812a8SEvalZero #define RTC_COUNT 3 141*150812a8SEvalZero 142*150812a8SEvalZero #define RTC0_CC_NUM 3 143*150812a8SEvalZero #define RTC1_CC_NUM 4 144*150812a8SEvalZero #define RTC2_CC_NUM 4 145*150812a8SEvalZero 146*150812a8SEvalZero /* RNG */ 147*150812a8SEvalZero #define RNG_PRESENT 148*150812a8SEvalZero #define RNG_COUNT 1 149*150812a8SEvalZero 150*150812a8SEvalZero /* Watchdog Timer */ 151*150812a8SEvalZero #define WDT_PRESENT 152*150812a8SEvalZero #define WDT_COUNT 1 153*150812a8SEvalZero 154*150812a8SEvalZero /* Temperature Sensor */ 155*150812a8SEvalZero #define TEMP_PRESENT 156*150812a8SEvalZero #define TEMP_COUNT 1 157*150812a8SEvalZero 158*150812a8SEvalZero /* Serial Peripheral Interface Master */ 159*150812a8SEvalZero #define SPI_PRESENT 160*150812a8SEvalZero #define SPI_COUNT 3 161*150812a8SEvalZero 162*150812a8SEvalZero /* Serial Peripheral Interface Master with DMA */ 163*150812a8SEvalZero #define SPIM_PRESENT 164*150812a8SEvalZero #define SPIM_COUNT 3 165*150812a8SEvalZero 166*150812a8SEvalZero #define SPIM0_MAX_DATARATE 8 167*150812a8SEvalZero #define SPIM1_MAX_DATARATE 8 168*150812a8SEvalZero #define SPIM2_MAX_DATARATE 8 169*150812a8SEvalZero 170*150812a8SEvalZero #define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0 171*150812a8SEvalZero #define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0 172*150812a8SEvalZero #define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0 173*150812a8SEvalZero 174*150812a8SEvalZero #define SPIM0_FEATURE_DCX_PRESENT 0 175*150812a8SEvalZero #define SPIM1_FEATURE_DCX_PRESENT 0 176*150812a8SEvalZero #define SPIM2_FEATURE_DCX_PRESENT 0 177*150812a8SEvalZero 178*150812a8SEvalZero #define SPIM0_FEATURE_RXDELAY_PRESENT 0 179*150812a8SEvalZero #define SPIM1_FEATURE_RXDELAY_PRESENT 0 180*150812a8SEvalZero #define SPIM2_FEATURE_RXDELAY_PRESENT 0 181*150812a8SEvalZero 182*150812a8SEvalZero #define SPIM0_EASYDMA_MAXCNT_SIZE 8 183*150812a8SEvalZero #define SPIM1_EASYDMA_MAXCNT_SIZE 8 184*150812a8SEvalZero #define SPIM2_EASYDMA_MAXCNT_SIZE 8 185*150812a8SEvalZero 186*150812a8SEvalZero /* Serial Peripheral Interface Slave with DMA*/ 187*150812a8SEvalZero #define SPIS_PRESENT 188*150812a8SEvalZero #define SPIS_COUNT 3 189*150812a8SEvalZero 190*150812a8SEvalZero #define SPIS0_EASYDMA_MAXCNT_SIZE 8 191*150812a8SEvalZero #define SPIS1_EASYDMA_MAXCNT_SIZE 8 192*150812a8SEvalZero #define SPIS2_EASYDMA_MAXCNT_SIZE 8 193*150812a8SEvalZero 194*150812a8SEvalZero /* Two Wire Interface Master */ 195*150812a8SEvalZero #define TWI_PRESENT 196*150812a8SEvalZero #define TWI_COUNT 2 197*150812a8SEvalZero 198*150812a8SEvalZero /* Two Wire Interface Master with DMA */ 199*150812a8SEvalZero #define TWIM_PRESENT 200*150812a8SEvalZero #define TWIM_COUNT 2 201*150812a8SEvalZero 202*150812a8SEvalZero #define TWIM0_EASYDMA_MAXCNT_SIZE 8 203*150812a8SEvalZero #define TWIM1_EASYDMA_MAXCNT_SIZE 8 204*150812a8SEvalZero 205*150812a8SEvalZero /* Two Wire Interface Slave with DMA */ 206*150812a8SEvalZero #define TWIS_PRESENT 207*150812a8SEvalZero #define TWIS_COUNT 2 208*150812a8SEvalZero 209*150812a8SEvalZero #define TWIS0_EASYDMA_MAXCNT_SIZE 8 210*150812a8SEvalZero #define TWIS1_EASYDMA_MAXCNT_SIZE 8 211*150812a8SEvalZero 212*150812a8SEvalZero /* Universal Asynchronous Receiver-Transmitter */ 213*150812a8SEvalZero #define UART_PRESENT 214*150812a8SEvalZero #define UART_COUNT 1 215*150812a8SEvalZero 216*150812a8SEvalZero /* Universal Asynchronous Receiver-Transmitter with DMA */ 217*150812a8SEvalZero #define UARTE_PRESENT 218*150812a8SEvalZero #define UARTE_COUNT 1 219*150812a8SEvalZero 220*150812a8SEvalZero #define UARTE0_EASYDMA_MAXCNT_SIZE 8 221*150812a8SEvalZero 222*150812a8SEvalZero /* Quadrature Decoder */ 223*150812a8SEvalZero #define QDEC_PRESENT 224*150812a8SEvalZero #define QDEC_COUNT 1 225*150812a8SEvalZero 226*150812a8SEvalZero /* Successive Approximation Analog to Digital Converter */ 227*150812a8SEvalZero #define SAADC_PRESENT 228*150812a8SEvalZero #define SAADC_COUNT 1 229*150812a8SEvalZero 230*150812a8SEvalZero #define SAADC_EASYDMA_MAXCNT_SIZE 15 231*150812a8SEvalZero 232*150812a8SEvalZero #define SAADC_CH_NUM 8 233*150812a8SEvalZero 234*150812a8SEvalZero /* GPIO Tasks and Events */ 235*150812a8SEvalZero #define GPIOTE_PRESENT 236*150812a8SEvalZero #define GPIOTE_COUNT 1 237*150812a8SEvalZero 238*150812a8SEvalZero #define GPIOTE_CH_NUM 8 239*150812a8SEvalZero 240*150812a8SEvalZero #define GPIOTE_FEATURE_SET_PRESENT 241*150812a8SEvalZero #define GPIOTE_FEATURE_CLR_PRESENT 242*150812a8SEvalZero 243*150812a8SEvalZero /* Low Power Comparator */ 244*150812a8SEvalZero #define LPCOMP_PRESENT 245*150812a8SEvalZero #define LPCOMP_COUNT 1 246*150812a8SEvalZero 247*150812a8SEvalZero #define LPCOMP_REFSEL_RESOLUTION 16 248*150812a8SEvalZero 249*150812a8SEvalZero #define LPCOMP_FEATURE_HYST_PRESENT 250*150812a8SEvalZero 251*150812a8SEvalZero /* Comparator */ 252*150812a8SEvalZero #define COMP_PRESENT 253*150812a8SEvalZero #define COMP_COUNT 1 254*150812a8SEvalZero 255*150812a8SEvalZero /* Pulse Width Modulator */ 256*150812a8SEvalZero #define PWM_PRESENT 257*150812a8SEvalZero #define PWM_COUNT 3 258*150812a8SEvalZero 259*150812a8SEvalZero #define PWM0_CH_NUM 4 260*150812a8SEvalZero #define PWM1_CH_NUM 4 261*150812a8SEvalZero #define PWM2_CH_NUM 4 262*150812a8SEvalZero 263*150812a8SEvalZero #define PWM0_EASYDMA_MAXCNT_SIZE 15 264*150812a8SEvalZero #define PWM1_EASYDMA_MAXCNT_SIZE 15 265*150812a8SEvalZero #define PWM2_EASYDMA_MAXCNT_SIZE 15 266*150812a8SEvalZero 267*150812a8SEvalZero /* Pulse Density Modulator */ 268*150812a8SEvalZero #define PDM_PRESENT 269*150812a8SEvalZero #define PDM_COUNT 1 270*150812a8SEvalZero 271*150812a8SEvalZero #define PDM_EASYDMA_MAXCNT_SIZE 15 272*150812a8SEvalZero 273*150812a8SEvalZero /* Inter-IC Sound Interface */ 274*150812a8SEvalZero #define I2S_PRESENT 275*150812a8SEvalZero #define I2S_COUNT 1 276*150812a8SEvalZero 277*150812a8SEvalZero #define I2S_EASYDMA_MAXCNT_SIZE 14 278*150812a8SEvalZero 279*150812a8SEvalZero 280*150812a8SEvalZero #endif // _NRF52832_PERIPHERALS_H 281