decode - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/decode

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
c59c31ca	03-Sep-2020	ZhangZifei <[email protected]>	Merge branch 'connect_atomics' into dev-fence /XiangShan/src/main/scala/xiangshan/XSCore.scala DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala
b8f08ca0	03-Sep-2020	ZhangZifei <[email protected]>	Fence: add fence decode and rewrite some fence logic. need roq redirect /XiangShan/.github/workflows/emu.yml /XiangShan/debug/Makefile /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala DecodeHelper.scala Decoder.scala isa/Privileged.scala isa/RVZifencei.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala
fa084740	02-Sep-2020	Allen <[email protected]>	Atomics: enable A instr in decode table and connects atomcs unit in memend. /XiangShan/.github/workflows/emu.yml /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/scala/top/XSSim.scala
37ee565a	24-Aug-2020	ZhangZifei <[email protected]>	TLB: add assert to avoid other alu(1/2/3) exec sfence/fence.i /XiangShan/src/main/scala/xiangshan/backend/Backend.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala
32ccb061	23-Aug-2020	ZhangZifei <[email protected]>	TLB: add sfence.vma decode( to ALU, NoSpecExec, not isBlocked now) /XiangShan/.gitmodules /XiangShan/.mill-jvm-opts /XiangShan/.mill-version /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sc /XiangShan/rocket-chip /XiangShan/run /XiangShan/src/main/scala/bus/axi4/AXI4.scala /XiangShan/src/main/scala/bus/tilelink/MMIOTLToAXI4.scala /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala Decoder.scala isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/misc.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/MiscUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/StoreUnit.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/scala/device/AXI4BurstMaster.scala /XiangShan/src/test/scala/device/AXI4RamTest.scala /XiangShan/src/test/scala/device/AXI4TimerTest.scala /XiangShan/src/test/scala/device/SimMMIOTest.scala /XiangShan/src/test/scala/device/TLBurstMaster.scala /XiangShan/src/test/scala/device/TLTimerTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/exu/DCacheTest.scala
1872d735	18-Aug-2020	ZhangZifei <[email protected]>	Merge branch 'dev-soc' into dev-soc-tlb still syntax bug but not fixed /XiangShan/Makefile /XiangShan/debug/Makefile /XiangShan/debug/cputest.sh /XiangShan/src/main/scala/bus/axi4/AXI4.scala /XiangShan/src/main/scala/bus/axi4/AXI4ToAXI4Lite.scala /XiangShan/src/main/scala/bus/tilelink/Arbiter.scala /XiangShan/src/main/scala/bus/tilelink/FakeTLCache.scala /XiangShan/src/main/scala/bus/tilelink/MMIOTLToAXI4.scala /XiangShan/src/main/scala/bus/tilelink/Metadata.scala /XiangShan/src/main/scala/bus/tilelink/NaiveTL1toN.scala /XiangShan/src/main/scala/bus/tilelink/TLUtilities.scala /XiangShan/src/main/scala/bus/tilelink/TileLink.scala /XiangShan/src/main/scala/noop/Cache.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/ECC.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/Misc.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeHelper.scala Decoder.scala isa/RVA.scala isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/Mem.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/misc.scala /XiangShan/src/main/scala/xiangshan/cache/miscMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/MiscUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/exu/DCacheTest.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala
6f6f796b	14-Aug-2020	LinJiawei <[email protected]>	Merge master /XiangShan/Makefile /XiangShan/debug/cputest.sh /XiangShan/src/main/scala/bus/tilelink/FakeTLCache.scala /XiangShan/src/main/scala/bus/tilelink/MMIOTLToAXI4.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala DecodeHelper.scala Decoder.scala isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/MiscUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/exu/DCacheTest.scala
3366070d	12-Aug-2020	William Wang <[email protected]>	RVA: add RVA decode /XiangShan/debug/cputest.sh /XiangShan/src/main/scala/bus/axi4/AXI4.scala /XiangShan/src/main/scala/bus/axi4/AXI4ToAXI4Lite.scala /XiangShan/src/main/scala/bus/tilelink/Arbiter.scala /XiangShan/src/main/scala/bus/tilelink/FakeTLCache.scala /XiangShan/src/main/scala/bus/tilelink/Metadata.scala /XiangShan/src/main/scala/bus/tilelink/NaiveTL1toN.scala /XiangShan/src/main/scala/bus/tilelink/NaiveTLToAXI4.scala /XiangShan/src/main/scala/bus/tilelink/TLUtilities.scala /XiangShan/src/main/scala/bus/tilelink/TileLink.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/ECC.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/Misc.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Decoder.scala isa/RVA.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/Mem.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/MiscUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/exu/DCacheTest.scala
e9199ec7	06-Aug-2020	zhanglinjuan <[email protected]>	ifu/bpu: fix bug in saveHalfRVI /XiangShan/src/main/scala/xiangshan/Bundle.scala isa/RVC.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
c9c84175	06-Aug-2020	zhanglinjuan <[email protected]>	decoder: fix bug in src1Type for C_LUI predecode: fix bugs in mask output Decoder.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
4ed69b39	06-Aug-2020	zhanglinjuan <[email protected]>	fakeICache: fetch instructions 2-bytes aligned decoder: fix bug in immrvc dummy passes! Decoder.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala
06138c3d	06-Aug-2020	ZhangZifei <[email protected]>	Merge branch 'temp-lsu-test' into temp-lsu-test-tlb /XiangShan/src/main/scala/xiangshan/XSCore.scala DecodeBuffer.scala Decoder.scala isa/RVC.scala isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/mem/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
c38306bf	06-Aug-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/master' into temp-lsu-test Decoder.scala isa/RVC.scala isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
6d5636a4	05-Aug-2020	linjiawei <[email protected]>	Merge remote-tracking branch 'origin/master' into temp-lsu-test Decoder.scala isa/RVC.scala isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
e87da745	05-Aug-2020	zhanglinjuan <[email protected]>	decoder: add rvc call/ret bpu: fix lastHit in stage3 DecodeHelper.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
e928f13c	05-Aug-2020	LinJiawei <[email protected]>	DecodeBuf: fix redirect bug /XiangShan/.gitignore /XiangShan/debug/Makefile /XiangShan/src/main/scala/noop/TLB.scala /XiangShan/src/main/scala/utils/Pipeline.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/ReservationStationTest.scala
bf393c2b	05-Aug-2020	ZhangZifei <[email protected]>	Merge branch 'temp-lsu-test' into temp-lsu-test-tlb /XiangShan/Makefile /XiangShan/build.sc /XiangShan/debug/Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/noop/EXU.scala /XiangShan/src/main/scala/noop/NOOPTrap.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeBuffer.scala DecodeStage.scala Decoder.scala isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/mem/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Sbuffer.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/device.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/ReservationStationTest.scala /XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
d077b118	05-Aug-2020	zhanglinjuan <[email protected]>	decoder/rvc: add rvc instructions Decoder.scala isa/RVC.scala isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
a428082b	04-Aug-2020	LinJiawei <[email protected]>	Merge master into dev-fronend /XiangShan/Makefile /XiangShan/build.sc /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/noop/EXU.scala /XiangShan/src/main/scala/noop/NOOPTrap.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/device.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
769b146d	02-Aug-2020	Lingrui98 <[email protected]>	Decode: isBr ->!notCFI /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/test/scala/IFUtest/PDtest.scala /XiangShan/src/test/scala/IFUtest/uBTBTest.scala /XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala
31402152	02-Aug-2020	ZhangZifei <[email protected]>	Merge branch 'temp-lsu-test' into temp-lsu-test-tlb /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeStage.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/ReservationStationTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala
608ba82c	31-Jul-2020	zhanglinjuan <[email protected]>	backend: adaptive backend interface with frontend /XiangShan/debug/Makefile /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeStage.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala
68eeafa8	31-Jul-2020	zhangfw <[email protected]>	Predecode: replace old PDecode /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala
f226232f	29-Jul-2020	zhanglinjuan <[email protected]>	Merge branch 'refactor-redirect' into dev-frontend /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/debug/Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeStage.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala
b2e6921e	28-Jul-2020	LinJiawei <[email protected]>	Refactor redirect, cputest pass, microbench fail /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/debug/Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/bus/simplebus/Crossbar.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeStage.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/vga.cpp /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/testcase/Makefile /XiangShan/src/test/testcase/tests/double-loop.c /XiangShan/src/test/testcase/tests/nested-loop.c
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