1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import utils._ 8 9trait HasIFUConst { this: XSModule => 10 val resetVector = 0x80000000L//TODO: set reset vec 11 val groupAlign = log2Up(FetchWidth * 4 * 2) 12 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 13 // each 1 bit in mask stands for 2 Bytes 14 def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0) 15 def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1) 16} 17 18class IFUIO extends XSBundle 19{ 20 val fetchPacket = DecoupledIO(new FetchPacket) 21 val redirect = Flipped(ValidIO(new Redirect)) 22 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 23 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 24 val icacheReq = DecoupledIO(new FakeIcacheReq) 25 val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp)) 26 val icacheFlush = Output(UInt(2.W)) 27} 28 29 30class IFU extends XSModule with HasIFUConst 31{ 32 val io = IO(new IFUIO) 33 val bpu = if (EnableBPU) Module(new BPU) else Module(new FakeBPU) 34 val pd = Module(new PreDecode) 35 36 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 37 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 38 39 if4_flush := io.redirect.valid 40 if3_flush := if4_flush || if4_redirect 41 if2_flush := if3_flush || if3_redirect 42 if1_flush := if2_flush || if2_redirect 43 44 //********************** IF1 ****************************// 45 val if1_valid = !reset.asBool 46 val if1_npc = WireInit(0.U(VAddrBits.W)) 47 val if2_ready = WireInit(false.B) 48 val if1_fire = if1_valid && (if2_ready || if1_flush) && io.icacheReq.ready 49 50 // val extHist = VecInit(Fill(ExtHistoryLength, RegInit(0.U(1.W)))) 51 val extHist = RegInit(VecInit(Seq.fill(ExtHistoryLength)(0.U(1.W)))) 52 val headPtr = RegInit(0.U(log2Up(ExtHistoryLength).W)) 53 val shiftPtr = WireInit(false.B) 54 val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 55 val ptr = Mux(shiftPtr, newPtr, headPtr) 56 when (shiftPtr) { headPtr := newPtr } 57 val hist = Wire(Vec(HistoryLength, UInt(1.W))) 58 for (i <- 0 until HistoryLength) { 59 hist(i) := extHist(ptr + i.U) 60 } 61 62 newPtr := headPtr 63 shiftPtr := false.B 64 65 //********************** IF2 ****************************// 66 val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire) 67 val if3_ready = WireInit(false.B) 68 val if2_fire = if2_valid && if3_ready && !if2_flush 69 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 70 val if2_snpc = snpc(if2_pc) 71 val if2_histPtr = RegEnable(ptr, if1_fire) 72 if2_ready := if2_fire || !if2_valid || if2_flush 73 when (if2_flush) { if2_valid := if1_fire } 74 .elsewhen (if1_fire) { if2_valid := if1_valid } 75 .elsewhen (if2_fire) { if2_valid := false.B } 76 77 when (RegNext(reset.asBool) && !reset.asBool) { 78 if1_npc := resetVector.U(VAddrBits.W) 79 }.elsewhen (if2_fire) { 80 if1_npc := if2_snpc 81 }.otherwise { 82 if1_npc := RegNext(if1_npc) 83 } 84 85 val if2_bp = bpu.io.out(0).bits 86 if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect && !if2_bp.saveHalfRVI 87 when (if2_redirect) { 88 if1_npc := if2_bp.target 89 } 90 91 when (if2_fire && (if2_bp.taken || if2_bp.hasNotTakenBrs)) { 92 shiftPtr := true.B 93 newPtr := headPtr - 1.U 94 hist(0) := if2_bp.taken.asUInt 95 extHist(newPtr) := if2_bp.taken.asUInt 96 } 97 98 //********************** IF3 ****************************// 99 val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire) 100 val if4_ready = WireInit(false.B) 101 val if3_fire = if3_valid && if4_ready && io.icacheResp.valid && !if3_flush 102 val if3_pc = RegEnable(if2_pc, if2_fire) 103 val if3_histPtr = RegEnable(if2_histPtr, if2_fire) 104 if3_ready := if3_fire || !if3_valid || if3_flush 105 when (if3_flush) { if3_valid := false.B } 106 .elsewhen (if2_fire) { if3_valid := if2_valid } 107 .elsewhen (if3_fire) { if3_valid := false.B } 108 109 val if3_bp = bpu.io.out(1).bits 110 val prev_half_valid = RegInit(false.B) 111 val prev_half_redirect = RegInit(false.B) 112 val prev_half_fetchpc = Reg(UInt(VAddrBits.W)) 113 val prev_half_idx = Reg(UInt(log2Up(PredictWidth).W)) 114 val prev_half_tgt = Reg(UInt(VAddrBits.W)) 115 val prev_half_taken = RegInit(false.B) 116 val prev_half_instr = Reg(UInt(16.W)) 117 when (if3_flush) { 118 prev_half_valid := false.B 119 prev_half_redirect := false.B 120 }.elsewhen (if3_fire && if3_bp.saveHalfRVI) { 121 prev_half_valid := true.B 122 prev_half_redirect := if3_bp.redirect && bpu.io.out(1).valid 123 prev_half_fetchpc := if3_pc 124 val idx = Mux(if3_bp.redirect && bpu.io.out(1).valid, if3_bp.jmpIdx, PopCount(mask(if3_pc)) - 1.U) 125 prev_half_idx := idx 126 prev_half_tgt := if3_bp.target 127 prev_half_taken := if3_bp.taken 128 prev_half_instr := pd.io.out.instrs(idx)(15, 0) 129 }.elsewhen (if3_fire) { 130 prev_half_valid := false.B 131 prev_half_redirect := false.B 132 } 133 134 // if3_redirect := if3_fire && (prev_half_valid && prev_half_taken || bpu.io.out(1).valid && if3_bp.redirect && !if3_bp.saveHalfRVI) 135 // when (if3_redirect) { 136 // if1_npc := Mux(prev_half_valid && prev_half_redirect, prev_half_tgt, if3_bp.target) 137 // } 138 139 when (bpu.io.out(1).valid && if3_fire) { 140 when (prev_half_valid && prev_half_taken) { 141 if3_redirect := true.B 142 if1_npc := prev_half_tgt 143 shiftPtr := true.B 144 newPtr := if3_histPtr - 1.U 145 hist(0) := 1.U 146 extHist(newPtr) := 1.U 147 }.elsewhen (if3_bp.redirect && !if3_bp.saveHalfRVI) { 148 if3_redirect := true.B 149 if1_npc := if3_bp.target 150 shiftPtr := true.B 151 newPtr := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 152 hist(0) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr)) 153 extHist(newPtr) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr)) 154 }.elsewhen (if3_bp.saveHalfRVI) { 155 if3_redirect := true.B 156 if1_npc := snpc(if3_pc) 157 shiftPtr := true.B 158 newPtr := Mux(if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 159 hist(0) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr)) 160 extHist(newPtr) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr)) 161 }.otherwise { 162 if3_redirect := false.B 163 } 164 }.otherwise { 165 if3_redirect := false.B 166 } 167 168 169 //********************** IF4 ****************************// 170 val if4_pd = RegEnable(pd.io.out, if3_fire) 171 // val if4_icacheResp = RegEnable(io.icacheResp.bits, if3_fire) 172 val if4_valid = RegInit(false.B) 173 // val if4_valid = RegEnable(next = if3_valid, init = false.B, enable = if3_fire) 174 val if4_fire = if4_valid && io.fetchPacket.ready 175 val if4_pc = RegEnable(if3_pc, if3_fire) 176 val if4_histPtr = RegEnable(if3_histPtr, if3_fire) 177 if4_ready := (if4_fire || !if4_valid || if4_flush) && GTimer() > 500.U 178 when (if4_flush) { if4_valid := false.B } 179 .elsewhen (if3_fire) { if4_valid := if3_valid } 180 .elsewhen(if4_fire) { if4_valid := false.B } 181 182 val if4_bp = Wire(new BranchPrediction) 183 if4_bp := bpu.io.out(2).bits 184 // TODO: c_jal 185 val if4_cfi_jal = if4_pd.instrs(if4_bp.jmpIdx) 186 val if4_cfi_jal_tgt = if4_pd.pc(if4_bp.jmpIdx) + SignExt(Cat(if4_cfi_jal(31), if4_cfi_jal(19, 12), if4_cfi_jal(20), if4_cfi_jal(30, 21), 0.U(1.W)), XLEN) 187 if4_bp.target := Mux(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, if4_cfi_jal_tgt, bpu.io.out(2).bits.target) 188 if4_bp.redirect := bpu.io.out(2).bits.redirect || if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken && if4_cfi_jal_tgt =/= bpu.io.out(2).bits.target 189 190 when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 191 when (!if4_bp.saveHalfRVI) { 192 if4_redirect := true.B 193 // if1_npc := if4_bp.target 194 if1_npc := Mux(if4_bp.taken, if4_bp.target, snpc(if4_pc)) 195 196 shiftPtr := true.B 197 newPtr := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 198 hist(0) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 199 extHist(newPtr) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 200 201 }.otherwise { 202 if4_redirect := true.B 203 if1_npc := snpc(if4_pc) 204 205 prev_half_valid := true.B 206 prev_half_redirect := true.B 207 prev_half_fetchpc := if4_pc 208 val idx = PopCount(mask(if4_pc)) - 1.U 209 prev_half_idx := idx 210 prev_half_tgt := if4_bp.target 211 prev_half_taken := if4_bp.taken 212 prev_half_instr := if4_pd.instrs(idx)(15, 0) 213 214 shiftPtr := true.B 215 newPtr := Mux(if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 216 hist(0) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr)) 217 extHist(newPtr) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr)) 218 } 219 }.otherwise { 220 if4_redirect := false.B 221 } 222 223 when (io.outOfOrderBrInfo.valid) { 224 shiftPtr := true.B 225 newPtr := io.outOfOrderBrInfo.bits.brInfo.histPtr - 1.U 226 hist(0) := io.outOfOrderBrInfo.bits.taken 227 extHist(newPtr) := io.outOfOrderBrInfo.bits.taken 228 } 229 230 when (io.redirect.valid) { 231 if1_npc := io.redirect.bits.target 232 } 233 234 io.icacheReq.valid := if1_valid && if2_ready 235 io.icacheReq.bits.addr := if1_npc 236 io.icacheResp.ready := if3_ready 237 io.icacheFlush := Cat(if3_flush, if2_flush) 238 239 val inOrderBrHist = Wire(Vec(HistoryLength, UInt(1.W))) 240 (0 until HistoryLength).foreach(i => inOrderBrHist(i) := extHist(i.U + io.inOrderBrInfo.bits.brInfo.histPtr)) 241 bpu.io.inOrderBrInfo.valid := io.inOrderBrInfo.valid 242 bpu.io.inOrderBrInfo.bits := BranchUpdateInfoWithHist(io.inOrderBrInfo.bits, inOrderBrHist.asUInt) 243 // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 244 bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush) 245 bpu.io.in.valid := if1_fire 246 bpu.io.in.bits.pc := if1_npc 247 bpu.io.in.bits.hist := hist.asUInt 248 bpu.io.in.bits.inMask := mask(if1_npc) 249 bpu.io.out(0).ready := if2_fire 250 bpu.io.out(1).ready := if3_fire 251 bpu.io.out(2).ready := if4_fire 252 bpu.io.predecode.valid := if4_valid 253 bpu.io.predecode.bits.mask := if4_pd.mask 254 bpu.io.predecode.bits.pd := if4_pd.pd 255 bpu.io.branchInfo.ready := if4_fire 256 257 pd.io.in := io.icacheResp.bits 258 pd.io.prev.valid := prev_half_valid 259 pd.io.prev.bits := prev_half_instr 260 261 io.fetchPacket.valid := if4_valid && !io.redirect.valid 262 io.fetchPacket.bits.instrs := if4_pd.instrs 263 io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 264 io.fetchPacket.bits.pc := if4_pd.pc 265 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 266 when (if4_bp.taken) { 267 io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target 268 } 269 io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits 270 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := if4_histPtr) 271 io.fetchPacket.bits.pd := if4_pd.pd 272 273 // debug info 274 XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 275 XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n") 276 XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n") 277 XSDebug(io.redirect.valid, "Redirect from backend! isExcp=%d isMisPred=%d isReplay=%d pc=%x\n", 278 io.redirect.bits.isException, io.redirect.bits.isMisPred, io.redirect.bits.isReplay, io.redirect.bits.pc) 279 XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits.target)} brTag=${io.redirect.bits.brTag}\n") 280 281 XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x ptr=%d mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, ptr, mask(if1_npc)) 282 XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_histPtr, if2_snpc) 283 XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr) 284 XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr) 285 286 XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr) 287 XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", headPtr, shiftPtr, newPtr, ptr) 288 XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt) 289 XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt) 290 291 XSDebug("[IF2][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.redirect, if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 292 293 XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask) 294 XSDebug("[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.redirect, if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 295 XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 296 prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 297 298 XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 299 XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 300 XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_cfi_jal, if4_cfi_jal_tgt) 301 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b\n", io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask) 302 for (i <- 0 until PredictWidth) { 303 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 304 io.fetchPacket.bits.mask(i), 305 io.fetchPacket.bits.instrs(i), 306 io.fetchPacket.bits.pc(i), 307 io.fetchPacket.bits.pnpc(i), 308 io.fetchPacket.bits.pd(i).isRVC, 309 io.fetchPacket.bits.pd(i).brType, 310 io.fetchPacket.bits.pd(i).isCall, 311 io.fetchPacket.bits.pd(i).isRet 312 ) 313 } 314}