xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision 314021526d2b85c4ff156bd66c805782837006e8) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig}
7import xiangshan.backend._
8import xiangshan.backend.dispatch.DispatchParameters
9import xiangshan.backend.exu.ExuParameters
10import xiangshan.frontend._
11import xiangshan.mem._
12import utils._
13
14trait HasXSParameter {
15  val XLEN = 64
16  val HasMExtension = true
17  val HasCExtension = true
18  val HasDiv = true
19  val HasIcache = true
20  val HasDcache = true
21  val EnableStoreQueue = false
22  val AddrBits = 64 // AddrBits is used in some cases
23  val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits
24  val PAddrBits = 40 // PAddrBits is Phyical Memory addr bits
25  val AddrBytes = AddrBits / 8 // unused
26  val DataBits = XLEN
27  val DataBytes = DataBits / 8
28  val CacheLineSize = 512
29  val SbufferSize = 16
30  val HasFPU = true
31  val FetchWidth = 8
32  val PredictWidth = FetchWidth * 2
33  val EnableBPU = true
34  val EnableBPD = false // enable backing predictor(like Tage) in BPUStage3
35  val EnableRAS = false
36  val HistoryLength = 64
37  val BtbSize = 256
38  // val BtbWays = 4
39  val BtbBanks = PredictWidth
40  // val BtbSets = BtbSize / BtbWays
41  val JbtacSize = 1024
42  val JbtacBanks = 8
43  val RasSize = 16
44  val IBufSize = 64
45  val DecodeWidth = 6
46  val RenameWidth = 6
47  val CommitWidth = 6
48  val BrqSize = 16
49  val IssQueSize = 8
50  val BrTagWidth = log2Up(BrqSize)
51  val NRPhyRegs = 128
52  val PhyRegIdxWidth = log2Up(NRPhyRegs)
53  val exuParameters = ExuParameters(
54    JmpCnt = 1,
55    AluCnt = 4,
56    MulCnt = 0,
57    MduCnt = 2,
58    FmacCnt = 0,
59    FmiscCnt = 0,
60    FmiscDivSqrtCnt = 0,
61    LduCnt = 2,
62    StuCnt = 2
63  )
64  val NRIntReadPorts = 8
65  val NRIntWritePorts = 8
66  val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt
67  val NRFpReadPorts = 14
68  val NRFpWritePorts = 8
69  val MoqSize = 16 // 64
70  val RoqSize = 32
71  val InnerRoqIdxWidth = log2Up(RoqSize)
72  val RoqIdxWidth = InnerRoqIdxWidth + 1
73  val InnerMoqIdxWidth = log2Up(MoqSize)
74  val MoqIdxWidth = InnerMoqIdxWidth + 1
75  val dpParams = DispatchParameters(
76    DqEnqWidth = 4,
77    IntDqSize = 64,
78    FpDqSize = 64,
79    LsDqSize = 64,
80    IntDqDeqWidth = 4,
81    FpDqDeqWidth = 4,
82    LsDqDeqWidth = 4
83  )
84  val DTLBSize = 32
85  val ITLBSize = 32
86}
87
88trait HasXSLog { this: Module =>
89  implicit val moduleName: String = this.name
90}
91
92abstract class XSModule extends Module
93  with HasXSParameter
94  with HasExceptionNO
95  with HasXSLog
96
97//remove this trait after impl module logic
98trait NeedImpl { this: Module =>
99  override protected def IO[T <: Data](iodef: T): T = {
100    val io = chisel3.experimental.IO(iodef)
101    io <> DontCare
102    io
103  }
104}
105
106abstract class XSBundle extends Bundle
107  with HasXSParameter
108
109case class XSConfig
110(
111  FPGAPlatform: Boolean = true,
112  EnableDebug: Boolean = true
113)
114
115object AddressSpace extends HasXSParameter {
116  // (start, size)
117  // address out of MMIO will be considered as DRAM
118  def mmio = List(
119    (0x30000000L, 0x10000000L),  // internal devices, such as CLINT and PLIC
120    (0x40000000L, 0x40000000L) // external devices
121  )
122
123  def isMMIO(addr: UInt): Bool = mmio.map(range => {
124    require(isPow2(range._2))
125    val bits = log2Up(range._2)
126    (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U
127  }).reduce(_ || _)
128}
129
130
131class XSCore(implicit p: XSConfig) extends XSModule with HasMEMConst {
132  val io = IO(new Bundle {
133    val imem = new SimpleBusC
134    val dmem = new SimpleBusC
135    val mmio = new SimpleBusUC
136    val frontend = Flipped(new SimpleBusUC())
137  })
138
139  io.imem <> DontCare
140
141  val dmemXbar = Module(new SimpleBusCrossbarNto1(n = 2, userBits = DcacheUserBundleWidth))
142
143  val front = Module(new Frontend)
144  val backend = Module(new Backend)
145  val mem = Module(new Memend)
146
147  front.io.backend <> backend.io.frontend
148  mem.io.backend   <> backend.io.mem
149
150  backend.io.memMMU.imem <> DontCare
151
152  val dtlb = TLB(
153    in = mem.io.dmem,
154    mem = dmemXbar.io.in(1),
155    flush = false.B,
156    csrMMU = backend.io.memMMU.dmem
157  )(TLBConfig(name = "dtlb", totalEntry = 64, userBits = DcacheUserBundleWidth))
158  dmemXbar.io.in(0) <> dtlb.io.out
159  // dmemXbar.io.in(1) <> io.frontend
160
161  io.frontend <> DontCare
162
163  io.dmem <> Cache(
164    in = dmemXbar.io.out,
165    mmio = Seq(io.mmio),
166    flush = "b00".U,
167    empty = dtlb.io.cacheEmpty,
168    enable = HasDcache
169  )(CacheConfig(name = "dcache", userBits = DcacheUserBundleWidth))
170
171}
172