1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import xiangshan.backend._ 8import xiangshan.backend.dispatch.DP1Parameters 9import xiangshan.backend.exu.ExuParameters 10import xiangshan.frontend._ 11import utils._ 12 13trait HasXSParameter { 14 val XLEN = 64 15 val HasMExtension = true 16 val HasCExtension = true 17 val HasDiv = true 18 val HasIcache = true 19 val HasDcache = true 20 val EnableStoreQueue = false 21 val AddrBits = 64 // AddrBits is used in some cases 22 val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits 23 val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits 24 val AddrBytes = AddrBits / 8 // unused 25 val DataBits = XLEN 26 val DataBytes = DataBits / 8 27 val CacheLineSize = 512 28 val CacheLineHalfWord = CacheLineSize / 16 29 val HasFPU = true 30 val FetchWidth = 8 31 val PredictWidth = FetchWidth * 2 32 val EnableBPU = true 33 val EnableBPD = false // enable backing predictor(like Tage) in BPUStage3 34 val EnableRAS = false 35 val HistoryLength = 64 36 val ExtHistoryLength = HistoryLength * 2 37 val UBtbWays = 16 38 val BtbWays = 2 39 val BtbSize = 256 40 // val BtbWays = 4 41 val BtbBanks = PredictWidth 42 // val BtbSets = BtbSize / BtbWays 43 val JbtacSize = 1024 44 val JbtacBanks = 8 45 val RasSize = 16 46 val IBufSize = 64 47 val DecodeWidth = 6 48 val RenameWidth = 6 49 val CommitWidth = 6 50 val BrqSize = 16 51 val IssQueSize = 8 52 val BrTagWidth = log2Up(BrqSize) 53 val NRPhyRegs = 128 54 val PhyRegIdxWidth = log2Up(NRPhyRegs) 55 val NRReadPorts = 14 56 val NRWritePorts = 8 57 val RoqSize = 128 58 val InnerRoqIdxWidth = log2Up(RoqSize) 59 val RoqIdxWidth = InnerRoqIdxWidth + 1 60 val IntDqDeqWidth = 4 61 val FpDqDeqWidth = 4 62 val LsDqDeqWidth = 4 63 val dp1Paremeters = DP1Parameters( 64 IntDqSize = 16, 65 FpDqSize = 16, 66 LsDqSize = 16 67 ) 68 val exuParameters = ExuParameters( 69 JmpCnt = 1, 70 AluCnt = 4, 71 MulCnt = 1, 72 MduCnt = 1, 73 FmacCnt = 0, 74 FmiscCnt = 0, 75 FmiscDivSqrtCnt = 0, 76 LduCnt = 0, 77 StuCnt = 1 78 ) 79} 80 81trait HasXSLog { this: Module => 82 implicit val moduleName: String = this.name 83} 84 85abstract class XSModule extends Module 86 with HasXSParameter 87 with HasExceptionNO 88 with HasXSLog 89 90//remove this trait after impl module logic 91trait NeedImpl { this: Module => 92 override protected def IO[T <: Data](iodef: T): T = { 93 val io = chisel3.experimental.IO(iodef) 94 io <> DontCare 95 io 96 } 97} 98 99abstract class XSBundle extends Bundle 100 with HasXSParameter 101 102case class XSConfig 103( 104 FPGAPlatform: Boolean = true, 105 EnableDebug: Boolean = true 106) 107 108object AddressSpace extends HasXSParameter { 109 // (start, size) 110 // address out of MMIO will be considered as DRAM 111 def mmio = List( 112 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 113 (0x40000000L, 0x40000000L) // external devices 114 ) 115 116 def isMMIO(addr: UInt): Bool = mmio.map(range => { 117 require(isPow2(range._2)) 118 val bits = log2Up(range._2) 119 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 120 }).reduce(_ || _) 121} 122 123 124class XSCore(implicit p: XSConfig) extends XSModule { 125 val io = IO(new Bundle { 126 val imem = new SimpleBusC 127 val dmem = new SimpleBusC 128 val mmio = new SimpleBusUC 129 val frontend = Flipped(new SimpleBusUC()) 130 }) 131 132 io.imem <> DontCare 133 134 val dmemXbar = Module(new SimpleBusCrossbarNto1(3)) 135 136 val front = Module(new Frontend) 137 val backend = Module(new Backend) 138 139 front.io.backend <> backend.io.frontend 140 141 backend.io.memMMU.imem <> DontCare 142 143 val dtlb = TLB( 144 in = backend.io.dmem, 145 mem = dmemXbar.io.in(1), 146 flush = false.B, 147 csrMMU = backend.io.memMMU.dmem 148 )(TLBConfig(name = "dtlb", totalEntry = 64)) 149 dmemXbar.io.in(0) <> dtlb.io.out 150 dmemXbar.io.in(2) <> io.frontend 151 152 io.dmem <> Cache( 153 in = dmemXbar.io.out, 154 mmio = Seq(io.mmio), 155 flush = "b00".U, 156 empty = dtlb.io.cacheEmpty, 157 enable = HasDcache 158 )(CacheConfig(name = "dcache")) 159 160 XSDebug("(req valid, ready | resp valid, ready) \n") 161 XSDebug("c-mem(%x %x %x| %x %x) c-coh(%x %x %x| %x %x) cache (%x %x %x| %x %x) tlb (%x %x %x| %x %x)\n", 162 io.dmem.mem.req.valid, 163 io.dmem.mem.req.ready, 164 io.dmem.mem.req.bits.addr, 165 io.dmem.mem.resp.valid, 166 io.dmem.mem.resp.ready, 167 io.dmem.coh.req.valid, 168 io.dmem.coh.req.ready, 169 io.dmem.coh.req.bits.addr, 170 io.dmem.coh.resp.valid, 171 io.dmem.coh.resp.ready, 172 dmemXbar.io.out.req.valid, 173 dmemXbar.io.out.req.ready, 174 dmemXbar.io.out.req.bits.addr, 175 dmemXbar.io.out.resp.valid, 176 dmemXbar.io.out.resp.ready, 177 backend.io.dmem.req.valid, 178 backend.io.dmem.req.ready, 179 backend.io.dmem.req.bits.addr, 180 backend.io.dmem.resp.valid, 181 backend.io.dmem.resp.ready 182 ) 183} 184