1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import utils._ 8 9trait HasIFUConst { this: XSModule => 10 val resetVector = 0x80000000L//TODO: set reset vec 11 val groupAlign = log2Up(FetchWidth * 4) 12 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 13 def snpc(pc: UInt): UInt = pc + (1 << groupAlign).U 14 15} 16 17class IFUIO extends XSBundle 18{ 19 val fetchPacket = DecoupledIO(new FetchPacket) 20 val redirect = Flipped(ValidIO(new Redirect)) 21 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 22 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 23 val icacheReq = DecoupledIO(new FakeIcacheReq) 24 val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp)) 25} 26 27 28class IFU extends XSModule with HasIFUConst 29{ 30 val io = IO(new IFUIO) 31// val bpu = if(EnableBPU) Module(new BPU) else Module(new FakeBPU) 32 val bpu = Module(new FakeBPU) 33 34 //------------------------- 35 // IF1 PC update 36 //------------------------- 37 //local 38 val if1_npc = WireInit(0.U(VAddrBits.W)) 39 val if1_valid = !reset.asBool 40 val if1_pc = RegInit(resetVector.U(VAddrBits.W)) 41 //next 42 val if2_ready = WireInit(false.B) 43 val if2_snpc = snpc(if1_pc) //TODO: calculate snpc according to mask of current fetch packet 44 val needflush = WireInit(false.B) 45 // when an RVI instruction is predicted as taken and it crosses over two fetch packets, 46 // IFU should not take this branch but fetch the latter half of the instruction sequentially, 47 // and take the jump target in the next fetch cycle 48 val if2_lateJumpLatch = WireInit(false.B) 49 val if2_lateJumpTarget = RegInit(0.U(VAddrBits.W)) 50 val if4_lateJumpLatch = WireInit(false.B) 51 val if4_lateJumpTarget = RegInit(0.U(VAddrBits.W)) 52 53 //pipe fire 54 val if1_fire = if1_valid && if2_ready || needflush 55 val if1_pcUpdate = if1_fire || needflush 56 57 bpu.io.in.pc.valid := if1_fire 58 bpu.io.in.pc.bits := if1_npc 59 bpu.io.redirect := io.redirect 60 bpu.io.inOrderBrInfo := io.inOrderBrInfo 61 62 XSDebug("[IF1]if1_valid:%d || if1_npc:0x%x || if1_pcUpdate:%d if1_pc:0x%x || if2_ready:%d",if1_valid,if1_npc,if1_pcUpdate,if1_pc,if2_ready) 63 XSDebug(false,if1_fire,"------IF1->fire!!!") 64 XSDebug(false,true.B,"\n") 65 66 //------------------------- 67 // IF2 btb response 68 // icache visit 69 //------------------------- 70 //local 71 val if2_valid = RegEnable(next=if1_valid,init=false.B,enable=if1_fire) 72 val if2_pc = if1_pc 73 val if2_btb_taken = bpu.io.btbOut.valid && bpu.io.btbOut.bits.redirect 74 val if2_btb_lateJump = WireInit(false.B) 75 val if2_btb_insMask = Mux(if2_btb_taken, bpu.io.btbOut.bits.instrValid.asUInt, Fill(FetchWidth*2, 1.U(1.W))) // TODO: FIX THIS 76 val if2_btb_target = Mux(if2_btb_lateJump, if2_snpc, bpu.io.btbOut.bits.target) 77 78 if2_lateJumpLatch := BoolStopWatch(if2_btb_lateJump, if1_fire, startHighPriority = true) 79 // since late jump target should be taken after the latter half of late jump instr is fetched, we need to latch this target 80 when (if2_btb_lateJump) { 81 if2_lateJumpTarget := bpu.io.btbOut.bits.target 82 } 83 84 //next 85 val if3_ready = WireInit(false.B) 86 87 //pipe fire 88 val if2_fire = if2_valid && if3_ready && io.icacheReq.fire() 89 if2_ready := (if2_fire) || !if2_valid 90 91 io.icacheReq.valid := if2_valid 92 io.icacheReq.bits.addr := if2_pc 93 94 when(RegNext(reset.asBool) && !reset.asBool){ 95 //when((GTimer() === 501.U)){ //TODO:this is ugly 96 XSDebug("RESET....\n") 97 if1_npc := resetVector.U(VAddrBits.W) 98 }.elsewhen (if2_fire) { 99 if1_npc := Mux(if4_lateJumpLatch, if4_lateJumpTarget, Mux(if2_lateJumpLatch, if2_lateJumpTarget, if2_snpc)) 100 }.otherwise { 101 if1_npc := if1_pc 102 } 103 104 when(if1_pcUpdate) 105 { 106 if1_pc := if1_npc 107 } 108 109 // when if2 fire and if2 redirects, update npc 110 when(if2_fire && if2_btb_taken) 111 { 112 if1_npc := if2_btb_target 113 } 114 115 bpu.io.in.pc.valid := if1_fire && !if2_btb_lateJump 116 117 XSDebug("[IF2]if2_valid:%d || if2_pc:0x%x || if3_ready:%d ",if2_valid,if2_pc,if3_ready) 118 XSDebug(false,if2_fire,"------IF2->fire!!!") 119 XSDebug(false,true.B,"\n") 120 XSDebug("[IF2-Icache-Req] icache_in_valid:%d icache_in_ready:%d\n",io.icacheReq.valid,io.icacheReq.ready) 121 XSDebug("[IF2-BPU-out]if2_btbTaken:%d || if2_btb_insMask:%b || if2_btb_target:0x%x \n",if2_btb_taken,if2_btb_insMask.asUInt,if2_btb_target) 122 //------------------------- 123 // IF3 icache hit check 124 //------------------------- 125 //local 126 val if3_valid = RegEnable(next=if2_valid,init=false.B,enable=if2_fire) 127 val if3_pc = RegEnable(if2_pc,if2_fire) 128 val if3_npc = RegEnable(if1_npc, if2_fire) 129 val if3_btb_target = RegEnable(Mux(if2_lateJumpLatch, if2_lateJumpTarget, Mux(if2_btb_lateJump, bpu.io.btbOut.bits.target, if2_btb_target)), if2_fire) 130 val if3_btb_taken = RegEnable(Mux(if2_lateJumpLatch, true.B, if2_btb_taken), if2_fire) 131 val if3_btb_insMask = RegEnable(Mux(if2_lateJumpLatch, 1.U((FetchWidth*2).W), if2_btb_insMask), if2_fire) 132 val if3_btb_lateJump = RegEnable(if2_btb_lateJump, if2_fire) 133 134 //next 135 val if4_ready = WireInit(false.B) 136 137 //pipe fire 138 val if3_fire = if3_valid && if4_ready 139 if3_ready := if3_fire || !if3_valid 140 141 142 XSDebug("[IF3]if3_valid:%d || if3_pc:0x%x if3_npc:0x%x || if4_ready:%d ",if3_valid,if3_pc,if3_npc,if4_ready) 143 XSDebug("[IF3]if3_btb_taken:%d if3_btb_insMask:%b if3_btb_lateJump:%d if3_btb_target:0x%x\n", 144 if3_btb_taken, if3_btb_insMask, if3_btb_lateJump, if3_btb_target) 145 XSDebug(false,if3_fire,"------IF3->fire!!!") 146 XSDebug(false,true.B,"\n") 147 148 //------------------------- 149 // IF4 icache response 150 // RAS result 151 // taget generate 152 //------------------------- 153 val if4_valid = RegEnable(next=if3_valid,init=false.B,enable=if3_fire) 154 val if4_pc = RegEnable(if3_pc,if3_fire) 155 val if4_npc = RegEnable(if3_npc,if3_fire) 156 val if4_btb_target = RegEnable(if3_btb_target,if3_fire) 157 val if4_btb_taken = RegEnable(if3_btb_taken,if3_fire) 158 val if4_btb_insMask = RegEnable(if3_btb_insMask, if3_fire) 159 val if4_btb_lateJump = RegEnable(if3_btb_lateJump, if3_fire) 160 val if4_tage_taken = bpu.io.tageOut.valid && bpu.io.tageOut.bits.redirect 161 val if4_tage_lateJump = if4_tage_taken && bpu.io.tageOut.bits.lateJump && !io.redirect.valid 162 val if4_tage_insMask = bpu.io.tageOut.bits.instrValid 163 val if4_snpc = if4_pc + (PopCount(if4_tage_insMask) << 1.U) 164 val if4_tage_target = Mux(if4_tage_lateJump, if4_snpc, bpu.io.tageOut.bits.target) 165 166 if2_btb_lateJump := if2_btb_taken && bpu.io.btbOut.bits.lateJump && !io.redirect.valid && !if4_tage_taken 167 168 if4_lateJumpLatch := BoolStopWatch(if4_tage_lateJump, if1_fire, startHighPriority = true) 169 when (if4_tage_lateJump) { 170 if4_lateJumpTarget := bpu.io.tageOut.bits.target 171 } 172 173 bpu.io.in.pc.valid := if1_fire && !if2_btb_lateJump && !if4_tage_lateJump 174 175 XSDebug("[IF4]if4_valid:%d || if4_pc:0x%x if4_npc:0x%x\n",if4_valid,if4_pc,if4_npc) 176 XSDebug("[IF4] if4_btb_taken:%d if4_btb_lateJump:%d if4_btb_insMask:%b if4_btb_target:0x%x\n",if4_btb_taken, if4_btb_lateJump, if4_btb_insMask.asUInt, if4_btb_target) 177 XSDebug("[IF4-TAGE-out]if4_tage_taken:%d if4_tage_lateJump:%d if4_tage_insMask:%b if4_tage_target:0x%x\n",if4_tage_taken,if4_tage_lateJump,if4_tage_insMask.asUInt,if4_tage_target) 178 XSDebug("[IF4-ICACHE-RESP]icacheResp.valid:%d icacheResp.ready:%d\n",io.icacheResp.valid,io.icacheResp.ready) 179 180 when(io.icacheResp.fire() && if4_tage_taken &&if4_valid) 181 { 182 if1_npc := if4_tage_target 183 } 184 185 //redirect: miss predict 186 when(io.redirect.valid){ 187 if1_npc := io.redirect.bits.target 188 } 189 XSDebug(io.redirect.valid, "[IFU-REDIRECT] target:0x%x \n", io.redirect.bits.target) 190 191 192 //flush pipline 193 // if(EnableBPD){needflush := (if4_valid && if4_tage_taken) || io.redirectInfo.flush() } 194 // else {needflush := io.redirectInfo.flush()} 195 needflush := (if4_valid && if4_tage_taken && io.icacheResp.fire()) || io.redirect.valid 196 when(needflush){ 197 if3_valid := false.B 198 if4_valid := false.B 199 } 200 //flush ICache 201 io.icacheReq.bits.flush := needflush 202 203 //Output -> iBuffer 204 //io.fetchPacket <> DontCare 205 if4_ready := io.fetchPacket.ready && (io.icacheResp.valid || !if4_valid) && (GTimer() > 500.U) 206 io.fetchPacket.valid := if4_valid && !io.redirect.valid 207 io.fetchPacket.bits.instrs := io.icacheResp.bits.icacheOut 208 io.fetchPacket.bits.mask := Mux(if4_lateJumpLatch, 1.U((FetchWidth*2).W), 209 Mux(if4_tage_taken, Fill(FetchWidth*2, 1.U(1.W)) & if4_tage_insMask.asUInt, 210 Fill(FetchWidth*2, 1.U(1.W)) & if4_btb_insMask.asUInt)) 211 io.fetchPacket.bits.pc := if4_pc 212 213 XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] starPC:0x%x GroupPC:0x%xn\n",if4_pc.asUInt,groupPC(if4_pc).asUInt) 214 XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] instrmask %b\n",io.fetchPacket.bits.mask.asUInt) 215 for(i <- 0 until (FetchWidth*2)) { 216 when (if4_btb_taken && !if4_tage_taken && i.U === OHToUInt(HighestBit(if4_btb_insMask.asUInt, FetchWidth*2))) { 217 io.fetchPacket.bits.pnpc(i) := if4_btb_target 218 if (i != 0) { 219 when (!io.icacheResp.bits.predecode.pd(i).isRVC && !if4_btb_lateJump) { 220 io.fetchPacket.bits.pnpc(i-1) := if4_btb_target 221 } 222 } 223 }.elsewhen (if4_tage_taken && i.U === OHToUInt(HighestBit(if4_tage_insMask.asUInt, FetchWidth*2))) { 224 io.fetchPacket.bits.pnpc(i) := Mux(if4_tage_lateJump, bpu.io.tageOut.bits.target, if4_tage_target) 225 if (i != 0) { 226 when (!io.icacheResp.bits.predecode.pd(i).isRVC && !if4_tage_lateJump) { 227 io.fetchPacket.bits.pnpc(i-1) := if4_tage_target 228 } 229 } 230 }.otherwise { 231 io.fetchPacket.bits.pnpc(i) := if4_pc + (i.U << 1.U) + Mux(io.icacheResp.bits.predecode.pd(i).isRVC, 2.U, 4.U) 232 } 233 XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] instruction %x pnpc:0x%x\n", 234 Mux((i.U)(0), io.fetchPacket.bits.instrs(i>>1)(31,16), io.fetchPacket.bits.instrs(i>>1)(15,0)), 235 io.fetchPacket.bits.pnpc(i)) 236 } 237 io.fetchPacket.bits.hist := bpu.io.tageOut.bits.hist 238 // io.fetchPacket.bits.btbVictimWay := bpu.io.tageOut.bits.btbVictimWay 239 io.fetchPacket.bits.predCtr := bpu.io.tageOut.bits.predCtr 240 io.fetchPacket.bits.btbHit := bpu.io.tageOut.bits.btbHit 241 io.fetchPacket.bits.tageMeta := bpu.io.tageOut.bits.tageMeta 242 io.fetchPacket.bits.rasSp := bpu.io.tageOut.bits.rasSp 243 io.fetchPacket.bits.rasTopCtr := bpu.io.tageOut.bits.rasTopCtr 244 bpu.io.tageOut.ready := io.fetchPacket.ready 245 246 //to BPU 247 bpu.io.predecode.valid := io.icacheResp.fire() && if4_valid 248 bpu.io.predecode.bits <> io.icacheResp.bits.predecode 249 //TODO: consider RVC && consider cross cacheline fetch 250 bpu.io.predecode.bits.mask := Fill(FetchWidth*2, 1.U(1.W)) 251 // bpu.io.redirectInfo := io.redirectInfo 252 bpu.io.predecode.bits.isRVC := 0.U.asTypeOf(Vec(FetchWidth*2, Bool())) 253 io.icacheResp.ready := io.fetchPacket.ready && (GTimer() > 500.U) 254 255}