1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils.XSInfo 7 8class Rename extends XSModule { 9 val io = IO(new Bundle() { 10 val redirect = Flipped(ValidIO(new Redirect)) 11 val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) 12 val wbIntResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput))) 13 val wbFpResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput))) 14 val intRfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W))) 15 val fpRfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W))) 16 val intPregRdy = Vec(NRReadPorts, Output(Bool())) 17 val fpPregRdy = Vec(NRReadPorts, Output(Bool())) 18 // from decode buffer 19 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 20 // to dispatch1 21 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 22 }) 23 24 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 25 XSInfo( 26 in.valid && in.ready, 27 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 28 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 29 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 30 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 31 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 32 p"old_pdest:${out.bits.old_pdest} " + 33 p"out v:${out.valid} r:${out.ready}\n" 34 ) 35 } 36 37 for((x,y) <- io.in.zip(io.out)){ 38 printRenameInfo(x, y) 39 } 40 41 val fpFreeList, intFreeList = Module(new FreeList).io 42 val fpRat = Module(new RenameTable(float = true)).io 43 val intRat = Module(new RenameTable(float = false)).io 44 val fpBusyTable, intBusyTable = Module(new BusyTable).io 45 46 fpFreeList.redirect := io.redirect 47 intFreeList.redirect := io.redirect 48 49 val flush = io.redirect.valid && io.redirect.bits.isException 50 fpRat.flush := flush 51 intRat.flush := flush 52 fpBusyTable.flush := flush 53 intBusyTable.flush := flush 54 55 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 56 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 57 } 58 59 val uops = Wire(Vec(RenameWidth, new MicroOp)) 60 61 uops.foreach( uop => { 62// uop.brMask := DontCare 63// uop.brTag := DontCare 64 uop.src1State := DontCare 65 uop.src2State := DontCare 66 uop.src3State := DontCare 67 uop.roqIdx := DontCare 68 }) 69 70 var lastReady = WireInit(io.out(0).ready) 71 // debug assert 72 val outRdy = Cat(io.out.map(_.ready)) 73 assert(outRdy===0.U || outRdy.andR()) 74 for(i <- 0 until RenameWidth) { 75 uops(i).cf := io.in(i).bits.cf 76 uops(i).ctrl := io.in(i).bits.ctrl 77 uops(i).brTag := io.in(i).bits.brTag 78 79 val inValid = io.in(i).valid 80 81 // alloc a new phy reg 82 val needFpDest = inValid && needDestReg(fp = true, io.in(i).bits) 83 val needIntDest = inValid && needDestReg(fp = false, io.in(i).bits) 84 fpFreeList.allocReqs(i) := needFpDest && lastReady 85 intFreeList.allocReqs(i) := needIntDest && lastReady 86 val fpCanAlloc = fpFreeList.canAlloc(i) 87 val intCanAlloc = intFreeList.canAlloc(i) 88 val this_can_alloc = Mux( 89 needIntDest, 90 intCanAlloc, 91 Mux( 92 needFpDest, 93 fpCanAlloc, 94 true.B 95 ) 96 ) 97 io.in(i).ready := lastReady && this_can_alloc 98 99 // do checkpoints when a branch inst come 100 for(fl <- Seq(fpFreeList, intFreeList)){ 101 fl.cpReqs(i).valid := inValid 102 fl.cpReqs(i).bits := io.in(i).bits.brTag 103 } 104 105 lastReady = io.in(i).ready 106 107 uops(i).pdest := Mux(needIntDest, 108 intFreeList.pdests(i), 109 Mux( 110 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 111 0.U, fpFreeList.pdests(i) 112 ) 113 ) 114 115 io.out(i).valid := io.in(i).fire() 116 io.out(i).bits := uops(i) 117 118 // write rename table 119 def writeRat(fp: Boolean) = { 120 val rat = if(fp) fpRat else intRat 121 val freeList = if(fp) fpFreeList else intFreeList 122 val busyTable = if(fp) fpBusyTable else intBusyTable 123 // speculative inst write 124 val specWen = freeList.allocReqs(i) && freeList.canAlloc(i) 125 // walk back write 126 val commitDestValid = io.roqCommits(i).valid && needDestReg(fp, io.roqCommits(i).bits.uop) 127 val walkWen = commitDestValid && io.roqCommits(i).bits.isWalk 128 129 rat.specWritePorts(i).wen := specWen || walkWen 130 rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits(i).bits.uop.ctrl.ldest) 131 rat.specWritePorts(i).wdata := Mux(specWen, freeList.pdests(i), io.roqCommits(i).bits.uop.old_pdest) 132 133 XSInfo(walkWen, 134 {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(io.roqCommits(i).bits.uop.cf.pc)}" + 135 p" ldst:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n" 136 ) 137 138 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits(i).bits.isWalk 139 rat.archWritePorts(i).addr := io.roqCommits(i).bits.uop.ctrl.ldest 140 rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest 141 142 XSInfo(rat.archWritePorts(i).wen, 143 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 144 p" pdest:${rat.archWritePorts(i).wdata}\n" 145 ) 146 147 freeList.deallocReqs(i) := rat.archWritePorts(i).wen 148 freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest 149 150 // set phy reg status to busy 151 busyTable.allocPregs(i).valid := specWen 152 busyTable.allocPregs(i).bits := freeList.pdests(i) 153 } 154 155 writeRat(fp = false) 156 writeRat(fp = true) 157 158 // read rename table 159 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 160 val rat = if(fp) fpRat else intRat 161 val srcCnt = lsrcList.size 162 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 163 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 164 for(k <- 0 until srcCnt+1){ 165 val rportIdx = i * (srcCnt+1) + k 166 if(k != srcCnt){ 167 rat.readPorts(rportIdx).addr := lsrcList(k) 168 psrcVec(k) := rat.readPorts(rportIdx).rdata 169 } else { 170 rat.readPorts(rportIdx).addr := ldest 171 old_pdest := rat.readPorts(rportIdx).rdata 172 } 173 } 174 (psrcVec, old_pdest) 175 } 176 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 177 val ldest = uops(i).ctrl.ldest 178 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 179 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 180 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 181 uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 182 uops(i).psrc3 := fpPhySrcVec(2) 183 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 184 } 185 186 187 def updateBusyTable(fp: Boolean) = { 188 val wbResults = if(fp) io.wbFpResults else io.wbIntResults 189 val busyTable = if(fp) fpBusyTable else intBusyTable 190 for((wb, setPhyRegRdy) <- wbResults.zip(busyTable.wbPregs)){ 191 setPhyRegRdy.valid := wb.valid && needDestReg(fp, wb.bits.uop) 192 setPhyRegRdy.bits := wb.bits.uop.pdest 193 } 194 } 195 196 updateBusyTable(false) 197 updateBusyTable(true) 198 199 intBusyTable.rfReadAddr <> io.intRfReadAddr 200 intBusyTable.pregRdy <> io.intPregRdy 201 fpBusyTable.rfReadAddr <> io.fpRfReadAddr 202 fpBusyTable.pregRdy <> io.fpPregRdy 203} 204