xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision f226232f57e6b3af2007622c841418e1055b0a21) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig}
7import xiangshan.backend._
8import xiangshan.backend.dispatch.DP1Parameters
9import xiangshan.backend.exu.ExuParameters
10import xiangshan.frontend._
11import utils._
12
13trait HasXSParameter {
14  val XLEN = 64
15  val HasMExtension = true
16  val HasCExtension = true
17  val HasDiv = true
18  val HasIcache = true
19  val HasDcache = true
20  val EnableStoreQueue = false
21  val AddrBits = 64 // AddrBits is used in some cases
22  val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits
23  val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits
24  val AddrBytes = AddrBits / 8 // unused
25  val DataBits = XLEN
26  val DataBytes = DataBits / 8
27  val CacheLineSize = 512
28  val CacheLineHalfWord = CacheLineSize / 16
29  val HasFPU = true
30  val FetchWidth = 8
31  val PredictWidth = FetchWidth * 2
32  val EnableBPU = true
33  val EnableBPD = false // enable backing predictor(like Tage) in BPUStage3
34  val EnableRAS = false
35  val HistoryLength = 64
36  val ExtHistoryLength = HistoryLength * 2
37  val BtbSize = 256
38  // val BtbWays = 4
39  val BtbBanks = PredictWidth
40  // val BtbSets = BtbSize / BtbWays
41  val JbtacSize = 1024
42  val JbtacBanks = 8
43  val RasSize = 16
44  val IBufSize = 64
45  val DecodeWidth = 6
46  val RenameWidth = 6
47  val CommitWidth = 6
48  val BrqSize = 16
49  val IssQueSize = 8
50  val BrTagWidth = log2Up(BrqSize)
51  val NRPhyRegs = 128
52  val PhyRegIdxWidth = log2Up(NRPhyRegs)
53  val NRReadPorts = 14
54  val NRWritePorts = 8
55  val RoqSize = 128
56  val InnerRoqIdxWidth = log2Up(RoqSize)
57  val RoqIdxWidth = InnerRoqIdxWidth + 1
58  val IntDqDeqWidth = 4
59  val FpDqDeqWidth = 4
60  val LsDqDeqWidth = 4
61  val dp1Paremeters = DP1Parameters(
62    IntDqSize = 16,
63    FpDqSize = 16,
64    LsDqSize = 16
65  )
66  val exuParameters = ExuParameters(
67    JmpCnt = 1,
68    AluCnt = 4,
69    MulCnt = 1,
70    MduCnt = 1,
71    FmacCnt = 0,
72    FmiscCnt = 0,
73    FmiscDivSqrtCnt = 0,
74    LduCnt = 0,
75    StuCnt = 1
76  )
77}
78
79trait HasXSLog { this: Module =>
80  implicit val moduleName: String = this.name
81}
82
83abstract class XSModule extends Module
84  with HasXSParameter
85  with HasExceptionNO
86  with HasXSLog
87
88//remove this trait after impl module logic
89trait NeedImpl { this: Module =>
90  override protected def IO[T <: Data](iodef: T): T = {
91    val io = chisel3.experimental.IO(iodef)
92    io <> DontCare
93    io
94  }
95}
96
97abstract class XSBundle extends Bundle
98  with HasXSParameter
99
100case class XSConfig
101(
102  FPGAPlatform: Boolean = true,
103  EnableDebug: Boolean = true
104)
105
106object AddressSpace extends HasXSParameter {
107  // (start, size)
108  // address out of MMIO will be considered as DRAM
109  def mmio = List(
110    (0x30000000L, 0x10000000L),  // internal devices, such as CLINT and PLIC
111    (0x40000000L, 0x40000000L) // external devices
112  )
113
114  def isMMIO(addr: UInt): Bool = mmio.map(range => {
115    require(isPow2(range._2))
116    val bits = log2Up(range._2)
117    (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U
118  }).reduce(_ || _)
119}
120
121
122class XSCore(implicit p: XSConfig) extends XSModule {
123  val io = IO(new Bundle {
124    val imem = new SimpleBusC
125    val dmem = new SimpleBusC
126    val mmio = new SimpleBusUC
127    val frontend = Flipped(new SimpleBusUC())
128  })
129
130  io.imem <> DontCare
131
132  val dmemXbar = Module(new SimpleBusCrossbarNto1(3))
133
134  val front = Module(new Frontend)
135  val backend = Module(new Backend)
136
137  front.io.backend <> backend.io.frontend
138
139  backend.io.memMMU.imem <> DontCare
140
141  val dtlb = TLB(
142    in = backend.io.dmem,
143    mem = dmemXbar.io.in(1),
144    flush = false.B,
145    csrMMU = backend.io.memMMU.dmem
146  )(TLBConfig(name = "dtlb", totalEntry = 64))
147  dmemXbar.io.in(0) <> dtlb.io.out
148  dmemXbar.io.in(2) <> io.frontend
149
150  io.dmem <> Cache(
151    in = dmemXbar.io.out,
152    mmio = Seq(io.mmio),
153    flush = "b00".U,
154    empty = dtlb.io.cacheEmpty,
155    enable = HasDcache
156  )(CacheConfig(name = "dcache"))
157
158  XSDebug("(req valid, ready | resp valid, ready) \n")
159  XSDebug("c-mem(%x %x %x| %x %x) c-coh(%x %x %x| %x %x) cache (%x %x %x| %x %x) tlb (%x %x %x| %x %x)\n",
160    io.dmem.mem.req.valid,
161    io.dmem.mem.req.ready,
162    io.dmem.mem.req.bits.addr,
163    io.dmem.mem.resp.valid,
164    io.dmem.mem.resp.ready,
165    io.dmem.coh.req.valid,
166    io.dmem.coh.req.ready,
167    io.dmem.coh.req.bits.addr,
168    io.dmem.coh.resp.valid,
169    io.dmem.coh.resp.ready,
170    dmemXbar.io.out.req.valid,
171    dmemXbar.io.out.req.ready,
172    dmemXbar.io.out.req.bits.addr,
173    dmemXbar.io.out.resp.valid,
174    dmemXbar.io.out.resp.ready,
175    backend.io.dmem.req.valid,
176    backend.io.dmem.req.ready,
177    backend.io.dmem.req.bits.addr,
178    backend.io.dmem.resp.valid,
179    backend.io.dmem.resp.ready
180  )
181}
182