1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import top.Parameters 8import xiangshan.backend._ 9import xiangshan.backend.dispatch.DispatchParameters 10import xiangshan.backend.exu.ExuParameters 11import xiangshan.frontend._ 12import xiangshan.mem._ 13import utils._ 14import xiangshan.mem.cache.DcacheUserBundle 15 16case class XSCoreParameters 17( 18 XLEN: Int = 64, 19 HasMExtension: Boolean = true, 20 HasCExtension: Boolean = true, 21 HasDiv: Boolean = true, 22 HasICache: Boolean = true, 23 HasDCache: Boolean = true, 24 EnableStoreQueue: Boolean = true, 25 AddrBits: Int = 64, 26 VAddrBits: Int = 39, 27 PAddrBits: Int = 32, 28 HasFPU: Boolean = true, 29 FectchWidth: Int = 8, 30 EnableBPU: Boolean = true, 31 EnableBPD: Boolean = false, 32 EnableRAS: Boolean = false, 33 EnableLB: Boolean = false, 34 HistoryLength: Int = 64, 35 BtbSize: Int = 256, 36 JbtacSize: Int = 1024, 37 JbtacBanks: Int = 8, 38 RasSize: Int = 16, 39 CacheLineSize: Int = 512, 40 UBtbWays: Int = 16, 41 BtbWays: Int = 2, 42 IBufSize: Int = 64, 43 DecodeWidth: Int = 6, 44 RenameWidth: Int = 6, 45 CommitWidth: Int = 6, 46 BrqSize: Int = 16, 47 IssQueSize: Int = 8, 48 NRPhyRegs: Int = 128, 49 NRIntReadPorts: Int = 8, 50 NRIntWritePorts: Int = 8, 51 NRFpReadPorts: Int = 14, 52 NRFpWritePorts: Int = 8, 53 MoqSize: Int = 16, 54 RoqSize: Int = 32, 55 IntDqDeqWidth: Int = 4, 56 FpDqDeqWidth: Int = 4, 57 LsDqDeqWidth: Int = 4, 58 dpParams: DispatchParameters = DispatchParameters( 59 DqEnqWidth = 4, 60 IntDqSize = 64, 61 FpDqSize = 64, 62 LsDqSize = 64, 63 IntDqDeqWidth = 4, 64 FpDqDeqWidth = 4, 65 LsDqDeqWidth = 4 66 ), 67 exuParameters: ExuParameters = ExuParameters( 68 JmpCnt = 1, 69 AluCnt = 4, 70 MulCnt = 0, 71 MduCnt = 2, 72 FmacCnt = 0, 73 FmiscCnt = 0, 74 FmiscDivSqrtCnt = 0, 75 LduCnt = 2, 76 StuCnt = 2 77 ), 78 LoadPipelineWidth: Int = 2, 79 StorePipelineWidth: Int = 2, 80 StoreBufferSize: Int = 16, 81 RefillSize: Int = 512, 82 TlbEntrySize: Int = 32, 83 TlbL2EntrySize: Int = 256, // or 512 84 PtwL1EntrySize: Int = 16, 85 PtwL2EntrySize: Int = 256 86) 87 88 89trait HasXSParameter { 90 91 val core = Parameters.get.coreParameters 92 val env = Parameters.get.envParameters 93 94 val XLEN = core.XLEN 95 val HasMExtension = core.HasMExtension 96 val HasCExtension = core.HasCExtension 97 val HasDiv = core.HasDiv 98 val HasIcache = core.HasICache 99 val HasDcache = core.HasDCache 100 val EnableStoreQueue = core.EnableStoreQueue 101 val AddrBits = core.AddrBits // AddrBits is used in some cases 102 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 103 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 104 val AddrBytes = AddrBits / 8 // unused 105 val DataBits = XLEN 106 val DataBytes = DataBits / 8 107 val HasFPU = core.HasFPU 108 val FetchWidth = core.FectchWidth 109 val PredictWidth = FetchWidth * 2 110 val EnableBPU = core.EnableBPU 111 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 112 val EnableRAS = core.EnableRAS 113 val EnableLB = core.EnableLB 114 val HistoryLength = core.HistoryLength 115 val BtbSize = core.BtbSize 116 // val BtbWays = 4 117 val BtbBanks = PredictWidth 118 // val BtbSets = BtbSize / BtbWays 119 val JbtacSize = core.JbtacSize 120 val JbtacBanks = core.JbtacBanks 121 val RasSize = core.RasSize 122 val CacheLineSize = core.CacheLineSize 123 val CacheLineHalfWord = CacheLineSize / 16 124 val ExtHistoryLength = HistoryLength * 2 125 val UBtbWays = core.UBtbWays 126 val BtbWays = core.BtbWays 127 val IBufSize = core.IBufSize 128 val DecodeWidth = core.DecodeWidth 129 val RenameWidth = core.RenameWidth 130 val CommitWidth = core.CommitWidth 131 val BrqSize = core.BrqSize 132 val IssQueSize = core.IssQueSize 133 val BrTagWidth = log2Up(BrqSize) 134 val NRPhyRegs = core.NRPhyRegs 135 val PhyRegIdxWidth = log2Up(NRPhyRegs) 136 val MoqSize = core.MoqSize // 64 137 val RoqSize = core.RoqSize 138 val InnerRoqIdxWidth = log2Up(RoqSize) 139 val RoqIdxWidth = InnerRoqIdxWidth + 1 140 val InnerMoqIdxWidth = log2Up(MoqSize) 141 val MoqIdxWidth = InnerMoqIdxWidth + 1 142 val IntDqDeqWidth = core.IntDqDeqWidth 143 val FpDqDeqWidth = core.FpDqDeqWidth 144 val LsDqDeqWidth = core.LsDqDeqWidth 145 val dpParams = core.dpParams 146 val exuParameters = core.exuParameters 147 val NRIntReadPorts = core.NRIntReadPorts 148 val NRIntWritePorts = core.NRIntWritePorts 149 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 150 val NRFpReadPorts = core.NRFpReadPorts 151 val NRFpWritePorts = core.NRFpWritePorts 152 val LoadPipelineWidth = core.LoadPipelineWidth 153 val StorePipelineWidth = core.StorePipelineWidth 154 val StoreBufferSize = core.StoreBufferSize 155 val RefillSize = core.RefillSize 156 val TLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 157 val TlbEntrySize = core.TlbEntrySize 158 val TlbL2EntrySize = core.TlbL2EntrySize 159 val PtwL1EntrySize = core.PtwL1EntrySize 160 val PtwL2EntrySize = core.PtwL2EntrySize 161} 162 163trait HasXSLog { this: Module => 164 implicit val moduleName: String = this.name 165} 166 167abstract class XSModule extends Module 168 with HasXSParameter 169 with HasExceptionNO 170 with HasXSLog 171 172//remove this trait after impl module logic 173trait NeedImpl { this: Module => 174 override protected def IO[T <: Data](iodef: T): T = { 175 val io = chisel3.experimental.IO(iodef) 176 io <> DontCare 177 io 178 } 179} 180 181abstract class XSBundle extends Bundle 182 with HasXSParameter 183 184case class EnviromentParameters 185( 186 FPGAPlatform: Boolean = true, 187 EnableDebug: Boolean = false 188) 189 190object AddressSpace extends HasXSParameter { 191 // (start, size) 192 // address out of MMIO will be considered as DRAM 193 def mmio = List( 194 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 195 (0x40000000L, 0x40000000L) // external devices 196 ) 197 198 def isMMIO(addr: UInt): Bool = mmio.map(range => { 199 require(isPow2(range._2)) 200 val bits = log2Up(range._2) 201 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 202 }).reduce(_ || _) 203} 204 205 206class XSCore extends XSModule { 207 val io = IO(new Bundle { 208 val imem = new SimpleBusC 209 val dmem = new SimpleBusC 210 val mmio = new SimpleBusUC 211 val frontend = Flipped(new SimpleBusUC()) 212 }) 213 214 io.imem <> DontCare 215 216 val DcacheUserBundleWidth = (new DcacheUserBundle).getWidth 217 218 val dmemXbar = Module(new SimpleBusCrossbarNto1(n = 2, userBits = DcacheUserBundleWidth)) 219 220 val front = Module(new Frontend) 221 val backend = Module(new Backend) 222 val mem = Module(new Memend) 223 224 front.io.backend <> backend.io.frontend 225 mem.io.backend <> backend.io.mem 226 227 backend.io.memMMU.imem <> DontCare 228 229 val dtlb = TLB( 230 in = mem.io.dmem, 231 mem = dmemXbar.io.in(1), 232 flush = false.B, 233 csrMMU = backend.io.memMMU.dmem 234 )(TLBConfig(name = "dtlb", totalEntry = 64, userBits = DcacheUserBundleWidth)) 235 dmemXbar.io.in(0) <> dtlb.io.out 236 // dmemXbar.io.in(1) <> io.frontend 237 238 io.frontend <> DontCare 239 240 io.dmem <> Cache( 241 in = dmemXbar.io.out, 242 mmio = Seq(io.mmio), 243 flush = "b00".U, 244 empty = dtlb.io.cacheEmpty, 245 enable = HasDcache 246 )(CacheConfig(name = "dcache", userBits = DcacheUserBundleWidth)) 247 248} 249