xref: /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala (revision f226232f57e6b3af2007622c841418e1055b0a21) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import utils._
6import xiangshan._
7import xiangshan.backend.ALUOpType
8import xiangshan.backend.JumpOpType
9
10class BPUStage1To2IO extends XSBundle {
11  // TODO
12}
13
14class BPUStage2To3IO extends XSBundle {
15  // TODO
16}
17
18class BPUStage1 extends XSModule {
19  val io = IO(new Bundle() {
20    val flush = Input(Bool())
21    val in = new Bundle { val pc = Flipped(ValidIO(UInt(VAddrBits.W))) }
22    val s1_out = Decoupled(new BranchPrediction)
23    val out = Decoupled(new BPUStage1To2IO)
24    val redirect = Flipped(ValidIO(new Redirect)) // used to fix ghr
25    val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
26    val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
27  })
28
29}
30
31class BPUStage2 extends XSModule {
32  val io = IO(new Bundle() {
33    val flush = Input(Bool())
34    val in = Flipped(Decoupled(new BPUStage1To2IO))
35    val s2_out = Decoupled(new BranchPrediction)
36    val out = Decoupled(new BPUStage2To3IO)
37    val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) // delete this if useless
38    val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) // delete this if useless
39  })
40
41}
42
43class BPUStage3 extends XSModule {
44  val io = IO(new Bundle() {
45    val flush = Input(Bool())
46    val in = Flipped(Decoupled(new BPUStage2To3IO))
47    val s3_out = Decoupled(new BranchPrediction)
48    val predecode = Flipped(ValidIO(new Predecode))
49  })
50
51}
52
53class BPU extends XSModule {
54  val io = IO(new Bundle() {
55    // from backend
56    val redirect = Flipped(ValidIO(new Redirect))
57    val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
58    val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
59    // from ifu, frontend redirect
60    val flush = Input(UInt(3.W))
61    // from if1
62    val in = new Bundle { val pc = Flipped(ValidIO(UInt(VAddrBits.W))) }
63    // to if2/if3/if4
64    val out = Vec(3, Decoupled(new BranchPrediction))
65    // from if4
66    val predecode = Flipped(ValidIO(new Predecode))
67    // to if4, some bpu info used for updating
68    val branchInfo = Decoupled(new BranchInfo)
69  })
70
71  val s1 = Module(new BPUStage1)
72  val s2 = Module(new BPUStage2)
73  val s3 = Module(new BPUStage3)
74
75  s1.io.flush := io.flush(0)
76  s2.io.flush := io.flush(1)
77  s3.io.flush := io.flush(2)
78
79  s1.io.in <> io.in
80  s2.io.in <> s1.io.out
81  s3.io.in <> s2.io.out
82
83  io.out(0) <> s1.io.s1_out
84  io.out(1) <> s2.io.s2_out
85  io.out(2) <> s3.io.s3_out
86
87  s1.io.redirect <> io.redirect
88  s1.io.outOfOrderBrInfo <> io.outOfOrderBrInfo
89  s1.io.inOrderBrInfo <> io.inOrderBrInfo
90  s2.io.outOfOrderBrInfo <> io.outOfOrderBrInfo
91  s2.io.inOrderBrInfo <> io.inOrderBrInfo
92
93  s3.io.predecode <> io.predecode
94}
95