power(bpu): optimize CGE of bpu/previous_s2_* (#3670)

Co-authored-by: pengxiao <[email protected]>

power(bpu): optimize CGE of bpu/predictors_io_update (#3579)

Bpu: Optimize CGE of bpu/predictors_io_update by moving update regs into
predictors, except for the update PC

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Co-authore

power(bpu): optimize CGE of bpu/predictors_io_update (#3579)

Bpu: Optimize CGE of bpu/predictors_io_update by moving update regs into
predictors, except for the update PC

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Co-authored-by: pengxiao <[email protected]>

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fix(BPU): fix potential bug on s2_fire_dup (#3850)

Detailed Issue please refer to issue:
https://github.com/OpenXiangShan/XiangShan/issues/3837

Close #3837

feat(ittage): Reuse always_taken to mark the first occurrence of the jalr inst (#3718)

Reuse always_taken to mark the first occurrence of the jalr instruction
and rename always_taken to strong_bias.

style(frontend): manually wrap some line (#3791)

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

fix(BPU): remove reg of reset_vector (#3669)

fix(BPU): adjust s3 target when fallThroughErr signal is high (#3636)

1. adjust S3 target address selection.

fix(BPU): adjust fallThroughErr signal usage strategy (#3627)

bpu: fix s0_pc assert fail before reset done (#3193)

BPU: change `MaxMetaBaseLength` to an even value (#3192)

bpu: use (27, 12, 12) segmented PC in BPU (#3027)

In dhrystone, most high bits of PC is gated.

bpu: gate reset_vector (#2790)

bpu: gate s0 registers when s0_stall (#2791)

bpu: disable ittage when no indirect branch & ittage backward shift (#3092)

Co-authored-by: Easton Man <[email protected]>

FTB: Merge ftb low power & fix fallThroughAddr calculation. (#2997)

ftq: cut area of ftq_redirect_mem (#2856)

dlt folded_hist/afhob/lastBrNumOH
ftq_redirect_mem: 247*64->73*64

ftq: cut ftq area (#2806)

ftb_entry_mem:
full ftb_entry: reg->sram;
origin reg: dlt valid/lower/tarStat/pftAddr/carry/last_may_be_rvi_call/always_taken

ftq_meta_1r_sram:
dlt Tage_SC: sc

ftq: cut ftq area (#2806)

ftb_entry_mem:
full ftb_entry: reg->sram;
origin reg: dlt valid/lower/tarStat/pftAddr/carry/last_may_be_rvi_call/always_taken

ftq_meta_1r_sram:
dlt Tage_SC: scMeta-tageTakens/scUsed/providerResps-unconf/altDiffers/takens;
dlt ITTage: altDiffers/taken
dlt uFTB: pred_way
dlt RAS: sctr/TOSR/NOS

ftq_redirect_sram->ftq_redirect_mem

Co-authored-by: chenguokai <[email protected]>

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BPU: add clock gating (#2733)

Co-authored-by: Liang Sen <[email protected]>

Frontend: fix dirty parameter generation

RVH: fix a bug about sim-verilog

ftq: reduce meta length (#2453)

MaxMetaLength: 256 -> 219

Frontend: delete unnecessary dontTouch in frontend (#2414)

docs: change comments (#2380)

comments does not match with code.

Bump rocket-chip (#2353)