1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import top.Parameters 8import xiangshan.backend._ 9import xiangshan.backend.dispatch.DP1Parameters 10import xiangshan.backend.exu.ExuParameters 11import xiangshan.frontend._ 12import utils._ 13 14case class XSCoreParameters 15( 16 XLEN: Int = 64, 17 HasMExtension: Boolean = true, 18 HasCExtension: Boolean = true, 19 HasDiv: Boolean = true, 20 HasICache: Boolean = true, 21 HasDCache: Boolean = true, 22 EnableStoreQueue: Boolean = true, 23 AddrBits: Int = 64, 24 VAddrBits: Int = 39, 25 PAddrBits: Int = 32, 26 HasFPU: Boolean = true, 27 FectchWidth: Int = 8, 28 EnableBPU: Boolean = true, 29 EnableBPD: Boolean = false, 30 EnableRAS: Boolean = false, 31 EnableLB: Boolean = false, 32 HistoryLength: Int = 64, 33 BtbSize: Int = 2048, 34 JbtacSize: Int = 1024, 35 JbtacBanks: Int = 8, 36 RasSize: Int = 16, 37 CacheLineSize: Int = 512, 38 UBtbWays: Int = 16, 39 BtbWays: Int = 2, 40 IBufSize: Int = 64, 41 DecodeWidth: Int = 6, 42 RenameWidth: Int = 6, 43 CommitWidth: Int = 6, 44 BrqSize: Int = 16, 45 IssQueSize: Int = 8, 46 NRPhyRegs: Int = 128, 47 NRReadPorts: Int = 14, 48 NRWritePorts: Int = 8, 49 RoqSize: Int = 32, 50 IntDqDeqWidth: Int = 4, 51 FpDqDeqWidth: Int = 4, 52 LsDqDeqWidth: Int = 4, 53 dp1Paremeters: DP1Parameters = DP1Parameters( 54 IntDqSize = 16, 55 FpDqSize = 16, 56 LsDqSize = 16 57 ), 58 exuParameters: ExuParameters = ExuParameters( 59 JmpCnt = 1, 60 AluCnt = 4, 61 MulCnt = 1, 62 MduCnt = 1, 63 FmacCnt = 0, 64 FmiscCnt = 0, 65 FmiscDivSqrtCnt = 0, 66 LduCnt = 0, 67 StuCnt = 1 68 ) 69) 70 71 72trait HasXSParameter { 73 74 val core = Parameters.get.coreParameters 75 val env = Parameters.get.envParameters 76 77 val XLEN = core.XLEN 78 val HasMExtension = core.HasMExtension 79 val HasCExtension = core.HasCExtension 80 val HasDiv = core.HasDiv 81 val HasIcache = core.HasICache 82 val HasDcache = core.HasDCache 83 val EnableStoreQueue = core.EnableStoreQueue 84 val AddrBits = core.AddrBits // AddrBits is used in some cases 85 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 86 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 87 val AddrBytes = AddrBits / 8 // unused 88 val DataBits = XLEN 89 val DataBytes = DataBits / 8 90 val HasFPU = core.HasFPU 91 val FetchWidth = core.FectchWidth 92 val PredictWidth = FetchWidth * 2 93 val EnableBPU = core.EnableBPU 94 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 95 val EnableRAS = core.EnableRAS 96 val EnableLB = core.EnableLB 97 val HistoryLength = core.HistoryLength 98 val BtbSize = core.BtbSize 99 val BtbBanks = PredictWidth 100 val JbtacSize = core.JbtacSize 101 val JbtacBanks = core.JbtacBanks 102 val RasSize = core.RasSize 103 val IBufSize = core.IBufSize 104 val DecodeWidth = core.DecodeWidth 105 val RenameWidth = core.RenameWidth 106 val CommitWidth = core.CommitWidth 107 val BrqSize = core.BrqSize 108 val IssQueSize = core.IssQueSize 109 val BrTagWidth = log2Up(BrqSize) 110 val NRPhyRegs = core.NRPhyRegs 111 val PhyRegIdxWidth = log2Up(NRPhyRegs) 112 val NRReadPorts = core.NRReadPorts 113 val NRWritePorts = core.NRWritePorts 114 val RoqSize = core.RoqSize 115 val InnerRoqIdxWidth = log2Up(RoqSize) 116 val RoqIdxWidth = InnerRoqIdxWidth + 1 117 val IntDqDeqWidth = core.IntDqDeqWidth 118 val FpDqDeqWidth = core.FpDqDeqWidth 119 val LsDqDeqWidth = core.LsDqDeqWidth 120 val dp1Paremeters = core.dp1Paremeters 121 val exuParameters = core.exuParameters 122 val CacheLineSize = core.CacheLineSize 123 val CacheLineHalfWord = CacheLineSize / 16 124 val ExtHistoryLength = HistoryLength * 2 125 val UBtbWays = core.UBtbWays 126 val BtbWays = core.BtbWays 127} 128 129trait HasXSLog { this: Module => 130 implicit val moduleName: String = this.name 131} 132 133abstract class XSModule extends Module 134 with HasXSParameter 135 with HasExceptionNO 136 with HasXSLog 137 138//remove this trait after impl module logic 139trait NeedImpl { this: Module => 140 override protected def IO[T <: Data](iodef: T): T = { 141 val io = chisel3.experimental.IO(iodef) 142 io <> DontCare 143 io 144 } 145} 146 147abstract class XSBundle extends Bundle 148 with HasXSParameter 149 150case class EnviromentParameters 151( 152 FPGAPlatform: Boolean = true, 153 EnableDebug: Boolean = false 154) 155 156object AddressSpace extends HasXSParameter { 157 // (start, size) 158 // address out of MMIO will be considered as DRAM 159 def mmio = List( 160 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 161 (0x40000000L, 0x40000000L) // external devices 162 ) 163 164 def isMMIO(addr: UInt): Bool = mmio.map(range => { 165 require(isPow2(range._2)) 166 val bits = log2Up(range._2) 167 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 168 }).reduce(_ || _) 169} 170 171 172class XSCore extends XSModule { 173 val io = IO(new Bundle { 174 val imem = new SimpleBusC 175 val dmem = new SimpleBusC 176 val mmio = new SimpleBusUC 177 val frontend = Flipped(new SimpleBusUC()) 178 }) 179 180 io.imem <> DontCare 181 182 val dmemXbar = Module(new SimpleBusCrossbarNto1(3)) 183 184 val front = Module(new Frontend) 185 val backend = Module(new Backend) 186 187 front.io.backend <> backend.io.frontend 188 189 backend.io.memMMU.imem <> DontCare 190 191 val dtlb = TLB( 192 in = backend.io.dmem, 193 mem = dmemXbar.io.in(1), 194 flush = false.B, 195 csrMMU = backend.io.memMMU.dmem 196 )(TLBConfig(name = "dtlb", totalEntry = 64)) 197 dmemXbar.io.in(0) <> dtlb.io.out 198 dmemXbar.io.in(2) <> io.frontend 199 200 io.dmem <> Cache( 201 in = dmemXbar.io.out, 202 mmio = Seq(io.mmio), 203 flush = "b00".U, 204 empty = dtlb.io.cacheEmpty, 205 enable = HasDcache 206 )(CacheConfig(name = "dcache")) 207 208 XSDebug("(req valid, ready | resp valid, ready) \n") 209 XSDebug("c-mem(%x %x %x| %x %x) c-coh(%x %x %x| %x %x) cache (%x %x %x| %x %x) tlb (%x %x %x| %x %x)\n", 210 io.dmem.mem.req.valid, 211 io.dmem.mem.req.ready, 212 io.dmem.mem.req.bits.addr, 213 io.dmem.mem.resp.valid, 214 io.dmem.mem.resp.ready, 215 io.dmem.coh.req.valid, 216 io.dmem.coh.req.ready, 217 io.dmem.coh.req.bits.addr, 218 io.dmem.coh.resp.valid, 219 io.dmem.coh.resp.ready, 220 dmemXbar.io.out.req.valid, 221 dmemXbar.io.out.req.ready, 222 dmemXbar.io.out.req.bits.addr, 223 dmemXbar.io.out.resp.valid, 224 dmemXbar.io.out.resp.ready, 225 backend.io.dmem.req.valid, 226 backend.io.dmem.req.ready, 227 backend.io.dmem.req.bits.addr, 228 backend.io.dmem.resp.valid, 229 backend.io.dmem.resp.ready 230 ) 231} 232