1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import top.Parameters 8import xiangshan.backend._ 9import xiangshan.backend.dispatch.DispatchParameters 10import xiangshan.backend.exu.ExuParameters 11import xiangshan.frontend._ 12import xiangshan.mem._ 13import xiangshan.cache.{DCacheParameters, ICacheParameters} 14import bus.tilelink.{TLArbiter, TLCached, TLMasterUtilities, TLParameters} 15import utils._ 16 17case class XSCoreParameters 18( 19 XLEN: Int = 64, 20 HasMExtension: Boolean = true, 21 HasCExtension: Boolean = true, 22 HasDiv: Boolean = true, 23 HasICache: Boolean = true, 24 HasDCache: Boolean = true, 25 EnableStoreQueue: Boolean = true, 26 AddrBits: Int = 64, 27 VAddrBits: Int = 39, 28 PAddrBits: Int = 40, 29 HasFPU: Boolean = true, 30 FectchWidth: Int = 8, 31 EnableBPU: Boolean = true, 32 EnableBPD: Boolean = true, 33 EnableRAS: Boolean = false, 34 EnableLB: Boolean = false, 35 HistoryLength: Int = 64, 36 BtbSize: Int = 256, 37 JbtacSize: Int = 1024, 38 JbtacBanks: Int = 8, 39 RasSize: Int = 16, 40 CacheLineSize: Int = 512, 41 UBtbWays: Int = 16, 42 BtbWays: Int = 2, 43 IBufSize: Int = 64, 44 DecodeWidth: Int = 6, 45 RenameWidth: Int = 6, 46 CommitWidth: Int = 6, 47 BrqSize: Int = 16, 48 IssQueSize: Int = 8, 49 NRPhyRegs: Int = 128, 50 NRIntReadPorts: Int = 8, 51 NRIntWritePorts: Int = 8, 52 NRFpReadPorts: Int = 14, 53 NRFpWritePorts: Int = 8, 54 LsroqSize: Int = 16, 55 RoqSize: Int = 32, 56 dpParams: DispatchParameters = DispatchParameters( 57 DqEnqWidth = 4, 58 IntDqSize = 64, 59 FpDqSize = 64, 60 LsDqSize = 64, 61 IntDqDeqWidth = 4, 62 FpDqDeqWidth = 4, 63 LsDqDeqWidth = 4, 64 IntDqReplayWidth = 4, 65 FpDqReplayWidth = 4, 66 LsDqReplayWidth = 4 67 ), 68 exuParameters: ExuParameters = ExuParameters( 69 JmpCnt = 1, 70 AluCnt = 4, 71 MulCnt = 0, 72 MduCnt = 2, 73 FmacCnt = 0, 74 FmiscCnt = 0, 75 FmiscDivSqrtCnt = 0, 76 LduCnt = 2, 77 StuCnt = 2 78 ), 79 LoadPipelineWidth: Int = 2, 80 StorePipelineWidth: Int = 2, 81 StoreBufferSize: Int = 16, 82 RefillSize: Int = 512, 83 TlbEntrySize: Int = 32, 84 TlbL2EntrySize: Int = 256, // or 512 85 PtwL1EntrySize: Int = 16, 86 PtwL2EntrySize: Int = 256 87) 88 89trait HasXSParameter { 90 91 val core = Parameters.get.coreParameters 92 val env = Parameters.get.envParameters 93 94 val XLEN = core.XLEN 95 val HasMExtension = core.HasMExtension 96 val HasCExtension = core.HasCExtension 97 val HasDiv = core.HasDiv 98 val HasIcache = core.HasICache 99 val HasDcache = core.HasDCache 100 val EnableStoreQueue = core.EnableStoreQueue 101 val AddrBits = core.AddrBits // AddrBits is used in some cases 102 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 103 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 104 val AddrBytes = AddrBits / 8 // unused 105 val DataBits = XLEN 106 val DataBytes = DataBits / 8 107 val HasFPU = core.HasFPU 108 val FetchWidth = core.FectchWidth 109 val PredictWidth = FetchWidth * 2 110 val EnableBPU = core.EnableBPU 111 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 112 val EnableRAS = core.EnableRAS 113 val EnableLB = core.EnableLB 114 val HistoryLength = core.HistoryLength 115 val BtbSize = core.BtbSize 116 // val BtbWays = 4 117 val BtbBanks = PredictWidth 118 // val BtbSets = BtbSize / BtbWays 119 val JbtacSize = core.JbtacSize 120 val JbtacBanks = core.JbtacBanks 121 val RasSize = core.RasSize 122 val CacheLineSize = core.CacheLineSize 123 val CacheLineHalfWord = CacheLineSize / 16 124 val ExtHistoryLength = HistoryLength * 2 125 val UBtbWays = core.UBtbWays 126 val BtbWays = core.BtbWays 127 val IBufSize = core.IBufSize 128 val DecodeWidth = core.DecodeWidth 129 val RenameWidth = core.RenameWidth 130 val CommitWidth = core.CommitWidth 131 val BrqSize = core.BrqSize 132 val IssQueSize = core.IssQueSize 133 val BrTagWidth = log2Up(BrqSize) 134 val NRPhyRegs = core.NRPhyRegs 135 val PhyRegIdxWidth = log2Up(NRPhyRegs) 136 val LsroqSize = core.LsroqSize // 64 137 val RoqSize = core.RoqSize 138 val InnerRoqIdxWidth = log2Up(RoqSize) 139 val RoqIdxWidth = InnerRoqIdxWidth + 1 140 val InnerLsroqIdxWidth = log2Up(LsroqSize) 141 val LsroqIdxWidth = InnerLsroqIdxWidth + 1 142 val dpParams = core.dpParams 143 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 144 val exuParameters = core.exuParameters 145 val NRIntReadPorts = core.NRIntReadPorts 146 val NRIntWritePorts = core.NRIntWritePorts 147 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 148 val NRFpReadPorts = core.NRFpReadPorts 149 val NRFpWritePorts = core.NRFpWritePorts 150 val LoadPipelineWidth = core.LoadPipelineWidth 151 val StorePipelineWidth = core.StorePipelineWidth 152 val StoreBufferSize = core.StoreBufferSize 153 val RefillSize = core.RefillSize 154 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 155 val TlbEntrySize = core.TlbEntrySize 156 val TlbL2EntrySize = core.TlbL2EntrySize 157 val PtwL1EntrySize = core.PtwL1EntrySize 158 val PtwL2EntrySize = core.PtwL2EntrySize 159 160 val l1BusDataWidth = 64 161 val l1BusParams = TLParameters( 162 addressBits = PAddrBits, 163 dataBits = l1BusDataWidth, 164 sourceBits = 3, 165 sinkBits = 3 166 ) 167 168 val icacheParameters = ICacheParameters( 169 ) 170 171 val LRSCCycles = 16 172 val dcacheParameters = DCacheParameters( 173 tagECC = Some("secded"), 174 dataECC = Some("secded"), 175 busParams = l1BusParams 176 ) 177} 178 179trait HasXSLog { this: Module => 180 implicit val moduleName: String = this.name 181} 182 183abstract class XSModule extends Module 184 with HasXSParameter 185 with HasExceptionNO 186 with HasXSLog 187 188//remove this trait after impl module logic 189trait NeedImpl { this: Module => 190 override protected def IO[T <: Data](iodef: T): T = { 191 val io = chisel3.experimental.IO(iodef) 192 io <> DontCare 193 io 194 } 195} 196 197abstract class XSBundle extends Bundle 198 with HasXSParameter 199 200case class EnviromentParameters 201( 202 FPGAPlatform: Boolean = true, 203 EnableDebug: Boolean = false 204) 205 206object AddressSpace extends HasXSParameter { 207 // (start, size) 208 // address out of MMIO will be considered as DRAM 209 def mmio = List( 210 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 211 (0x40000000L, 0x40000000L) // external devices 212 ) 213 214 def isMMIO(addr: UInt): Bool = mmio.map(range => { 215 require(isPow2(range._2)) 216 val bits = log2Up(range._2) 217 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 218 }).reduce(_ || _) 219} 220 221 222class TLReqProducer extends XSModule { 223 val io = IO(new TLCached(l1BusParams)) 224 225 io <> DontCare 226 227 val addr = RegInit("h80000000".U) 228 addr := addr + 4.U 229 val (legal, bundle) = TLMasterUtilities.Get(io.params, 0.U, addr, 3.U) 230 io.a.bits := bundle 231 io.a.valid := true.B 232 assert(legal) 233 io.d.ready := true.B 234 when(io.a.fire()){ 235 io.a.bits.dump() 236 } 237 when(io.d.fire()){ 238 io.d.bits.dump() 239 } 240} 241 242class XSCore extends XSModule { 243 val io = IO(new Bundle { 244 val mem = new TLCached(l1BusParams) 245 val mmio = new TLCached(l1BusParams) 246 }) 247 248 // val fakecache = Module(new TLReqProducer) 249 // io.mem <> fakecache.io 250 251 io.mmio <> DontCare 252 253 val front = Module(new Frontend) 254 val backend = Module(new Backend) 255 val mem = Module(new Memend) 256 257 front.io.backend <> backend.io.frontend 258 mem.io.backend <> backend.io.mem 259 mem.io.mem <> io.mem 260 mem.io.mmio <> io.mmio 261} 262