Merge remote-tracking branch 'origin/gen-sram-conf' into decoupled-frontend

parameters: ras size 32, btb size 4096

Merge pull request #923 from OpenXiangShan/vaddr-fwd

mem: use vaddr based store to load forward for better timing

frontend: add ittage indirect predictor

l0tlb: add a new level tlb, a load tlb and a store tlb (#961)

* Revert "Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945)"

This reverts commit b052b97230d6fdeedaf4e4905092ade

l0tlb: add a new level tlb, a load tlb and a store tlb (#961)

* Revert "Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945)"

This reverts commit b052b97230d6fdeedaf4e4905092adef6e768b4f.

* fu: remove unused import

* mmu.tlb: 2 load/store pipeline has 1 dtlb

* mmu: remove btlb, the l1-tlb

* mmu: set split-tlb to 32 to check perf effect

* mmu: wrap tlb's param with TLBParameters

* mmu: add params 'useBTlb'

dtlb size is small: normal 8, super 2

* mmu.tlb: add Bundle TlbEntry, simplify tlb hit logic(coding)

* mmu.tlb: seperate tlb's storage, relative hit/sfence logic

tlb now supports full-associate, set-associate, directive-associate.
more: change tlb's parameter usage, change util.Random to support
case that mod is 1.

* mmu.tlb: support normalAsVictim, super(fa) -> normal(sa/da)

be carefull to use tlb's parameter, only a part of param combination
is supported

* mmu.tlb: fix bug of hit method and victim write

* mmu.tlb: add tlb storage's perf counter

* mmu.tlb: rewrite replace part, support set or non-set

* mmu.tlb: add param outReplace to receive out replace index

* mmu.tlb: change param superSize to superNWays

add param superNSets, which should always be 1

* mmu.tlb: change some perf counter's name and change some params

* mmu.tlb: fix bug of replace io bundle

* mmu.tlb: remove unused signal wayIdx in tlbstorageio

* mmu.tlb: separate tlb_ld/st into two 'same' tlb

* mmu.tlb: when nWays is 1, replace returns 0.U

before, replace will return 1.U, no influence for refill but bad
for perf counter

* mmu.tlb: give tlb_ld and tlb_st a name (in waveform)

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Merge branch 'master' into vaddr-fwd

Merge pull request #949 from OpenXiangShan/me-opt

backend, rename: configurable free list & `headPtr` bug fix & `dst=0/dst=src` move inst elimination

Merge remote-tracking branch 'origin/master' into vaddr-fwd

update base table update logic, update pred table and alt_pred table update logic

Merge branch 'master' into dcp-merge-master

Merge branch 'master' into me-opt

l2tlb: mem access now takes 512 bits, 8 ptes (#973)

* mmu: wrap l2tlb's param withL2TLBParameters

* mmu.l2tlb: add param blockBytes: 64, 8 ptes

* mmu.l2tlb: set l2tlb cache size to l2:256, l3:

l2tlb: mem access now takes 512 bits, 8 ptes (#973)

* mmu: wrap l2tlb's param withL2TLBParameters

* mmu.l2tlb: add param blockBytes: 64, 8 ptes

* mmu.l2tlb: set l2tlb cache size to l2:256, l3:4096

* mmu.l2tlb: add config print

* mmu.l2tlb: fix bug of resp data indices choosen and opt coding style

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Merge branch 'rename-flush-bug-fix' into me-opt

bpu: prevent always taken branches from utilizing conditional branch predictor

Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945)

This reverts commit 5aae5b8dd522c46434b81201cec5dcbf1bd28e4d.

rename: [refactor] move free list into 'freelist' package
"trait" was used to improve code style
parameters: use EnableIntMoveElim to control code generation
[WIP] EnableIntMoveElim=false has

rename: [refactor] move free list into 'freelist' package
"trait" was used to improve code style
parameters: use EnableIntMoveElim to control code generation
[WIP] EnableIntMoveElim=false hasn't been tested

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AlternativeFreeList: parameterize length of FL
FreeList: same as above
Parameters: add 2 core param and 2 derived param
[TODO] use EnableIntMoveElim to control ME function

l0tlb: add a new level tlb to each mem pipeline (#936)

* Miniconfig: change dtlb size to 32 at minimal config

* mmu.dtlb: change tlb's replacement access code style

dtlb now can support plru (

l0tlb: add a new level tlb to each mem pipeline (#936)

* Miniconfig: change dtlb size to 32 at minimal config

* mmu.dtlb: change tlb's replacement access code style

dtlb now can support plru (functionaly).
plru with multi-access is chained, so there will be long latency
for dtlb to use plru.

* mmu.tlb: add tlb at new level named btlb

bridge tlb:
one l0-tlb in each mem pipeline
all the l0-tlb connect to bridge tlb
btlb connects to l2tlb, so btlb is also l1-tlb
itlb remains the same

* mmu.tlb: set tlb size: l0-8, l1-64

* mmu.btlb: add sfence logic

* mmu.tlb: fix bug of sfence logic of g bit

* mmu.btlb: add some perf counter

* mmu.btlb: fix bug of random replace

* mmu.filter: add port vector to record which ports the reqs come from

* mmu.btlb: add some perf counter && add refill mask

* mmu.filter: add check for flushed req

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backend: separate store address and data (#921)

This commit separates store address and store data in backend, including both reservation stations and function units. This commit also changes how st

backend: separate store address and data (#921)

This commit separates store address and store data in backend, including both reservation stations and function units. This commit also changes how stIssuePtr is updated. stIssuePtr should only be updated when both store data and address issue.

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mmu.l2tlb: cut down l2tlb.l2 size to 256 and set l2tlb.l3 way to 8, keep l3's size (#927)

* Miniconfig: change dtlb size to 32 at minimal config

* mmu.dtlb: change tlb's replacement access code s

mmu.l2tlb: cut down l2tlb.l2 size to 256 and set l2tlb.l3 way to 8, keep l3's size (#927)

* Miniconfig: change dtlb size to 32 at minimal config

* mmu.dtlb: change tlb's replacement access code style

dtlb now can support plru (functionaly).
plru with multi-access is chained, so there will be long latency
for dtlb to use plru.

* mmu.l2tlb: cut down l2tlb.l2 to 256 and set l3.way to 8

* mmu.l2tlb: cut down l2tlb.l3 to 2048 from 4096

* Revert "mmu.l2tlb: cut down l2tlb.l3 to 2048 from 4096"

This reverts commit efbb077ef4be1d4e585a49537ba9be3144423b52.

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mem: loadpipe will not miss if fullForward succeed

New option `EnableFastForward` is added to config list.
EnableFastForward will reduce L1D$ miss but make timing worse.

* `forwardMaskFast` is gene

mem: loadpipe will not miss if fullForward succeed

New option `EnableFastForward` is added to config list.
EnableFastForward will reduce L1D$ miss but make timing worse.

* `forwardMaskFast` is generated at load_s1, it is used to generate
fastUop for fast wakeup
* `forwardMask` is generated at load_s2, it will be used to check if
forward result is correct

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core: add basic debug mode features (#918)

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support

core: add basic debug mode features (#918)

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support
* Use difftest with JTAG support

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BPU: Use separate sc table for each branch instruction

Merge branch 'master' into merge-master

bpu: let stage1 use result of bim
tage: fix phist support