1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.dispatch.DispatchParameters 26import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, Tage_SC} 30import freechips.rocketchip.diplomacy.AddressSet 31 32case object XSCoreParamsKey extends Field[XSCoreParameters] 33 34case class XSCoreParameters 35( 36 HasPrefetch: Boolean = false, 37 HartId: Int = 0, 38 XLEN: Int = 64, 39 HasMExtension: Boolean = true, 40 HasCExtension: Boolean = true, 41 HasDiv: Boolean = true, 42 HasICache: Boolean = true, 43 HasDCache: Boolean = true, 44 AddrBits: Int = 64, 45 VAddrBits: Int = 39, 46 PAddrBits: Int = 40, 47 HasFPU: Boolean = true, 48 FetchWidth: Int = 8, 49 EnableBPU: Boolean = true, 50 EnableBPD: Boolean = true, 51 EnableRAS: Boolean = true, 52 EnableLB: Boolean = false, 53 EnableLoop: Boolean = true, 54 EnableSC: Boolean = true, 55 EnbaleTlbDebug: Boolean = false, 56 EnableJal: Boolean = false, 57 EnableUBTB: Boolean = true, 58 HistoryLength: Int = 64, 59 PathHistoryLength: Int = 16, 60 BtbSize: Int = 2048, 61 JbtacSize: Int = 1024, 62 JbtacBanks: Int = 8, 63 RasSize: Int = 16, 64 CacheLineSize: Int = 512, 65 UBtbWays: Int = 16, 66 BtbWays: Int = 2, 67 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 68 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 69 // val loop = Module(new LoopPredictor) 70 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 71 // else Module(new Tage) } 72 // else { Module(new FakeTage) }) 73 val ftb = Module(new FTB()(p)) 74 val ubtb = Module(new MicroBTB()(p)) 75 val bim = Module(new BIM()(p)) 76 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 77 val ras = Module(new RAS()(p)) 78 // val tage = Module(new Tage()(p)) 79 // val fake = Module(new FakePredictor()(p)) 80 81 // val preds = Seq(loop, tage, btb, ubtb, bim) 82 val preds = Seq(bim, ubtb, tage, ftb, ras) 83 preds.map(_.io := DontCare) 84 85 // ubtb.io.resp_in(0) := resp_in 86 // bim.io.resp_in(0) := ubtb.io.resp 87 // btb.io.resp_in(0) := bim.io.resp 88 // tage.io.resp_in(0) := btb.io.resp 89 // loop.io.resp_in(0) := tage.io.resp 90 bim.io.in.bits.resp_in(0) := resp_in 91 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 92 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 93 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 94 ras.io.in.bits.resp_in(0) := ftb.io.out.resp 95 96 (preds, ras.io.out.resp) 97 }), 98 99 100 EnableL1plusPrefetcher: Boolean = true, 101 IBufSize: Int = 48, 102 DecodeWidth: Int = 6, 103 RenameWidth: Int = 6, 104 CommitWidth: Int = 6, 105 BrqSize: Int = 32, 106 FtqSize: Int = 64, 107 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 108 IssQueSize: Int = 16, 109 NRPhyRegs: Int = 160, 110 NRIntReadPorts: Int = 14, 111 NRIntWritePorts: Int = 8, 112 NRFpReadPorts: Int = 14, 113 NRFpWritePorts: Int = 8, 114 LoadQueueSize: Int = 64, 115 StoreQueueSize: Int = 48, 116 RoqSize: Int = 192, 117 EnableIntMoveElim: Boolean = true, 118 IntRefCounterWidth: Int = 2, 119 dpParams: DispatchParameters = DispatchParameters( 120 IntDqSize = 16, 121 FpDqSize = 16, 122 LsDqSize = 16, 123 IntDqDeqWidth = 4, 124 FpDqDeqWidth = 4, 125 LsDqDeqWidth = 4 126 ), 127 exuParameters: ExuParameters = ExuParameters( 128 JmpCnt = 1, 129 AluCnt = 4, 130 MulCnt = 0, 131 MduCnt = 2, 132 FmacCnt = 4, 133 FmiscCnt = 2, 134 FmiscDivSqrtCnt = 0, 135 LduCnt = 2, 136 StuCnt = 2 137 ), 138 LoadPipelineWidth: Int = 2, 139 StorePipelineWidth: Int = 2, 140 StoreBufferSize: Int = 16, 141 StoreBufferThreshold: Int = 7, 142 RefillSize: Int = 512, 143 itlbParameters: TLBParameters = TLBParameters( 144 name = "itlb", 145 fetchi = true, 146 useDmode = false, 147 sameCycle = true, 148 normalReplacer = Some("plru"), 149 superReplacer = Some("plru"), 150 shouldBlock = true 151 ), 152 ldtlbParameters: TLBParameters = TLBParameters( 153 name = "ldtlb", 154 normalNSets = 128, 155 normalNWays = 1, 156 normalAssociative = "sa", 157 normalReplacer = Some("setplru"), 158 superNWays = 8, 159 normalAsVictim = true, 160 outReplace = true 161 ), 162 sttlbParameters: TLBParameters = TLBParameters( 163 name = "sttlb", 164 normalNSets = 128, 165 normalNWays = 1, 166 normalAssociative = "sa", 167 normalReplacer = Some("setplru"), 168 superNWays = 8, 169 normalAsVictim = true, 170 outReplace = true 171 ), 172 btlbParameters: TLBParameters = TLBParameters( 173 name = "btlb", 174 normalNSets = 1, 175 normalNWays = 64, 176 superNWays = 4, 177 ), 178 useBTlb: Boolean = false, 179 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 180 NumPerfCounters: Int = 16, 181 icacheParameters: ICacheParameters = ICacheParameters( 182 tagECC = Some("parity"), 183 dataECC = Some("parity"), 184 replacer = Some("setplru"), 185 nMissEntries = 2 186 ), 187 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 188 tagECC = Some("secded"), 189 dataECC = Some("secded"), 190 replacer = Some("setplru"), 191 nMissEntries = 8 192 ), 193 dcacheParameters: DCacheParameters = DCacheParameters( 194 tagECC = Some("secded"), 195 dataECC = Some("secded"), 196 replacer = Some("setplru"), 197 nMissEntries = 16, 198 nProbeEntries = 16, 199 nReleaseEntries = 16, 200 nStoreReplayEntries = 16 201 ), 202 L2Size: Int = 512 * 1024, // 512KB 203 L2NWays: Int = 8, 204 useFakePTW: Boolean = false, 205 useFakeDCache: Boolean = false, 206 useFakeL1plusCache: Boolean = false, 207 useFakeL2Cache: Boolean = false 208){ 209 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 210 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 211 212 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 213 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 214 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 215 216 val fpExuConfigs = 217 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 218 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 219 220 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 221} 222 223case object DebugOptionsKey extends Field[DebugOptions] 224 225case class DebugOptions 226( 227 FPGAPlatform: Boolean = true, 228 EnableDebug: Boolean = true, 229 EnablePerfDebug: Boolean = true, 230 UseDRAMSim: Boolean = false 231) 232 233trait HasXSParameter { 234 235 implicit val p: Parameters 236 237 val coreParams = p(XSCoreParamsKey) 238 val env = p(DebugOptionsKey) 239 240 val XLEN = coreParams.XLEN 241 val hardId = coreParams.HartId 242 val minFLen = 32 243 val fLen = 64 244 def xLen = XLEN 245 246 val HasMExtension = coreParams.HasMExtension 247 val HasCExtension = coreParams.HasCExtension 248 val HasDiv = coreParams.HasDiv 249 val HasIcache = coreParams.HasICache 250 val HasDcache = coreParams.HasDCache 251 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 252 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 253 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 254 val AddrBytes = AddrBits / 8 // unused 255 val DataBits = XLEN 256 val DataBytes = DataBits / 8 257 val HasFPU = coreParams.HasFPU 258 val FetchWidth = coreParams.FetchWidth 259 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 260 val EnableBPU = coreParams.EnableBPU 261 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 262 val EnableRAS = coreParams.EnableRAS 263 val EnableLB = coreParams.EnableLB 264 val EnableLoop = coreParams.EnableLoop 265 val EnableSC = coreParams.EnableSC 266 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 267 val HistoryLength = coreParams.HistoryLength 268 val PathHistoryLength = coreParams.PathHistoryLength 269 val BtbSize = coreParams.BtbSize 270 // val BtbWays = 4 271 val BtbBanks = PredictWidth 272 // val BtbSets = BtbSize / BtbWays 273 val JbtacSize = coreParams.JbtacSize 274 val JbtacBanks = coreParams.JbtacBanks 275 val RasSize = coreParams.RasSize 276 277 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 278 coreParams.branchPredictor(resp_in, p, enableSC) 279 } 280 281 val CacheLineSize = coreParams.CacheLineSize 282 val CacheLineHalfWord = CacheLineSize / 16 283 val ExtHistoryLength = HistoryLength + 64 284 val UBtbWays = coreParams.UBtbWays 285 val BtbWays = coreParams.BtbWays 286 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 287 val IBufSize = coreParams.IBufSize 288 val DecodeWidth = coreParams.DecodeWidth 289 val RenameWidth = coreParams.RenameWidth 290 val CommitWidth = coreParams.CommitWidth 291 val BrqSize = coreParams.BrqSize 292 val FtqSize = coreParams.FtqSize 293 val IssQueSize = coreParams.IssQueSize 294 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 295 val BrTagWidth = log2Up(BrqSize) 296 val NRPhyRegs = coreParams.NRPhyRegs 297 val PhyRegIdxWidth = log2Up(NRPhyRegs) 298 val RoqSize = coreParams.RoqSize 299 val EnableIntMoveElim = coreParams.EnableIntMoveElim 300 val IntRefCounterWidth = coreParams.IntRefCounterWidth 301 val StdFreeListSize = NRPhyRegs - 32 302 val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 } 303 val LoadQueueSize = coreParams.LoadQueueSize 304 val StoreQueueSize = coreParams.StoreQueueSize 305 val dpParams = coreParams.dpParams 306 val exuParameters = coreParams.exuParameters 307 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 308 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 309 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 310 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 311 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 312 val LoadPipelineWidth = coreParams.LoadPipelineWidth 313 val StorePipelineWidth = coreParams.StorePipelineWidth 314 val StoreBufferSize = coreParams.StoreBufferSize 315 val StoreBufferThreshold = coreParams.StoreBufferThreshold 316 val RefillSize = coreParams.RefillSize 317 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 318 val useBTlb = coreParams.useBTlb 319 val itlbParams = coreParams.itlbParameters 320 val ldtlbParams = coreParams.ldtlbParameters 321 val sttlbParams = coreParams.sttlbParameters 322 val btlbParams = coreParams.btlbParameters 323 val l2tlbParams = coreParams.l2tlbParameters 324 val NumPerfCounters = coreParams.NumPerfCounters 325 326 val instBytes = if (HasCExtension) 2 else 4 327 val instOffsetBits = log2Ceil(instBytes) 328 329 val icacheParameters = coreParams.icacheParameters 330 val l1plusCacheParameters = coreParams.l1plusCacheParameters 331 val dcacheParameters = coreParams.dcacheParameters 332 333 val LRSCCycles = 100 334 335 336 // cache hierarchy configurations 337 val l1BusDataWidth = 256 338 339 val useFakeDCache = coreParams.useFakeDCache 340 val useFakePTW = coreParams.useFakePTW 341 val useFakeL1plusCache = coreParams.useFakeL1plusCache 342 // L2 configurations 343 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 344 val L1BusWidth = 256 345 val L2Size = coreParams.L2Size 346 val L2BlockSize = 64 347 val L2NWays = coreParams.L2NWays 348 val L2NSets = L2Size / L2BlockSize / L2NWays 349 350 // L3 configurations 351 val L2BusWidth = 256 352 353 // icache prefetcher 354 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 355 enable = true, 356 _type = "stream", 357 streamParams = StreamPrefetchParameters( 358 streamCnt = 2, 359 streamSize = 4, 360 ageWidth = 4, 361 blockBytes = l1plusCacheParameters.blockBytes, 362 reallocStreamOnMissInstantly = true, 363 cacheName = "icache" 364 ) 365 ) 366 367 // dcache prefetcher 368 val l2PrefetcherParameters = L2PrefetcherParameters( 369 enable = true, 370 _type = "bop", // "stream" or "bop" 371 streamParams = StreamPrefetchParameters( 372 streamCnt = 4, 373 streamSize = 4, 374 ageWidth = 4, 375 blockBytes = L2BlockSize, 376 reallocStreamOnMissInstantly = true, 377 cacheName = "dcache" 378 ), 379 bopParams = BOPParameters( 380 rrTableEntries = 256, 381 rrTagBits = 12, 382 scoreBits = 5, 383 roundMax = 50, 384 badScore = 1, 385 blockBytes = L2BlockSize, 386 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 387 ), 388 ) 389 390 // load violation predict 391 val ResetTimeMax2Pow = 20 //1078576 392 val ResetTimeMin2Pow = 10 //1024 393 // wait table parameters 394 val WaitTableSize = 1024 395 val MemPredPCWidth = log2Up(WaitTableSize) 396 val LWTUse2BitCounter = true 397 // store set parameters 398 val SSITSize = WaitTableSize 399 val LFSTSize = 32 400 val SSIDWidth = log2Up(LFSTSize) 401 val LFSTWidth = 4 402 val StoreSetEnable = true // LWT will be disabled if SS is enabled 403 404 val loadExuConfigs = coreParams.loadExuConfigs 405 val storeExuConfigs = coreParams.storeExuConfigs 406 407 val intExuConfigs = coreParams.intExuConfigs 408 409 val fpExuConfigs = coreParams.fpExuConfigs 410 411 val exuConfigs = coreParams.exuConfigs 412 413} 414