1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.dispatch.DispatchParameters 26import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 28import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, Tage_SC} 29 30case object XSCoreParamsKey extends Field[XSCoreParameters] 31 32case class XSCoreParameters 33( 34 HasPrefetch: Boolean = false, 35 HartId: Int = 0, 36 XLEN: Int = 64, 37 HasMExtension: Boolean = true, 38 HasCExtension: Boolean = true, 39 HasDiv: Boolean = true, 40 HasICache: Boolean = true, 41 HasDCache: Boolean = true, 42 AddrBits: Int = 64, 43 VAddrBits: Int = 39, 44 PAddrBits: Int = 40, 45 HasFPU: Boolean = true, 46 FetchWidth: Int = 8, 47 EnableBPU: Boolean = true, 48 EnableBPD: Boolean = true, 49 EnableRAS: Boolean = true, 50 EnableLB: Boolean = false, 51 EnableLoop: Boolean = true, 52 EnableSC: Boolean = true, 53 EnbaleTlbDebug: Boolean = false, 54 EnableJal: Boolean = false, 55 EnableUBTB: Boolean = true, 56 HistoryLength: Int = 64, 57 PathHistoryLength: Int = 16, 58 BtbSize: Int = 2048, 59 JbtacSize: Int = 1024, 60 JbtacBanks: Int = 8, 61 RasSize: Int = 16, 62 CacheLineSize: Int = 512, 63 UBtbWays: Int = 16, 64 BtbWays: Int = 2, 65 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 66 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 67 // val loop = Module(new LoopPredictor) 68 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 69 // else Module(new Tage) } 70 // else { Module(new FakeTage) }) 71 val ftb = Module(new FTB()(p)) 72 val ubtb = Module(new MicroBTB()(p)) 73 val bim = Module(new BIM()(p)) 74 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 75 val ras = Module(new RAS()(p)) 76 // val tage = Module(new Tage()(p)) 77 // val fake = Module(new FakePredictor()(p)) 78 79 // val preds = Seq(loop, tage, btb, ubtb, bim) 80 val preds = Seq(bim, ubtb, tage, ftb, ras) 81 preds.map(_.io := DontCare) 82 83 // ubtb.io.resp_in(0) := resp_in 84 // bim.io.resp_in(0) := ubtb.io.resp 85 // btb.io.resp_in(0) := bim.io.resp 86 // tage.io.resp_in(0) := btb.io.resp 87 // loop.io.resp_in(0) := tage.io.resp 88 bim.io.in.bits.resp_in(0) := resp_in 89 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 90 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 91 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 92 ras.io.in.bits.resp_in(0) := ftb.io.out.resp 93 94 (preds, ras.io.out.resp) 95 }), 96 97 98 EnableL1plusPrefetcher: Boolean = true, 99 IBufSize: Int = 48, 100 DecodeWidth: Int = 6, 101 RenameWidth: Int = 6, 102 CommitWidth: Int = 6, 103 BrqSize: Int = 32, 104 FtqSize: Int = 64, 105 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 106 IssQueSize: Int = 16, 107 NRPhyRegs: Int = 160, 108 NRIntReadPorts: Int = 14, 109 NRIntWritePorts: Int = 8, 110 NRFpReadPorts: Int = 14, 111 NRFpWritePorts: Int = 8, 112 LoadQueueSize: Int = 64, 113 StoreQueueSize: Int = 48, 114 RoqSize: Int = 192, 115 dpParams: DispatchParameters = DispatchParameters( 116 IntDqSize = 16, 117 FpDqSize = 16, 118 LsDqSize = 16, 119 IntDqDeqWidth = 4, 120 FpDqDeqWidth = 4, 121 LsDqDeqWidth = 4 122 ), 123 exuParameters: ExuParameters = ExuParameters( 124 JmpCnt = 1, 125 AluCnt = 4, 126 MulCnt = 0, 127 MduCnt = 2, 128 FmacCnt = 4, 129 FmiscCnt = 2, 130 FmiscDivSqrtCnt = 0, 131 LduCnt = 2, 132 StuCnt = 2 133 ), 134 LoadPipelineWidth: Int = 2, 135 StorePipelineWidth: Int = 2, 136 StoreBufferSize: Int = 16, 137 StoreBufferThreshold: Int = 7, 138 RefillSize: Int = 512, 139 TlbEntrySize: Int = 32, 140 TlbSPEntrySize: Int = 4, 141 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 142 PtwSPEntrySize: Int = 16, 143 PtwL1EntrySize: Int = 16, 144 PtwL2EntrySize: Int = 2048, //(256 * 8) 145 PtwMissQueueSize: Int = 8, 146 NumPerfCounters: Int = 16, 147 icacheParameters: ICacheParameters = ICacheParameters( 148 tagECC = Some("parity"), 149 dataECC = Some("parity"), 150 replacer = Some("setplru"), 151 nMissEntries = 2 152 ), 153 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 154 tagECC = Some("secded"), 155 dataECC = Some("secded"), 156 replacer = Some("setplru"), 157 nMissEntries = 8 158 ), 159 dcacheParameters: DCacheParameters = DCacheParameters( 160 tagECC = Some("secded"), 161 dataECC = Some("secded"), 162 replacer = Some("setplru"), 163 nMissEntries = 16, 164 nProbeEntries = 16, 165 nReleaseEntries = 16, 166 nStoreReplayEntries = 16 167 ), 168 L2Size: Int = 512 * 1024, // 512KB 169 L2NWays: Int = 8, 170 usePTWRepeater: Boolean = false, 171 useFakePTW: Boolean = false, 172 useFakeDCache: Boolean = false, 173 useFakeL1plusCache: Boolean = false, 174 useFakeL2Cache: Boolean = false 175){ 176 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 177 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg) 178 179 val intExuConfigs = Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 180 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg 181 182 val fpExuConfigs = 183 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 184 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 185 186 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 187} 188 189case object DebugOptionsKey extends Field[DebugOptions] 190 191case class DebugOptions 192( 193 FPGAPlatform: Boolean = true, 194 EnableDebug: Boolean = true, 195 EnablePerfDebug: Boolean = true, 196 UseDRAMSim: Boolean = false 197) 198 199trait HasXSParameter { 200 201 implicit val p: Parameters 202 203 val coreParams = p(XSCoreParamsKey) 204 val env = p(DebugOptionsKey) 205 206 val XLEN = coreParams.XLEN 207 val hardId = coreParams.HartId 208 val minFLen = 32 209 val fLen = 64 210 def xLen = XLEN 211 212 val HasMExtension = coreParams.HasMExtension 213 val HasCExtension = coreParams.HasCExtension 214 val HasDiv = coreParams.HasDiv 215 val HasIcache = coreParams.HasICache 216 val HasDcache = coreParams.HasDCache 217 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 218 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 219 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 220 val AddrBytes = AddrBits / 8 // unused 221 val DataBits = XLEN 222 val DataBytes = DataBits / 8 223 val HasFPU = coreParams.HasFPU 224 val FetchWidth = coreParams.FetchWidth 225 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 226 val EnableBPU = coreParams.EnableBPU 227 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 228 val EnableRAS = coreParams.EnableRAS 229 val EnableLB = coreParams.EnableLB 230 val EnableLoop = coreParams.EnableLoop 231 val EnableSC = coreParams.EnableSC 232 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 233 val HistoryLength = coreParams.HistoryLength 234 val PathHistoryLength = coreParams.PathHistoryLength 235 val BtbSize = coreParams.BtbSize 236 // val BtbWays = 4 237 val BtbBanks = PredictWidth 238 // val BtbSets = BtbSize / BtbWays 239 val JbtacSize = coreParams.JbtacSize 240 val JbtacBanks = coreParams.JbtacBanks 241 val RasSize = coreParams.RasSize 242 243 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 244 coreParams.branchPredictor(resp_in, p, enableSC) 245 } 246 247 val CacheLineSize = coreParams.CacheLineSize 248 val CacheLineHalfWord = CacheLineSize / 16 249 val ExtHistoryLength = HistoryLength + 64 250 val UBtbWays = coreParams.UBtbWays 251 val BtbWays = coreParams.BtbWays 252 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 253 val IBufSize = coreParams.IBufSize 254 val DecodeWidth = coreParams.DecodeWidth 255 val RenameWidth = coreParams.RenameWidth 256 val CommitWidth = coreParams.CommitWidth 257 val BrqSize = coreParams.BrqSize 258 val FtqSize = coreParams.FtqSize 259 val IssQueSize = coreParams.IssQueSize 260 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 261 val BrTagWidth = log2Up(BrqSize) 262 val NRPhyRegs = coreParams.NRPhyRegs 263 val PhyRegIdxWidth = log2Up(NRPhyRegs) 264 val RoqSize = coreParams.RoqSize 265 val LoadQueueSize = coreParams.LoadQueueSize 266 val StoreQueueSize = coreParams.StoreQueueSize 267 val dpParams = coreParams.dpParams 268 val exuParameters = coreParams.exuParameters 269 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 270 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 271 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 272 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 273 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 274 val LoadPipelineWidth = coreParams.LoadPipelineWidth 275 val StorePipelineWidth = coreParams.StorePipelineWidth 276 val StoreBufferSize = coreParams.StoreBufferSize 277 val StoreBufferThreshold = coreParams.StoreBufferThreshold 278 val RefillSize = coreParams.RefillSize 279 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 280 val TlbEntrySize = coreParams.TlbEntrySize 281 val TlbSPEntrySize = coreParams.TlbSPEntrySize 282 val PtwL3EntrySize = coreParams.PtwL3EntrySize 283 val PtwSPEntrySize = coreParams.PtwSPEntrySize 284 val PtwL1EntrySize = coreParams.PtwL1EntrySize 285 val PtwL2EntrySize = coreParams.PtwL2EntrySize 286 val PtwMissQueueSize = coreParams.PtwMissQueueSize 287 val NumPerfCounters = coreParams.NumPerfCounters 288 289 val instBytes = if (HasCExtension) 2 else 4 290 val instOffsetBits = log2Ceil(instBytes) 291 292 val icacheParameters = coreParams.icacheParameters 293 val l1plusCacheParameters = coreParams.l1plusCacheParameters 294 val dcacheParameters = coreParams.dcacheParameters 295 296 val LRSCCycles = 100 297 298 299 // cache hierarchy configurations 300 val l1BusDataWidth = 256 301 302 val usePTWRepeater = coreParams.usePTWRepeater 303 val useFakeDCache = coreParams.useFakeDCache 304 val useFakePTW = coreParams.useFakePTW 305 val useFakeL1plusCache = coreParams.useFakeL1plusCache 306 // L2 configurations 307 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 308 val L1BusWidth = 256 309 val L2Size = coreParams.L2Size 310 val L2BlockSize = 64 311 val L2NWays = coreParams.L2NWays 312 val L2NSets = L2Size / L2BlockSize / L2NWays 313 314 // L3 configurations 315 val L2BusWidth = 256 316 317 // icache prefetcher 318 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 319 enable = true, 320 _type = "stream", 321 streamParams = StreamPrefetchParameters( 322 streamCnt = 2, 323 streamSize = 4, 324 ageWidth = 4, 325 blockBytes = l1plusCacheParameters.blockBytes, 326 reallocStreamOnMissInstantly = true, 327 cacheName = "icache" 328 ) 329 ) 330 331 // dcache prefetcher 332 val l2PrefetcherParameters = L2PrefetcherParameters( 333 enable = true, 334 _type = "bop", // "stream" or "bop" 335 streamParams = StreamPrefetchParameters( 336 streamCnt = 4, 337 streamSize = 4, 338 ageWidth = 4, 339 blockBytes = L2BlockSize, 340 reallocStreamOnMissInstantly = true, 341 cacheName = "dcache" 342 ), 343 bopParams = BOPParameters( 344 rrTableEntries = 256, 345 rrTagBits = 12, 346 scoreBits = 5, 347 roundMax = 50, 348 badScore = 1, 349 blockBytes = L2BlockSize, 350 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 351 ), 352 ) 353 354 // load violation predict 355 val ResetTimeMax2Pow = 20 //1078576 356 val ResetTimeMin2Pow = 10 //1024 357 // wait table parameters 358 val WaitTableSize = 1024 359 val MemPredPCWidth = log2Up(WaitTableSize) 360 val LWTUse2BitCounter = true 361 // store set parameters 362 val SSITSize = WaitTableSize 363 val LFSTSize = 32 364 val SSIDWidth = log2Up(LFSTSize) 365 val LFSTWidth = 4 366 val StoreSetEnable = true // LWT will be disabled if SS is enabled 367 368 val loadExuConfigs = coreParams.loadExuConfigs 369 val storeExuConfigs = coreParams.storeExuConfigs 370 371 val intExuConfigs = coreParams.intExuConfigs 372 373 val fpExuConfigs = coreParams.fpExuConfigs 374 375 val exuConfigs = coreParams.exuConfigs 376 377} 378