xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision 5aae5b8dd522c46434b81201cec5dcbf1bd28e4d) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import xiangshan.backend.exu._
23import xiangshan.backend.fu._
24import xiangshan.backend.fu.fpu._
25import xiangshan.backend.dispatch.DispatchParameters
26import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters}
27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters}
28import freechips.rocketchip.diplomacy.AddressSet
29
30case object XSCoreParamsKey extends Field[XSCoreParameters]
31
32case class XSCoreParameters
33(
34  HasPrefetch: Boolean = false,
35  HartId: Int = 0,
36  XLEN: Int = 64,
37  HasMExtension: Boolean = true,
38  HasCExtension: Boolean = true,
39  HasDiv: Boolean = true,
40  HasICache: Boolean = true,
41  HasDCache: Boolean = true,
42  AddrBits: Int = 64,
43  VAddrBits: Int = 39,
44  PAddrBits: Int = 40,
45  HasFPU: Boolean = true,
46  FetchWidth: Int = 8,
47  EnableBPU: Boolean = true,
48  EnableBPD: Boolean = true,
49  EnableRAS: Boolean = true,
50  EnableLB: Boolean = false,
51  EnableLoop: Boolean = true,
52  EnableSC: Boolean = true,
53  EnbaleTlbDebug: Boolean = false,
54  EnableJal: Boolean = false,
55  EnableUBTB: Boolean = true,
56  HistoryLength: Int = 64,
57  BtbSize: Int = 2048,
58  JbtacSize: Int = 1024,
59  JbtacBanks: Int = 8,
60  RasSize: Int = 16,
61  CacheLineSize: Int = 512,
62  UBtbWays: Int = 16,
63  BtbWays: Int = 2,
64
65  EnableL1plusPrefetcher: Boolean = true,
66  IBufSize: Int = 48,
67  DecodeWidth: Int = 6,
68  RenameWidth: Int = 6,
69  CommitWidth: Int = 6,
70  BrqSize: Int = 32,
71  FtqSize: Int = 48,
72  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
73  IssQueSize: Int = 16,
74  NRPhyRegs: Int = 160,
75  NRIntReadPorts: Int = 14,
76  NRIntWritePorts: Int = 8,
77  NRFpReadPorts: Int = 14,
78  NRFpWritePorts: Int = 8,
79  LoadQueueSize: Int = 64,
80  StoreQueueSize: Int = 48,
81  RoqSize: Int = 192,
82  dpParams: DispatchParameters = DispatchParameters(
83    IntDqSize = 16,
84    FpDqSize = 16,
85    LsDqSize = 16,
86    IntDqDeqWidth = 4,
87    FpDqDeqWidth = 4,
88    LsDqDeqWidth = 4
89  ),
90  exuParameters: ExuParameters = ExuParameters(
91    JmpCnt = 1,
92    AluCnt = 4,
93    MulCnt = 0,
94    MduCnt = 2,
95    FmacCnt = 4,
96    FmiscCnt = 2,
97    FmiscDivSqrtCnt = 0,
98    LduCnt = 2,
99    StuCnt = 2
100  ),
101  LoadPipelineWidth: Int = 2,
102  StorePipelineWidth: Int = 2,
103  StoreBufferSize: Int = 16,
104  StoreBufferThreshold: Int = 7,
105  RefillSize: Int = 512,
106  TlbEntrySize: Int = 8,
107  TlbSPEntrySize: Int = 2,
108  BTlbEntrySize: Int = 64,
109  PtwL3EntrySize: Int = 4096, //(256 * 16) or 512
110  PtwSPEntrySize: Int = 16,
111  PtwL1EntrySize: Int = 16,
112  PtwL2EntrySize: Int = 256, //(256 * 8)
113  PtwMissQueueSize: Int = 8,
114  NumPerfCounters: Int = 16,
115  icacheParameters: ICacheParameters = ICacheParameters(
116    tagECC = Some("parity"),
117    dataECC = Some("parity"),
118    replacer = Some("setplru"),
119    nMissEntries = 2
120  ),
121  l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters(
122    tagECC = Some("secded"),
123    dataECC = Some("secded"),
124    replacer = Some("setplru"),
125    nMissEntries = 8
126  ),
127  dcacheParameters: DCacheParameters = DCacheParameters(
128    tagECC = Some("secded"),
129    dataECC = Some("secded"),
130    replacer = Some("setplru"),
131    nMissEntries = 16,
132    nProbeEntries = 16,
133    nReleaseEntries = 16,
134    nStoreReplayEntries = 16
135  ),
136  L2Size: Int = 512 * 1024, // 512KB
137  L2NWays: Int = 8,
138  usePTWRepeater: Boolean = false,
139  useFakePTW: Boolean = false,
140  useFakeDCache: Boolean = false,
141  useFakeL1plusCache: Boolean = false,
142  useFakeL2Cache: Boolean = false
143){
144  val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
145  val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg)
146
147  val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++
148    Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++
149    Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg)
150
151  val fpExuConfigs =
152    Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++
153      Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg)
154
155  val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs
156}
157
158case object DebugOptionsKey extends Field[DebugOptions]
159
160case class DebugOptions
161(
162  FPGAPlatform: Boolean = true,
163  EnableDebug: Boolean = true,
164  EnablePerfDebug: Boolean = true,
165  UseDRAMSim: Boolean = false
166)
167
168trait HasXSParameter {
169
170  implicit val p: Parameters
171
172  val coreParams = p(XSCoreParamsKey)
173  val env = p(DebugOptionsKey)
174
175  val XLEN = coreParams.XLEN
176  val hardId = coreParams.HartId
177  val minFLen = 32
178  val fLen = 64
179  def xLen = XLEN
180
181  val HasMExtension = coreParams.HasMExtension
182  val HasCExtension = coreParams.HasCExtension
183  val HasDiv = coreParams.HasDiv
184  val HasIcache = coreParams.HasICache
185  val HasDcache = coreParams.HasDCache
186  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
187  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
188  val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits
189  val AddrBytes = AddrBits / 8 // unused
190  val DataBits = XLEN
191  val DataBytes = DataBits / 8
192  val HasFPU = coreParams.HasFPU
193  val FetchWidth = coreParams.FetchWidth
194  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
195  val EnableBPU = coreParams.EnableBPU
196  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
197  val EnableRAS = coreParams.EnableRAS
198  val EnableLB = coreParams.EnableLB
199  val EnableLoop = coreParams.EnableLoop
200  val EnableSC = coreParams.EnableSC
201  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
202  val HistoryLength = coreParams.HistoryLength
203  val BtbSize = coreParams.BtbSize
204  // val BtbWays = 4
205  val BtbBanks = PredictWidth
206  // val BtbSets = BtbSize / BtbWays
207  val JbtacSize = coreParams.JbtacSize
208  val JbtacBanks = coreParams.JbtacBanks
209  val RasSize = coreParams.RasSize
210  val CacheLineSize = coreParams.CacheLineSize
211  val CacheLineHalfWord = CacheLineSize / 16
212  val ExtHistoryLength = HistoryLength + 64
213  val UBtbWays = coreParams.UBtbWays
214  val BtbWays = coreParams.BtbWays
215  val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher
216  val IBufSize = coreParams.IBufSize
217  val DecodeWidth = coreParams.DecodeWidth
218  val RenameWidth = coreParams.RenameWidth
219  val CommitWidth = coreParams.CommitWidth
220  val BrqSize = coreParams.BrqSize
221  val FtqSize = coreParams.FtqSize
222  val IssQueSize = coreParams.IssQueSize
223  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
224  val BrTagWidth = log2Up(BrqSize)
225  val NRPhyRegs = coreParams.NRPhyRegs
226  val PhyRegIdxWidth = log2Up(NRPhyRegs)
227  val RoqSize = coreParams.RoqSize
228  val LoadQueueSize = coreParams.LoadQueueSize
229  val StoreQueueSize = coreParams.StoreQueueSize
230  val dpParams = coreParams.dpParams
231  val exuParameters = coreParams.exuParameters
232  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
233  val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts
234  val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt
235  val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt
236  val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt
237  val LoadPipelineWidth = coreParams.LoadPipelineWidth
238  val StorePipelineWidth = coreParams.StorePipelineWidth
239  val StoreBufferSize = coreParams.StoreBufferSize
240  val StoreBufferThreshold = coreParams.StoreBufferThreshold
241  val RefillSize = coreParams.RefillSize
242  val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
243  val TlbEntrySize = coreParams.TlbEntrySize
244  val TlbSPEntrySize = coreParams.TlbSPEntrySize
245  val BTlbEntrySize = coreParams.BTlbEntrySize
246  val PtwL3EntrySize = coreParams.PtwL3EntrySize
247  val PtwSPEntrySize = coreParams.PtwSPEntrySize
248  val PtwL1EntrySize = coreParams.PtwL1EntrySize
249  val PtwL2EntrySize = coreParams.PtwL2EntrySize
250  val PtwMissQueueSize = coreParams.PtwMissQueueSize
251  val NumPerfCounters = coreParams.NumPerfCounters
252
253  val instBytes = if (HasCExtension) 2 else 4
254  val instOffsetBits = log2Ceil(instBytes)
255
256  val icacheParameters = coreParams.icacheParameters
257  val l1plusCacheParameters = coreParams.l1plusCacheParameters
258  val dcacheParameters = coreParams.dcacheParameters
259
260  val LRSCCycles = 100
261
262
263  // cache hierarchy configurations
264  val l1BusDataWidth = 256
265
266  val usePTWRepeater = coreParams.usePTWRepeater
267  val useFakeDCache = coreParams.useFakeDCache
268  val useFakePTW = coreParams.useFakePTW
269  val useFakeL1plusCache = coreParams.useFakeL1plusCache
270  // L2 configurations
271  val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache
272  val L1BusWidth = 256
273  val L2Size = coreParams.L2Size
274  val L2BlockSize = 64
275  val L2NWays = coreParams.L2NWays
276  val L2NSets = L2Size / L2BlockSize / L2NWays
277
278  // L3 configurations
279  val L2BusWidth = 256
280
281  // icache prefetcher
282  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
283    enable = true,
284    _type = "stream",
285    streamParams = StreamPrefetchParameters(
286      streamCnt = 2,
287      streamSize = 4,
288      ageWidth = 4,
289      blockBytes = l1plusCacheParameters.blockBytes,
290      reallocStreamOnMissInstantly = true,
291      cacheName = "icache"
292    )
293  )
294
295  // dcache prefetcher
296  val l2PrefetcherParameters = L2PrefetcherParameters(
297    enable = true,
298    _type = "bop", // "stream" or "bop"
299    streamParams = StreamPrefetchParameters(
300      streamCnt = 4,
301      streamSize = 4,
302      ageWidth = 4,
303      blockBytes = L2BlockSize,
304      reallocStreamOnMissInstantly = true,
305      cacheName = "dcache"
306    ),
307    bopParams = BOPParameters(
308      rrTableEntries = 256,
309      rrTagBits = 12,
310      scoreBits = 5,
311      roundMax = 50,
312      badScore = 1,
313      blockBytes = L2BlockSize,
314      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
315    ),
316  )
317
318  // load violation predict
319  val ResetTimeMax2Pow = 20 //1078576
320  val ResetTimeMin2Pow = 10 //1024
321  // wait table parameters
322  val WaitTableSize = 1024
323  val MemPredPCWidth = log2Up(WaitTableSize)
324  val LWTUse2BitCounter = true
325  // store set parameters
326  val SSITSize = WaitTableSize
327  val LFSTSize = 32
328  val SSIDWidth = log2Up(LFSTSize)
329  val LFSTWidth = 4
330  val StoreSetEnable = true // LWT will be disabled if SS is enabled
331
332  val loadExuConfigs = coreParams.loadExuConfigs
333  val storeExuConfigs = coreParams.storeExuConfigs
334
335  val intExuConfigs = coreParams.intExuConfigs
336
337  val fpExuConfigs = coreParams.fpExuConfigs
338
339  val exuConfigs = coreParams.exuConfigs
340
341}
342