1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.dispatch.DispatchParameters 26import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, Tage_SC} 30import freechips.rocketchip.diplomacy.AddressSet 31 32case object XSCoreParamsKey extends Field[XSCoreParameters] 33 34case class XSCoreParameters 35( 36 HasPrefetch: Boolean = false, 37 HartId: Int = 0, 38 XLEN: Int = 64, 39 HasMExtension: Boolean = true, 40 HasCExtension: Boolean = true, 41 HasDiv: Boolean = true, 42 HasICache: Boolean = true, 43 HasDCache: Boolean = true, 44 AddrBits: Int = 64, 45 VAddrBits: Int = 39, 46 PAddrBits: Int = 40, 47 HasFPU: Boolean = true, 48 FetchWidth: Int = 8, 49 EnableBPU: Boolean = true, 50 EnableBPD: Boolean = true, 51 EnableRAS: Boolean = true, 52 EnableLB: Boolean = false, 53 EnableLoop: Boolean = true, 54 EnableSC: Boolean = true, 55 EnbaleTlbDebug: Boolean = false, 56 EnableJal: Boolean = false, 57 EnableUBTB: Boolean = true, 58 HistoryLength: Int = 64, 59 PathHistoryLength: Int = 16, 60 BtbSize: Int = 2048, 61 JbtacSize: Int = 1024, 62 JbtacBanks: Int = 8, 63 RasSize: Int = 16, 64 CacheLineSize: Int = 512, 65 UBtbWays: Int = 16, 66 BtbWays: Int = 2, 67 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 68 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 69 // val loop = Module(new LoopPredictor) 70 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 71 // else Module(new Tage) } 72 // else { Module(new FakeTage) }) 73 val ftb = Module(new FTB()(p)) 74 val ubtb = Module(new MicroBTB()(p)) 75 val bim = Module(new BIM()(p)) 76 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 77 val ras = Module(new RAS()(p)) 78 // val tage = Module(new Tage()(p)) 79 // val fake = Module(new FakePredictor()(p)) 80 81 // val preds = Seq(loop, tage, btb, ubtb, bim) 82 val preds = Seq(bim, ubtb, tage, ftb, ras) 83 preds.map(_.io := DontCare) 84 85 // ubtb.io.resp_in(0) := resp_in 86 // bim.io.resp_in(0) := ubtb.io.resp 87 // btb.io.resp_in(0) := bim.io.resp 88 // tage.io.resp_in(0) := btb.io.resp 89 // loop.io.resp_in(0) := tage.io.resp 90 bim.io.in.bits.resp_in(0) := resp_in 91 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 92 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 93 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 94 ras.io.in.bits.resp_in(0) := ftb.io.out.resp 95 96 (preds, ras.io.out.resp) 97 }), 98 99 100 EnableL1plusPrefetcher: Boolean = true, 101 IBufSize: Int = 48, 102 DecodeWidth: Int = 6, 103 RenameWidth: Int = 6, 104 CommitWidth: Int = 6, 105 BrqSize: Int = 32, 106 FtqSize: Int = 64, 107 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 108 IssQueSize: Int = 16, 109 NRPhyRegs: Int = 160, 110 NRIntReadPorts: Int = 14, 111 NRIntWritePorts: Int = 8, 112 NRFpReadPorts: Int = 14, 113 NRFpWritePorts: Int = 8, 114 LoadQueueSize: Int = 64, 115 StoreQueueSize: Int = 48, 116 RoqSize: Int = 192, 117 EnableIntMoveElim: Boolean = true, 118 IntRefCounterWidth: Int = 2, 119 dpParams: DispatchParameters = DispatchParameters( 120 IntDqSize = 16, 121 FpDqSize = 16, 122 LsDqSize = 16, 123 IntDqDeqWidth = 4, 124 FpDqDeqWidth = 4, 125 LsDqDeqWidth = 4 126 ), 127 exuParameters: ExuParameters = ExuParameters( 128 JmpCnt = 1, 129 AluCnt = 4, 130 MulCnt = 0, 131 MduCnt = 2, 132 FmacCnt = 4, 133 FmiscCnt = 2, 134 FmiscDivSqrtCnt = 0, 135 LduCnt = 2, 136 StuCnt = 2 137 ), 138 LoadPipelineWidth: Int = 2, 139 StorePipelineWidth: Int = 2, 140 StoreBufferSize: Int = 16, 141 StoreBufferThreshold: Int = 7, 142 EnableFastForward: Boolean = true, 143 RefillSize: Int = 512, 144 itlbParameters: TLBParameters = TLBParameters( 145 name = "itlb", 146 fetchi = true, 147 useDmode = false, 148 sameCycle = true, 149 normalReplacer = Some("plru"), 150 superReplacer = Some("plru"), 151 shouldBlock = true 152 ), 153 ldtlbParameters: TLBParameters = TLBParameters( 154 name = "ldtlb", 155 normalNSets = 128, 156 normalNWays = 1, 157 normalAssociative = "sa", 158 normalReplacer = Some("setplru"), 159 superNWays = 8, 160 normalAsVictim = true, 161 outReplace = true 162 ), 163 sttlbParameters: TLBParameters = TLBParameters( 164 name = "sttlb", 165 normalNSets = 128, 166 normalNWays = 1, 167 normalAssociative = "sa", 168 normalReplacer = Some("setplru"), 169 superNWays = 8, 170 normalAsVictim = true, 171 outReplace = true 172 ), 173 btlbParameters: TLBParameters = TLBParameters( 174 name = "btlb", 175 normalNSets = 1, 176 normalNWays = 64, 177 superNWays = 4, 178 ), 179 useBTlb: Boolean = false, 180 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 181 NumPerfCounters: Int = 16, 182 icacheParameters: ICacheParameters = ICacheParameters( 183 tagECC = Some("parity"), 184 dataECC = Some("parity"), 185 replacer = Some("setplru"), 186 nMissEntries = 2 187 ), 188 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 189 tagECC = Some("secded"), 190 dataECC = Some("secded"), 191 replacer = Some("setplru"), 192 nMissEntries = 8 193 ), 194 dcacheParameters: DCacheParameters = DCacheParameters( 195 tagECC = Some("secded"), 196 dataECC = Some("secded"), 197 replacer = Some("setplru"), 198 nMissEntries = 16, 199 nProbeEntries = 16, 200 nReleaseEntries = 16, 201 nStoreReplayEntries = 16 202 ), 203 L2Size: Int = 512 * 1024, // 512KB 204 L2NWays: Int = 8, 205 useFakePTW: Boolean = false, 206 useFakeDCache: Boolean = false, 207 useFakeL1plusCache: Boolean = false, 208 useFakeL2Cache: Boolean = false 209){ 210 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 211 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 212 213 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 214 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 215 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 216 217 val fpExuConfigs = 218 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 219 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 220 221 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 222} 223 224case object DebugOptionsKey extends Field[DebugOptions] 225 226case class DebugOptions 227( 228 FPGAPlatform: Boolean = true, 229 EnableDebug: Boolean = true, 230 EnablePerfDebug: Boolean = true, 231 UseDRAMSim: Boolean = false 232) 233 234trait HasXSParameter { 235 236 implicit val p: Parameters 237 238 val coreParams = p(XSCoreParamsKey) 239 val env = p(DebugOptionsKey) 240 241 val XLEN = coreParams.XLEN 242 val hardId = coreParams.HartId 243 val minFLen = 32 244 val fLen = 64 245 def xLen = XLEN 246 247 val HasMExtension = coreParams.HasMExtension 248 val HasCExtension = coreParams.HasCExtension 249 val HasDiv = coreParams.HasDiv 250 val HasIcache = coreParams.HasICache 251 val HasDcache = coreParams.HasDCache 252 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 253 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 254 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 255 val AddrBytes = AddrBits / 8 // unused 256 val DataBits = XLEN 257 val DataBytes = DataBits / 8 258 val HasFPU = coreParams.HasFPU 259 val FetchWidth = coreParams.FetchWidth 260 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 261 val EnableBPU = coreParams.EnableBPU 262 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 263 val EnableRAS = coreParams.EnableRAS 264 val EnableLB = coreParams.EnableLB 265 val EnableLoop = coreParams.EnableLoop 266 val EnableSC = coreParams.EnableSC 267 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 268 val HistoryLength = coreParams.HistoryLength 269 val PathHistoryLength = coreParams.PathHistoryLength 270 val BtbSize = coreParams.BtbSize 271 // val BtbWays = 4 272 val BtbBanks = PredictWidth 273 // val BtbSets = BtbSize / BtbWays 274 val JbtacSize = coreParams.JbtacSize 275 val JbtacBanks = coreParams.JbtacBanks 276 val RasSize = coreParams.RasSize 277 278 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 279 coreParams.branchPredictor(resp_in, p, enableSC) 280 } 281 282 val CacheLineSize = coreParams.CacheLineSize 283 val CacheLineHalfWord = CacheLineSize / 16 284 val ExtHistoryLength = HistoryLength + 64 285 val UBtbWays = coreParams.UBtbWays 286 val BtbWays = coreParams.BtbWays 287 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 288 val IBufSize = coreParams.IBufSize 289 val DecodeWidth = coreParams.DecodeWidth 290 val RenameWidth = coreParams.RenameWidth 291 val CommitWidth = coreParams.CommitWidth 292 val BrqSize = coreParams.BrqSize 293 val FtqSize = coreParams.FtqSize 294 val IssQueSize = coreParams.IssQueSize 295 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 296 val BrTagWidth = log2Up(BrqSize) 297 val NRPhyRegs = coreParams.NRPhyRegs 298 val PhyRegIdxWidth = log2Up(NRPhyRegs) 299 val RoqSize = coreParams.RoqSize 300 val EnableIntMoveElim = coreParams.EnableIntMoveElim 301 val IntRefCounterWidth = coreParams.IntRefCounterWidth 302 val StdFreeListSize = NRPhyRegs - 32 303 val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 } 304 val LoadQueueSize = coreParams.LoadQueueSize 305 val StoreQueueSize = coreParams.StoreQueueSize 306 val dpParams = coreParams.dpParams 307 val exuParameters = coreParams.exuParameters 308 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 309 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 310 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 311 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 312 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 313 val LoadPipelineWidth = coreParams.LoadPipelineWidth 314 val StorePipelineWidth = coreParams.StorePipelineWidth 315 val StoreBufferSize = coreParams.StoreBufferSize 316 val StoreBufferThreshold = coreParams.StoreBufferThreshold 317 val EnableFastForward = coreParams.EnableFastForward 318 val RefillSize = coreParams.RefillSize 319 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 320 val useBTlb = coreParams.useBTlb 321 val itlbParams = coreParams.itlbParameters 322 val ldtlbParams = coreParams.ldtlbParameters 323 val sttlbParams = coreParams.sttlbParameters 324 val btlbParams = coreParams.btlbParameters 325 val l2tlbParams = coreParams.l2tlbParameters 326 val NumPerfCounters = coreParams.NumPerfCounters 327 328 val instBytes = if (HasCExtension) 2 else 4 329 val instOffsetBits = log2Ceil(instBytes) 330 331 val icacheParameters = coreParams.icacheParameters 332 val l1plusCacheParameters = coreParams.l1plusCacheParameters 333 val dcacheParameters = coreParams.dcacheParameters 334 335 val LRSCCycles = 100 336 337 338 // cache hierarchy configurations 339 val l1BusDataWidth = 256 340 341 val useFakeDCache = coreParams.useFakeDCache 342 val useFakePTW = coreParams.useFakePTW 343 val useFakeL1plusCache = coreParams.useFakeL1plusCache 344 // L2 configurations 345 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 346 val L1BusWidth = 256 347 val L2Size = coreParams.L2Size 348 val L2BlockSize = 64 349 val L2NWays = coreParams.L2NWays 350 val L2NSets = L2Size / L2BlockSize / L2NWays 351 352 // L3 configurations 353 val L2BusWidth = 256 354 355 // icache prefetcher 356 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 357 enable = true, 358 _type = "stream", 359 streamParams = StreamPrefetchParameters( 360 streamCnt = 2, 361 streamSize = 4, 362 ageWidth = 4, 363 blockBytes = l1plusCacheParameters.blockBytes, 364 reallocStreamOnMissInstantly = true, 365 cacheName = "icache" 366 ) 367 ) 368 369 // dcache prefetcher 370 val l2PrefetcherParameters = L2PrefetcherParameters( 371 enable = true, 372 _type = "bop", // "stream" or "bop" 373 streamParams = StreamPrefetchParameters( 374 streamCnt = 4, 375 streamSize = 4, 376 ageWidth = 4, 377 blockBytes = L2BlockSize, 378 reallocStreamOnMissInstantly = true, 379 cacheName = "dcache" 380 ), 381 bopParams = BOPParameters( 382 rrTableEntries = 256, 383 rrTagBits = 12, 384 scoreBits = 5, 385 roundMax = 50, 386 badScore = 1, 387 blockBytes = L2BlockSize, 388 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 389 ), 390 ) 391 392 // load violation predict 393 val ResetTimeMax2Pow = 20 //1078576 394 val ResetTimeMin2Pow = 10 //1024 395 // wait table parameters 396 val WaitTableSize = 1024 397 val MemPredPCWidth = log2Up(WaitTableSize) 398 val LWTUse2BitCounter = true 399 // store set parameters 400 val SSITSize = WaitTableSize 401 val LFSTSize = 32 402 val SSIDWidth = log2Up(LFSTSize) 403 val LFSTWidth = 4 404 val StoreSetEnable = true // LWT will be disabled if SS is enabled 405 406 val loadExuConfigs = coreParams.loadExuConfigs 407 val storeExuConfigs = coreParams.storeExuConfigs 408 409 val intExuConfigs = coreParams.intExuConfigs 410 411 val fpExuConfigs = coreParams.fpExuConfigs 412 413 val exuConfigs = coreParams.exuConfigs 414 415} 416