xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision 9aee2f1b31bc25f78eedb144d4e46fed1c8d3f38) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import xiangshan.backend.exu._
23import xiangshan.backend.fu._
24import xiangshan.backend.fu.fpu._
25import xiangshan.backend.dispatch.DispatchParameters
26import xiangshan.cache.{DCacheParameters, L1plusCacheParameters}
27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters}
28import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, Tage_SC}
29import xiangshan.cache.mmu.{L2TLBParameters}
30import freechips.rocketchip.diplomacy.AddressSet
31
32case object XSCoreParamsKey extends Field[XSCoreParameters]
33
34case class XSCoreParameters
35(
36  HasPrefetch: Boolean = false,
37  HartId: Int = 0,
38  XLEN: Int = 64,
39  HasMExtension: Boolean = true,
40  HasCExtension: Boolean = true,
41  HasDiv: Boolean = true,
42  HasICache: Boolean = true,
43  HasDCache: Boolean = true,
44  AddrBits: Int = 64,
45  VAddrBits: Int = 39,
46  PAddrBits: Int = 40,
47  HasFPU: Boolean = true,
48  FetchWidth: Int = 8,
49  EnableBPU: Boolean = true,
50  EnableBPD: Boolean = true,
51  EnableRAS: Boolean = true,
52  EnableLB: Boolean = false,
53  EnableLoop: Boolean = true,
54  EnableSC: Boolean = true,
55  EnbaleTlbDebug: Boolean = false,
56  EnableJal: Boolean = false,
57  EnableUBTB: Boolean = true,
58  HistoryLength: Int = 64,
59  PathHistoryLength: Int = 16,
60  BtbSize: Int = 2048,
61  JbtacSize: Int = 1024,
62  JbtacBanks: Int = 8,
63  RasSize: Int = 16,
64  CacheLineSize: Int = 512,
65  UBtbWays: Int = 16,
66  BtbWays: Int = 2,
67  branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] =
68    ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => {
69      // val loop = Module(new LoopPredictor)
70      // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC)
71      //                             else          Module(new Tage) }
72      //             else          { Module(new FakeTage) })
73      val ftb = Module(new FTB()(p))
74      val ubtb = Module(new MicroBTB()(p))
75      val bim = Module(new BIM()(p))
76      val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) }
77      val ras = Module(new RAS()(p))
78      // val tage = Module(new Tage()(p))
79      // val fake = Module(new FakePredictor()(p))
80
81      // val preds = Seq(loop, tage, btb, ubtb, bim)
82      val preds = Seq(bim, ubtb, tage, ftb, ras)
83      preds.map(_.io := DontCare)
84
85      // ubtb.io.resp_in(0)  := resp_in
86      // bim.io.resp_in(0)   := ubtb.io.resp
87      // btb.io.resp_in(0)   := bim.io.resp
88      // tage.io.resp_in(0)  := btb.io.resp
89      // loop.io.resp_in(0)  := tage.io.resp
90      bim.io.in.bits.resp_in(0)  := resp_in
91      ubtb.io.in.bits.resp_in(0) := bim.io.out.resp
92      tage.io.in.bits.resp_in(0) := ubtb.io.out.resp
93      ftb.io.in.bits.resp_in(0)  := tage.io.out.resp
94      ras.io.in.bits.resp_in(0)  := ftb.io.out.resp
95
96      (preds, ras.io.out.resp)
97    }),
98
99
100  EnableL1plusPrefetcher: Boolean = true,
101  IBufSize: Int = 48,
102  DecodeWidth: Int = 6,
103  RenameWidth: Int = 6,
104  CommitWidth: Int = 6,
105  BrqSize: Int = 32,
106  FtqSize: Int = 64,
107  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
108  IssQueSize: Int = 16,
109  NRPhyRegs: Int = 160,
110  NRIntReadPorts: Int = 14,
111  NRIntWritePorts: Int = 8,
112  NRFpReadPorts: Int = 14,
113  NRFpWritePorts: Int = 8,
114  LoadQueueSize: Int = 64,
115  StoreQueueSize: Int = 48,
116  RoqSize: Int = 192,
117  dpParams: DispatchParameters = DispatchParameters(
118    IntDqSize = 16,
119    FpDqSize = 16,
120    LsDqSize = 16,
121    IntDqDeqWidth = 4,
122    FpDqDeqWidth = 4,
123    LsDqDeqWidth = 4
124  ),
125  exuParameters: ExuParameters = ExuParameters(
126    JmpCnt = 1,
127    AluCnt = 4,
128    MulCnt = 0,
129    MduCnt = 2,
130    FmacCnt = 4,
131    FmiscCnt = 2,
132    FmiscDivSqrtCnt = 0,
133    LduCnt = 2,
134    StuCnt = 2
135  ),
136  LoadPipelineWidth: Int = 2,
137  StorePipelineWidth: Int = 2,
138  StoreBufferSize: Int = 16,
139  StoreBufferThreshold: Int = 7,
140  RefillSize: Int = 512,
141  TlbEntrySize: Int = 32,
142  TlbSPEntrySize: Int = 4,
143  l2tlbParameters: L2TLBParameters = L2TLBParameters(),
144  NumPerfCounters: Int = 16,
145  icacheParameters: ICacheParameters = ICacheParameters(
146    tagECC = Some("parity"),
147    dataECC = Some("parity"),
148    replacer = Some("setplru"),
149    nMissEntries = 2
150  ),
151  l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters(
152    tagECC = Some("secded"),
153    dataECC = Some("secded"),
154    replacer = Some("setplru"),
155    nMissEntries = 8
156  ),
157  dcacheParameters: DCacheParameters = DCacheParameters(
158    tagECC = Some("secded"),
159    dataECC = Some("secded"),
160    replacer = Some("setplru"),
161    nMissEntries = 16,
162    nProbeEntries = 16,
163    nReleaseEntries = 16,
164    nStoreReplayEntries = 16
165  ),
166  L2Size: Int = 512 * 1024, // 512KB
167  L2NWays: Int = 8,
168  usePTWRepeater: Boolean = false,
169  useFakePTW: Boolean = false,
170  useFakeDCache: Boolean = false,
171  useFakeL1plusCache: Boolean = false,
172  useFakeL2Cache: Boolean = false
173){
174  val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
175  val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg)
176
177  val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++
178    Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++
179    Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg)
180
181  val fpExuConfigs =
182    Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++
183      Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg)
184
185  val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs
186}
187
188case object DebugOptionsKey extends Field[DebugOptions]
189
190case class DebugOptions
191(
192  FPGAPlatform: Boolean = true,
193  EnableDebug: Boolean = true,
194  EnablePerfDebug: Boolean = true,
195  UseDRAMSim: Boolean = false
196)
197
198trait HasXSParameter {
199
200  implicit val p: Parameters
201
202  val coreParams = p(XSCoreParamsKey)
203  val env = p(DebugOptionsKey)
204
205  val XLEN = coreParams.XLEN
206  val hardId = coreParams.HartId
207  val minFLen = 32
208  val fLen = 64
209  def xLen = XLEN
210
211  val HasMExtension = coreParams.HasMExtension
212  val HasCExtension = coreParams.HasCExtension
213  val HasDiv = coreParams.HasDiv
214  val HasIcache = coreParams.HasICache
215  val HasDcache = coreParams.HasDCache
216  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
217  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
218  val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits
219  val AddrBytes = AddrBits / 8 // unused
220  val DataBits = XLEN
221  val DataBytes = DataBits / 8
222  val HasFPU = coreParams.HasFPU
223  val FetchWidth = coreParams.FetchWidth
224  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
225  val EnableBPU = coreParams.EnableBPU
226  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
227  val EnableRAS = coreParams.EnableRAS
228  val EnableLB = coreParams.EnableLB
229  val EnableLoop = coreParams.EnableLoop
230  val EnableSC = coreParams.EnableSC
231  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
232  val HistoryLength = coreParams.HistoryLength
233  val PathHistoryLength = coreParams.PathHistoryLength
234  val BtbSize = coreParams.BtbSize
235  // val BtbWays = 4
236  val BtbBanks = PredictWidth
237  // val BtbSets = BtbSize / BtbWays
238  val JbtacSize = coreParams.JbtacSize
239  val JbtacBanks = coreParams.JbtacBanks
240  val RasSize = coreParams.RasSize
241
242  def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = {
243    coreParams.branchPredictor(resp_in, p, enableSC)
244  }
245
246  val CacheLineSize = coreParams.CacheLineSize
247  val CacheLineHalfWord = CacheLineSize / 16
248  val ExtHistoryLength = HistoryLength + 64
249  val UBtbWays = coreParams.UBtbWays
250  val BtbWays = coreParams.BtbWays
251  val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher
252  val IBufSize = coreParams.IBufSize
253  val DecodeWidth = coreParams.DecodeWidth
254  val RenameWidth = coreParams.RenameWidth
255  val CommitWidth = coreParams.CommitWidth
256  val BrqSize = coreParams.BrqSize
257  val FtqSize = coreParams.FtqSize
258  val IssQueSize = coreParams.IssQueSize
259  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
260  val BrTagWidth = log2Up(BrqSize)
261  val NRPhyRegs = coreParams.NRPhyRegs
262  val PhyRegIdxWidth = log2Up(NRPhyRegs)
263  val RoqSize = coreParams.RoqSize
264  val LoadQueueSize = coreParams.LoadQueueSize
265  val StoreQueueSize = coreParams.StoreQueueSize
266  val dpParams = coreParams.dpParams
267  val exuParameters = coreParams.exuParameters
268  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
269  val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts
270  val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt
271  val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt
272  val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt
273  val LoadPipelineWidth = coreParams.LoadPipelineWidth
274  val StorePipelineWidth = coreParams.StorePipelineWidth
275  val StoreBufferSize = coreParams.StoreBufferSize
276  val StoreBufferThreshold = coreParams.StoreBufferThreshold
277  val RefillSize = coreParams.RefillSize
278  val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
279  val TlbEntrySize = coreParams.TlbEntrySize
280  val TlbSPEntrySize = coreParams.TlbSPEntrySize
281  val l2tlbParams = coreParams.l2tlbParameters
282  val NumPerfCounters = coreParams.NumPerfCounters
283
284  val instBytes = if (HasCExtension) 2 else 4
285  val instOffsetBits = log2Ceil(instBytes)
286
287  val icacheParameters = coreParams.icacheParameters
288  val l1plusCacheParameters = coreParams.l1plusCacheParameters
289  val dcacheParameters = coreParams.dcacheParameters
290
291  val LRSCCycles = 100
292
293
294  // cache hierarchy configurations
295  val l1BusDataWidth = 256
296
297  val usePTWRepeater = coreParams.usePTWRepeater
298  val useFakeDCache = coreParams.useFakeDCache
299  val useFakePTW = coreParams.useFakePTW
300  val useFakeL1plusCache = coreParams.useFakeL1plusCache
301  // L2 configurations
302  val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache
303  val L1BusWidth = 256
304  val L2Size = coreParams.L2Size
305  val L2BlockSize = 64
306  val L2NWays = coreParams.L2NWays
307  val L2NSets = L2Size / L2BlockSize / L2NWays
308
309  // L3 configurations
310  val L2BusWidth = 256
311
312  // icache prefetcher
313  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
314    enable = true,
315    _type = "stream",
316    streamParams = StreamPrefetchParameters(
317      streamCnt = 2,
318      streamSize = 4,
319      ageWidth = 4,
320      blockBytes = l1plusCacheParameters.blockBytes,
321      reallocStreamOnMissInstantly = true,
322      cacheName = "icache"
323    )
324  )
325
326  // dcache prefetcher
327  val l2PrefetcherParameters = L2PrefetcherParameters(
328    enable = true,
329    _type = "bop", // "stream" or "bop"
330    streamParams = StreamPrefetchParameters(
331      streamCnt = 4,
332      streamSize = 4,
333      ageWidth = 4,
334      blockBytes = L2BlockSize,
335      reallocStreamOnMissInstantly = true,
336      cacheName = "dcache"
337    ),
338    bopParams = BOPParameters(
339      rrTableEntries = 256,
340      rrTagBits = 12,
341      scoreBits = 5,
342      roundMax = 50,
343      badScore = 1,
344      blockBytes = L2BlockSize,
345      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
346    ),
347  )
348
349  // load violation predict
350  val ResetTimeMax2Pow = 20 //1078576
351  val ResetTimeMin2Pow = 10 //1024
352  // wait table parameters
353  val WaitTableSize = 1024
354  val MemPredPCWidth = log2Up(WaitTableSize)
355  val LWTUse2BitCounter = true
356  // store set parameters
357  val SSITSize = WaitTableSize
358  val LFSTSize = 32
359  val SSIDWidth = log2Up(LFSTSize)
360  val LFSTWidth = 4
361  val StoreSetEnable = true // LWT will be disabled if SS is enabled
362
363  val loadExuConfigs = coreParams.loadExuConfigs
364  val storeExuConfigs = coreParams.storeExuConfigs
365
366  val intExuConfigs = coreParams.intExuConfigs
367
368  val fpExuConfigs = coreParams.fpExuConfigs
369
370  val exuConfigs = coreParams.exuConfigs
371
372}
373