1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.dispatch.DispatchParameters 26import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 28import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 29import xiangshan.cache.mmu.{L2TLBParameters} 30import freechips.rocketchip.diplomacy.AddressSet 31 32case object XSCoreParamsKey extends Field[XSCoreParameters] 33 34case class XSCoreParameters 35( 36 HasPrefetch: Boolean = false, 37 HartId: Int = 0, 38 XLEN: Int = 64, 39 HasMExtension: Boolean = true, 40 HasCExtension: Boolean = true, 41 HasDiv: Boolean = true, 42 HasICache: Boolean = true, 43 HasDCache: Boolean = true, 44 AddrBits: Int = 64, 45 VAddrBits: Int = 39, 46 PAddrBits: Int = 40, 47 HasFPU: Boolean = true, 48 FetchWidth: Int = 8, 49 EnableBPU: Boolean = true, 50 EnableBPD: Boolean = true, 51 EnableRAS: Boolean = true, 52 EnableLB: Boolean = false, 53 EnableLoop: Boolean = true, 54 EnableSC: Boolean = true, 55 EnbaleTlbDebug: Boolean = false, 56 EnableJal: Boolean = false, 57 EnableUBTB: Boolean = true, 58 HistoryLength: Int = 64, 59 PathHistoryLength: Int = 16, 60 BtbSize: Int = 2048, 61 JbtacSize: Int = 1024, 62 JbtacBanks: Int = 8, 63 RasSize: Int = 32, 64 CacheLineSize: Int = 512, 65 UBtbWays: Int = 16, 66 BtbWays: Int = 2, 67 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 68 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 69 // val loop = Module(new LoopPredictor) 70 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 71 // else Module(new Tage) } 72 // else { Module(new FakeTage) }) 73 val ftb = Module(new FTB()(p)) 74 val ubtb = Module(new MicroBTB()(p)) 75 val bim = Module(new BIM()(p)) 76 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 77 val ras = Module(new RAS()(p)) 78 val ittage = Module(new ITTage()(p)) 79 // val tage = Module(new Tage()(p)) 80 // val fake = Module(new FakePredictor()(p)) 81 82 // val preds = Seq(loop, tage, btb, ubtb, bim) 83 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 84 preds.map(_.io := DontCare) 85 86 // ubtb.io.resp_in(0) := resp_in 87 // bim.io.resp_in(0) := ubtb.io.resp 88 // btb.io.resp_in(0) := bim.io.resp 89 // tage.io.resp_in(0) := btb.io.resp 90 // loop.io.resp_in(0) := tage.io.resp 91 bim.io.in.bits.resp_in(0) := resp_in 92 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 93 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 94 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 95 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 96 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 97 98 (preds, ras.io.out.resp) 99 }), 100 101 102 EnableL1plusPrefetcher: Boolean = true, 103 IBufSize: Int = 48, 104 DecodeWidth: Int = 6, 105 RenameWidth: Int = 6, 106 CommitWidth: Int = 6, 107 BrqSize: Int = 32, 108 FtqSize: Int = 64, 109 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 110 IssQueSize: Int = 16, 111 NRPhyRegs: Int = 160, 112 NRIntReadPorts: Int = 14, 113 NRIntWritePorts: Int = 8, 114 NRFpReadPorts: Int = 14, 115 NRFpWritePorts: Int = 8, 116 LoadQueueSize: Int = 64, 117 StoreQueueSize: Int = 48, 118 RoqSize: Int = 192, 119 dpParams: DispatchParameters = DispatchParameters( 120 IntDqSize = 16, 121 FpDqSize = 16, 122 LsDqSize = 16, 123 IntDqDeqWidth = 4, 124 FpDqDeqWidth = 4, 125 LsDqDeqWidth = 4 126 ), 127 exuParameters: ExuParameters = ExuParameters( 128 JmpCnt = 1, 129 AluCnt = 4, 130 MulCnt = 0, 131 MduCnt = 2, 132 FmacCnt = 4, 133 FmiscCnt = 2, 134 FmiscDivSqrtCnt = 0, 135 LduCnt = 2, 136 StuCnt = 2 137 ), 138 LoadPipelineWidth: Int = 2, 139 StorePipelineWidth: Int = 2, 140 StoreBufferSize: Int = 16, 141 StoreBufferThreshold: Int = 7, 142 RefillSize: Int = 512, 143 TlbEntrySize: Int = 32, 144 TlbSPEntrySize: Int = 4, 145 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 146 NumPerfCounters: Int = 16, 147 icacheParameters: ICacheParameters = ICacheParameters( 148 tagECC = Some("parity"), 149 dataECC = Some("parity"), 150 replacer = Some("setplru"), 151 nMissEntries = 2 152 ), 153 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 154 tagECC = Some("secded"), 155 dataECC = Some("secded"), 156 replacer = Some("setplru"), 157 nMissEntries = 8 158 ), 159 dcacheParameters: DCacheParameters = DCacheParameters( 160 tagECC = Some("secded"), 161 dataECC = Some("secded"), 162 replacer = Some("setplru"), 163 nMissEntries = 16, 164 nProbeEntries = 16, 165 nReleaseEntries = 16, 166 nStoreReplayEntries = 16 167 ), 168 L2Size: Int = 512 * 1024, // 512KB 169 L2NWays: Int = 8, 170 usePTWRepeater: Boolean = false, 171 useFakePTW: Boolean = false, 172 useFakeDCache: Boolean = false, 173 useFakeL1plusCache: Boolean = false, 174 useFakeL2Cache: Boolean = false 175){ 176 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 177 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 178 179 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 180 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 181 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 182 183 val fpExuConfigs = 184 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 185 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 186 187 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 188} 189 190case object DebugOptionsKey extends Field[DebugOptions] 191 192case class DebugOptions 193( 194 FPGAPlatform: Boolean = true, 195 EnableDebug: Boolean = true, 196 EnablePerfDebug: Boolean = true, 197 UseDRAMSim: Boolean = false 198) 199 200trait HasXSParameter { 201 202 implicit val p: Parameters 203 204 val coreParams = p(XSCoreParamsKey) 205 val env = p(DebugOptionsKey) 206 207 val XLEN = coreParams.XLEN 208 val hardId = coreParams.HartId 209 val minFLen = 32 210 val fLen = 64 211 def xLen = XLEN 212 213 val HasMExtension = coreParams.HasMExtension 214 val HasCExtension = coreParams.HasCExtension 215 val HasDiv = coreParams.HasDiv 216 val HasIcache = coreParams.HasICache 217 val HasDcache = coreParams.HasDCache 218 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 219 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 220 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 221 val AddrBytes = AddrBits / 8 // unused 222 val DataBits = XLEN 223 val DataBytes = DataBits / 8 224 val HasFPU = coreParams.HasFPU 225 val FetchWidth = coreParams.FetchWidth 226 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 227 val EnableBPU = coreParams.EnableBPU 228 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 229 val EnableRAS = coreParams.EnableRAS 230 val EnableLB = coreParams.EnableLB 231 val EnableLoop = coreParams.EnableLoop 232 val EnableSC = coreParams.EnableSC 233 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 234 val HistoryLength = coreParams.HistoryLength 235 val PathHistoryLength = coreParams.PathHistoryLength 236 val BtbSize = coreParams.BtbSize 237 // val BtbWays = 4 238 val BtbBanks = PredictWidth 239 // val BtbSets = BtbSize / BtbWays 240 val JbtacSize = coreParams.JbtacSize 241 val JbtacBanks = coreParams.JbtacBanks 242 val RasSize = coreParams.RasSize 243 244 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 245 coreParams.branchPredictor(resp_in, p, enableSC) 246 } 247 248 val CacheLineSize = coreParams.CacheLineSize 249 val CacheLineHalfWord = CacheLineSize / 16 250 val ExtHistoryLength = HistoryLength + 64 251 val UBtbWays = coreParams.UBtbWays 252 val BtbWays = coreParams.BtbWays 253 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 254 val IBufSize = coreParams.IBufSize 255 val DecodeWidth = coreParams.DecodeWidth 256 val RenameWidth = coreParams.RenameWidth 257 val CommitWidth = coreParams.CommitWidth 258 val BrqSize = coreParams.BrqSize 259 val FtqSize = coreParams.FtqSize 260 val IssQueSize = coreParams.IssQueSize 261 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 262 val BrTagWidth = log2Up(BrqSize) 263 val NRPhyRegs = coreParams.NRPhyRegs 264 val PhyRegIdxWidth = log2Up(NRPhyRegs) 265 val RoqSize = coreParams.RoqSize 266 val LoadQueueSize = coreParams.LoadQueueSize 267 val StoreQueueSize = coreParams.StoreQueueSize 268 val dpParams = coreParams.dpParams 269 val exuParameters = coreParams.exuParameters 270 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 271 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 272 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 273 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 274 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 275 val LoadPipelineWidth = coreParams.LoadPipelineWidth 276 val StorePipelineWidth = coreParams.StorePipelineWidth 277 val StoreBufferSize = coreParams.StoreBufferSize 278 val StoreBufferThreshold = coreParams.StoreBufferThreshold 279 val RefillSize = coreParams.RefillSize 280 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 281 val TlbEntrySize = coreParams.TlbEntrySize 282 val TlbSPEntrySize = coreParams.TlbSPEntrySize 283 val l2tlbParams = coreParams.l2tlbParameters 284 val NumPerfCounters = coreParams.NumPerfCounters 285 286 val instBytes = if (HasCExtension) 2 else 4 287 val instOffsetBits = log2Ceil(instBytes) 288 289 val icacheParameters = coreParams.icacheParameters 290 val l1plusCacheParameters = coreParams.l1plusCacheParameters 291 val dcacheParameters = coreParams.dcacheParameters 292 293 val LRSCCycles = 100 294 295 296 // cache hierarchy configurations 297 val l1BusDataWidth = 256 298 299 val usePTWRepeater = coreParams.usePTWRepeater 300 val useFakeDCache = coreParams.useFakeDCache 301 val useFakePTW = coreParams.useFakePTW 302 val useFakeL1plusCache = coreParams.useFakeL1plusCache 303 // L2 configurations 304 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 305 val L1BusWidth = 256 306 val L2Size = coreParams.L2Size 307 val L2BlockSize = 64 308 val L2NWays = coreParams.L2NWays 309 val L2NSets = L2Size / L2BlockSize / L2NWays 310 311 // L3 configurations 312 val L2BusWidth = 256 313 314 // icache prefetcher 315 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 316 enable = true, 317 _type = "stream", 318 streamParams = StreamPrefetchParameters( 319 streamCnt = 2, 320 streamSize = 4, 321 ageWidth = 4, 322 blockBytes = l1plusCacheParameters.blockBytes, 323 reallocStreamOnMissInstantly = true, 324 cacheName = "icache" 325 ) 326 ) 327 328 // dcache prefetcher 329 val l2PrefetcherParameters = L2PrefetcherParameters( 330 enable = true, 331 _type = "bop", // "stream" or "bop" 332 streamParams = StreamPrefetchParameters( 333 streamCnt = 4, 334 streamSize = 4, 335 ageWidth = 4, 336 blockBytes = L2BlockSize, 337 reallocStreamOnMissInstantly = true, 338 cacheName = "dcache" 339 ), 340 bopParams = BOPParameters( 341 rrTableEntries = 256, 342 rrTagBits = 12, 343 scoreBits = 5, 344 roundMax = 50, 345 badScore = 1, 346 blockBytes = L2BlockSize, 347 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 348 ), 349 ) 350 351 // load violation predict 352 val ResetTimeMax2Pow = 20 //1078576 353 val ResetTimeMin2Pow = 10 //1024 354 // wait table parameters 355 val WaitTableSize = 1024 356 val MemPredPCWidth = log2Up(WaitTableSize) 357 val LWTUse2BitCounter = true 358 // store set parameters 359 val SSITSize = WaitTableSize 360 val LFSTSize = 32 361 val SSIDWidth = log2Up(LFSTSize) 362 val LFSTWidth = 4 363 val StoreSetEnable = true // LWT will be disabled if SS is enabled 364 365 val loadExuConfigs = coreParams.loadExuConfigs 366 val storeExuConfigs = coreParams.storeExuConfigs 367 368 val intExuConfigs = coreParams.intExuConfigs 369 370 val fpExuConfigs = coreParams.fpExuConfigs 371 372 val exuConfigs = coreParams.exuConfigs 373 374} 375