Merge remote-tracking branch 'origin/master' into rf-after-issue

Merge pull request #1883 from OpenXiangShan/merge-l1-pf-master

sms,ldu,dcache: prefetch to l1 framework & new load flow arb

Merge remote-tracking branch 'origin/master' into rf-after-issue

MMU: Add Fake L1 TLB (#1888)

ldu: do not override ldflow when ld replay

TODO: ldflow from prefetch to be added to ldflow select logic

Added sms prefetcher

Merge remote-tracking branch 'origin/master' into rf-after-issue

dcache: setup way predictor framework (#1857)

This commit sets up a basic dcache way predictor framework and a dummy predictor.
A Way Predictor Unit (WPU) module has been added to dcache. Dcache da

dcache: setup way predictor framework (#1857)

This commit sets up a basic dcache way predictor framework and a dummy predictor.
A Way Predictor Unit (WPU) module has been added to dcache. Dcache data SRAMs
have been reorganized for that.

The dummy predictor is disabled by default.

Besides, dcache bank conflict check has been optimized. It may cause timing problems,
to be fixed in the future.

* ideal wpu

* BankedDataArray: change architecture to reduce bank_conflict

* BankedDataArray: add db analysis

* Merge: the rest

* BankedDataArray: change the logic of rrl_bank_conflict, but let the number of rw_bank_conflict up

* Load Logic: changed to be as expected

reading data will be delayed by one cycle to make selection
writing data will be also delayed by one cycle to do write operation

* fix: ecc check error

* update the gitignore

* WPU: add regular wpu and change the replay mechanism

* WPU: fix refill fail bug, but a new addiw fail bug appears

* WPU: temporarily turn off to PR

* WPU: tfix all bug

* loadqueue: fix the initialization of replayCarry

* bankeddataarray: fix the bug

* DCacheWrapper: fix bug

* ready-to-run: correct the version

* WayPredictor: comments clean

* BankedDataArray: fix ecc_bank bug

* Parameter: set the enable signal of wpu

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Merge remote-tracking branch 'origin/master' into rf-after-issue

Difftest: add vec regs

RegFile: add vector regfile

MMU: Add ChiselDB and Fake PTW (#1858)

* L2TLB: Fix a bug of Prefetcher

* MMU: Add ChiselDB

* MMU: Add Fake PTW

* MMU: Fix ChiselDB for dual core

vector rename: support vector register rename

Merge branch 'rf-after-issue' of https://github.com/OpenXiangShan/XiangShan into rf-after-issue

CSR: support vcsr

vlsu: define vlsu io (#1853)

Uncache: optimize write operation (#1844)

This commit adds an uncache write buffer to accelerate uncache write

For uncacheable address range, now we use atomic bit in PMA to indicate
uncache wri

Uncache: optimize write operation (#1844)

This commit adds an uncache write buffer to accelerate uncache write

For uncacheable address range, now we use atomic bit in PMA to indicate
uncache write in this range should not use uncache write buffer.

Note that XiangShan does not support atomic insts in uncacheable address range.

* uncache: optimize write operation

* pma: add atomic config

* uncache: assign hartId

* remove some pma atomic

* extend peripheral id width

Co-authored-by: Lyn <[email protected]>

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Replay all load instructions from LQ (#1838)

This intermediate architecture replays all load instructions from LQ.
An independent load replay queue will be added later.

Performance loss caused b

Replay all load instructions from LQ (#1838)

This intermediate architecture replays all load instructions from LQ.
An independent load replay queue will be added later.

Performance loss caused by changing of load replay sequences will be
analyzed in the future.

* memblock: load queue based replay

* replay load from load queue rather than RS
* use counters to delay replay logic

* memblock: refactor priority

* lsq-replay has higher priority than try pointchasing

* RS: remove load store rs's feedback port

* ld-replay: a new path for fast replay

* when fast replay needed, wire it to loadqueue and it will be selected
this cycle and replay to load pipline s0 in next cycle

* memblock: refactor load S0

* move all the select logic from lsq to load S0
* split a tlbReplayDelayCycleCtrl out of loadqueue to speed up
generating emu

* loadqueue: parameterize replay

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Merge pull request #1831 from OpenXiangShan/nanhu-lsu-timing-to-master

Rebase nanhu lsu timing opt to master

std: add an extra pipe stage for std (#1704)

top-down: introduce top-down counters and scripts (#1803)

* top-down: add initial top-down features

* rob600: enlarge queue/buffer size

* :art: After git pull

* :sparkles: Add BranchResteer

top-down: introduce top-down counters and scripts (#1803)

* top-down: add initial top-down features

* rob600: enlarge queue/buffer size

* :art: After git pull

* :sparkles: Add BranchResteers->CtrlBlock

* :sparkles: Cg BranchResteers after pending

* :sparkles: Add robflush_bubble & ldReplay_bubble

* :ambulance: Fix loadReplay->loadReplay.valid

* :art: Dlt printf

* :sparkles: Add stage2_redirect_cycles->CtrlBlock

* :saprkles: CtrlBlock:Add s2Redirect_when_pending

* :sparkles: ID:Add ifu2id_allNO_cycle

* :sparkles: Add ifu2ibuffer_validCnt

* :sparkles: Add ibuffer_IDWidth_hvButNotFull

* :sparkles: Fix ifu2ibuffer_validCnt

* :ambulance: Fix ibuffer_IDWidth_hvButNotFull

* :sparkles: Fix ifu2ibuffer_validCnt->stop

* feat(buggy): parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* fix(SBuffer): fix idx update logic

* fix(Sbuffer): use `&&` to generate flushMask instead of `||`

* fix(atomic): parameterize atomic logic in `MemBlock`

* fix(StoreQueue): update allow enque requirement

* chore: update comments, requirements and assertions

* chore: refactor some Mux to meet original logic

* feat: reduce `LsMaxRsDeq` to 2 and delete it

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

* top-down: add initial top-down features

* rob600: enlarge queue/buffer size

* top-down: add l1, l2, l3 and ddr loads bound perf counters

* top-down: dig into l1d loads bound

* top-down: move memory related counters to `Scheduler`

* top-down: add 2 Ldus and 2 Stus

* top-down: v1.0

* huancun: bump HuanCun to a version with top-down

* chore: restore parameters and update `build.sc`

* top-down: use ExcitingUtils instead of BoringUtils

* top-down: add switch of top-down counters

* top-down: add top-down scripts

* difftest: enlarge stuck limit cycles again

Co-authored-by: gaozeyu <[email protected]>

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bpu: remove minimal pred and old ubtb

bpu: implement fully-associated micro ftb to replace current ubtb

bpu: refactor prediction i/o bundles

dtlb: change volume from s128f8 to s64f16 (#1662)

DTLB volume configuration:
old: normal page 128 direct-asso + super page 8 full-asso
new: normal page 64 direct-asso + super page 16 full-asso
Be

dtlb: change volume from s128f8 to s64f16 (#1662)

DTLB volume configuration:
old: normal page 128 direct-asso + super page 8 full-asso
new: normal page 64 direct-asso + super page 16 full-asso
Better timing and better driver now.

For Spec06，some specs increase slightly, while some others decrease slightly.

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