1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableFauFTB: Boolean = true, 64 UbtbGHRLength: Int = 4, 65 // HistoryLength: Int = 512, 66 EnableGHistDiff: Boolean = true, 67 UbtbSize: Int = 256, 68 FtbSize: Int = 2048, 69 RasSize: Int = 32, 70 CacheLineSize: Int = 512, 71 FtbWays: Int = 4, 72 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 73 // Sets Hist Tag 74 // Seq(( 2048, 2, 8), 75 // ( 2048, 9, 8), 76 // ( 2048, 13, 8), 77 // ( 2048, 20, 8), 78 // ( 2048, 26, 8), 79 // ( 2048, 44, 8), 80 // ( 2048, 73, 8), 81 // ( 2048, 256, 8)), 82 Seq(( 4096, 8, 8), 83 ( 4096, 13, 8), 84 ( 4096, 32, 8), 85 ( 4096, 119, 8)), 86 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 87 // Sets Hist Tag 88 Seq(( 256, 4, 9), 89 ( 256, 8, 9), 90 ( 512, 13, 9), 91 ( 512, 16, 9), 92 ( 512, 32, 9)), 93 SCNRows: Int = 512, 94 SCNTables: Int = 4, 95 SCCtrBits: Int = 6, 96 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 97 numBr: Int = 2, 98 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 99 ((resp_in: BranchPredictionResp, p: Parameters) => { 100 val ftb = Module(new FTB()(p)) 101 val ubtb =Module(new FauFTB()(p)) 102 // val bim = Module(new BIM()(p)) 103 val tage = Module(new Tage_SC()(p)) 104 val ras = Module(new RAS()(p)) 105 val ittage = Module(new ITTage()(p)) 106 val preds = Seq(ubtb, tage, ftb, ittage, ras) 107 preds.map(_.io := DontCare) 108 109 // ubtb.io.resp_in(0) := resp_in 110 // bim.io.resp_in(0) := ubtb.io.resp 111 // btb.io.resp_in(0) := bim.io.resp 112 // tage.io.resp_in(0) := btb.io.resp 113 // loop.io.resp_in(0) := tage.io.resp 114 ubtb.io.in.bits.resp_in(0) := resp_in 115 tage.io.in.bits.resp_in(0) := ubtb.io.out 116 ftb.io.in.bits.resp_in(0) := tage.io.out 117 ittage.io.in.bits.resp_in(0) := ftb.io.out 118 ras.io.in.bits.resp_in(0) := ittage.io.out 119 120 (preds, ras.io.out) 121 }), 122 IBufSize: Int = 48, 123 DecodeWidth: Int = 6, 124 RenameWidth: Int = 6, 125 CommitWidth: Int = 6, 126 FtqSize: Int = 64, 127 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 128 IssQueSize: Int = 16, 129 NRPhyRegs: Int = 192, 130 LoadQueueSize: Int = 80, 131 LoadQueueNWriteBanks: Int = 8, 132 StoreQueueSize: Int = 64, 133 StoreQueueNWriteBanks: Int = 8, 134 VlsQueueSize: Int = 8, 135 RobSize: Int = 256, 136 dpParams: DispatchParameters = DispatchParameters( 137 IntDqSize = 16, 138 FpDqSize = 16, 139 LsDqSize = 16, 140 IntDqDeqWidth = 4, 141 FpDqDeqWidth = 4, 142 LsDqDeqWidth = 4 143 ), 144 exuParameters: ExuParameters = ExuParameters( 145 JmpCnt = 1, 146 AluCnt = 4, 147 MulCnt = 0, 148 MduCnt = 2, 149 FmacCnt = 4, 150 FmiscCnt = 2, 151 FmiscDivSqrtCnt = 0, 152 LduCnt = 2, 153 StuCnt = 2 154 ), 155 LoadPipelineWidth: Int = 2, 156 StorePipelineWidth: Int = 2, 157 VecMemSrcInWidth: Int = 2, 158 VecMemInstWbWidth: Int = 1, 159 VecMemDispatchWidth: Int = 1, 160 StoreBufferSize: Int = 16, 161 StoreBufferThreshold: Int = 7, 162 EnsbufferWidth: Int = 2, 163 UncacheBufferSize: Int = 4, 164 EnableLoadToLoadForward: Boolean = true, 165 EnableFastForward: Boolean = false, 166 EnableLdVioCheckAfterReset: Boolean = true, 167 EnableSoftPrefetchAfterReset: Boolean = true, 168 EnableCacheErrorAfterReset: Boolean = true, 169 EnableDCacheWPU: Boolean = false, 170 EnableAccurateLoadError: Boolean = true, 171 EnableUncacheWriteOutstanding: Boolean = true, 172 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 173 ReSelectLen: Int = 6, // load replay queue replay select counter len 174 itlbParameters: TLBParameters = TLBParameters( 175 name = "itlb", 176 fetchi = true, 177 useDmode = false, 178 normalNWays = 32, 179 normalReplacer = Some("plru"), 180 superNWays = 4, 181 superReplacer = Some("plru") 182 ), 183 ldtlbParameters: TLBParameters = TLBParameters( 184 name = "ldtlb", 185 normalNSets = 64, 186 normalNWays = 1, 187 normalAssociative = "sa", 188 normalReplacer = Some("setplru"), 189 superNWays = 16, 190 normalAsVictim = true, 191 outReplace = false, 192 partialStaticPMP = true, 193 outsideRecvFlush = true, 194 saveLevel = true 195 ), 196 sttlbParameters: TLBParameters = TLBParameters( 197 name = "sttlb", 198 normalNSets = 64, 199 normalNWays = 1, 200 normalAssociative = "sa", 201 normalReplacer = Some("setplru"), 202 superNWays = 16, 203 normalAsVictim = true, 204 outReplace = false, 205 partialStaticPMP = true, 206 outsideRecvFlush = true, 207 saveLevel = true 208 ), 209 refillBothTlb: Boolean = false, 210 btlbParameters: TLBParameters = TLBParameters( 211 name = "btlb", 212 normalNSets = 1, 213 normalNWays = 64, 214 superNWays = 4, 215 ), 216 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 217 NumPerfCounters: Int = 16, 218 icacheParameters: ICacheParameters = ICacheParameters( 219 tagECC = Some("parity"), 220 dataECC = Some("parity"), 221 replacer = Some("setplru"), 222 nMissEntries = 2, 223 nProbeEntries = 2, 224 nPrefetchEntries = 2, 225 hasPrefetch = true, 226 ), 227 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 228 tagECC = Some("secded"), 229 dataECC = Some("secded"), 230 replacer = Some("setplru"), 231 nMissEntries = 16, 232 nProbeEntries = 8, 233 nReleaseEntries = 18 234 )), 235 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 236 name = "l2", 237 level = 2, 238 ways = 8, 239 sets = 1024, // default 512KB L2 240 prefetch = Some(huancun.prefetch.BOPParameters()) 241 )), 242 L2NBanks: Int = 1, 243 usePTWRepeater: Boolean = false, 244 softTLB: Boolean = false, // dpi-c l1tlb debug only 245 softPTW: Boolean = false, // dpi-c l2tlb debug only 246 softPTWDelay: Int = 1 247){ 248 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 249 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 250 251 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 252 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 253 254 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 255 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 256 257 val fpExuConfigs = 258 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 259 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 260 261 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 262} 263 264case object DebugOptionsKey extends Field[DebugOptions] 265 266case class DebugOptions 267( 268 FPGAPlatform: Boolean = false, 269 EnableDifftest: Boolean = false, 270 AlwaysBasicDiff: Boolean = true, 271 EnableDebug: Boolean = false, 272 EnablePerfDebug: Boolean = true, 273 UseDRAMSim: Boolean = false, 274 EnableTopDown: Boolean = false 275) 276 277trait HasXSParameter { 278 279 implicit val p: Parameters 280 281 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 282 283 val coreParams = p(XSCoreParamsKey) 284 val env = p(DebugOptionsKey) 285 286 val XLEN = coreParams.XLEN 287 val minFLen = 32 288 val fLen = 64 289 def xLen = XLEN 290 291 val HasMExtension = coreParams.HasMExtension 292 val HasCExtension = coreParams.HasCExtension 293 val HasDiv = coreParams.HasDiv 294 val HasIcache = coreParams.HasICache 295 val HasDcache = coreParams.HasDCache 296 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 297 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 298 val AsidLength = coreParams.AsidLength 299 val ReSelectLen = coreParams.ReSelectLen 300 val AddrBytes = AddrBits / 8 // unused 301 val DataBits = XLEN 302 val DataBytes = DataBits / 8 303 val HasFPU = coreParams.HasFPU 304 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 305 val FetchWidth = coreParams.FetchWidth 306 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 307 val EnableBPU = coreParams.EnableBPU 308 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 309 val EnableRAS = coreParams.EnableRAS 310 val EnableLB = coreParams.EnableLB 311 val EnableLoop = coreParams.EnableLoop 312 val EnableSC = coreParams.EnableSC 313 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 314 val HistoryLength = coreParams.HistoryLength 315 val EnableGHistDiff = coreParams.EnableGHistDiff 316 val UbtbGHRLength = coreParams.UbtbGHRLength 317 val UbtbSize = coreParams.UbtbSize 318 val EnableFauFTB = coreParams.EnableFauFTB 319 val FtbSize = coreParams.FtbSize 320 val FtbWays = coreParams.FtbWays 321 val RasSize = coreParams.RasSize 322 323 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 324 coreParams.branchPredictor(resp_in, p) 325 } 326 val numBr = coreParams.numBr 327 val TageTableInfos = coreParams.TageTableInfos 328 val TageBanks = coreParams.numBr 329 val SCNRows = coreParams.SCNRows 330 val SCCtrBits = coreParams.SCCtrBits 331 val SCHistLens = coreParams.SCHistLens 332 val SCNTables = coreParams.SCNTables 333 334 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 335 case ((n, cb), h) => (n, cb, h) 336 } 337 val ITTageTableInfos = coreParams.ITTageTableInfos 338 type FoldedHistoryInfo = Tuple2[Int, Int] 339 val foldedGHistInfos = 340 (TageTableInfos.map{ case (nRows, h, t) => 341 if (h > 0) 342 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 343 else 344 Set[FoldedHistoryInfo]() 345 }.reduce(_++_).toSet ++ 346 SCTableInfos.map{ case (nRows, _, h) => 347 if (h > 0) 348 Set((h, min(log2Ceil(nRows/TageBanks), h))) 349 else 350 Set[FoldedHistoryInfo]() 351 }.reduce(_++_).toSet ++ 352 ITTageTableInfos.map{ case (nRows, h, t) => 353 if (h > 0) 354 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 355 else 356 Set[FoldedHistoryInfo]() 357 }.reduce(_++_) ++ 358 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 359 ).toList 360 361 362 363 val CacheLineSize = coreParams.CacheLineSize 364 val CacheLineHalfWord = CacheLineSize / 16 365 val ExtHistoryLength = HistoryLength + 64 366 val IBufSize = coreParams.IBufSize 367 val DecodeWidth = coreParams.DecodeWidth 368 val RenameWidth = coreParams.RenameWidth 369 val CommitWidth = coreParams.CommitWidth 370 val FtqSize = coreParams.FtqSize 371 val IssQueSize = coreParams.IssQueSize 372 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 373 val NRPhyRegs = coreParams.NRPhyRegs 374 val PhyRegIdxWidth = log2Up(NRPhyRegs) 375 val RobSize = coreParams.RobSize 376 val IntRefCounterWidth = log2Ceil(RobSize) 377 val LoadQueueSize = coreParams.LoadQueueSize 378 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 379 val StoreQueueSize = coreParams.StoreQueueSize 380 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 381 val VlsQueueSize = coreParams.VlsQueueSize 382 val dpParams = coreParams.dpParams 383 val exuParameters = coreParams.exuParameters 384 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 385 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 386 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 387 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 388 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 389 val LoadPipelineWidth = coreParams.LoadPipelineWidth 390 val StorePipelineWidth = coreParams.StorePipelineWidth 391 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 392 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 393 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 394 val StoreBufferSize = coreParams.StoreBufferSize 395 val StoreBufferThreshold = coreParams.StoreBufferThreshold 396 val EnsbufferWidth = coreParams.EnsbufferWidth 397 val UncacheBufferSize = coreParams.UncacheBufferSize 398 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 399 val EnableFastForward = coreParams.EnableFastForward 400 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 401 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 402 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 403 val EnableDCacheWPU = coreParams.EnableDCacheWPU 404 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 405 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 406 val asidLen = coreParams.MMUAsidLen 407 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 408 val refillBothTlb = coreParams.refillBothTlb 409 val itlbParams = coreParams.itlbParameters 410 val ldtlbParams = coreParams.ldtlbParameters 411 val sttlbParams = coreParams.sttlbParameters 412 val btlbParams = coreParams.btlbParameters 413 val l2tlbParams = coreParams.l2tlbParameters 414 val NumPerfCounters = coreParams.NumPerfCounters 415 416 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 417 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 418 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 419 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 420 421 val instBytes = if (HasCExtension) 2 else 4 422 val instOffsetBits = log2Ceil(instBytes) 423 424 val icacheParameters = coreParams.icacheParameters 425 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 426 427 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 428 // for constrained LR/SC loop 429 val LRSCCycles = 64 430 // for lr storm 431 val LRSCBackOff = 8 432 433 // cache hierarchy configurations 434 val l1BusDataWidth = 256 435 436 // load violation predict 437 val ResetTimeMax2Pow = 20 //1078576 438 val ResetTimeMin2Pow = 10 //1024 439 // wait table parameters 440 val WaitTableSize = 1024 441 val MemPredPCWidth = log2Up(WaitTableSize) 442 val LWTUse2BitCounter = true 443 // store set parameters 444 val SSITSize = WaitTableSize 445 val LFSTSize = 32 446 val SSIDWidth = log2Up(LFSTSize) 447 val LFSTWidth = 4 448 val StoreSetEnable = true // LWT will be disabled if SS is enabled 449 450 val loadExuConfigs = coreParams.loadExuConfigs 451 val storeExuConfigs = coreParams.storeExuConfigs 452 453 val intExuConfigs = coreParams.intExuConfigs 454 455 val fpExuConfigs = coreParams.fpExuConfigs 456 457 val exuConfigs = coreParams.exuConfigs 458 459 val PCntIncrStep: Int = 6 460 val numPCntHc: Int = 25 461 val numPCntPtw: Int = 19 462 463 val numCSRPCntFrontend = 8 464 val numCSRPCntCtrl = 8 465 val numCSRPCntLsu = 8 466 val numCSRPCntHc = 5 467} 468