1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableFauFTB: Boolean = true, 64 UbtbGHRLength: Int = 4, 65 // HistoryLength: Int = 512, 66 EnableGHistDiff: Boolean = true, 67 UbtbSize: Int = 256, 68 FtbSize: Int = 2048, 69 RasSize: Int = 32, 70 CacheLineSize: Int = 512, 71 FtbWays: Int = 4, 72 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 73 // Sets Hist Tag 74 // Seq(( 2048, 2, 8), 75 // ( 2048, 9, 8), 76 // ( 2048, 13, 8), 77 // ( 2048, 20, 8), 78 // ( 2048, 26, 8), 79 // ( 2048, 44, 8), 80 // ( 2048, 73, 8), 81 // ( 2048, 256, 8)), 82 Seq(( 4096, 8, 8), 83 ( 4096, 13, 8), 84 ( 4096, 32, 8), 85 ( 4096, 119, 8)), 86 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 87 // Sets Hist Tag 88 Seq(( 256, 4, 9), 89 ( 256, 8, 9), 90 ( 512, 13, 9), 91 ( 512, 16, 9), 92 ( 512, 32, 9)), 93 SCNRows: Int = 512, 94 SCNTables: Int = 4, 95 SCCtrBits: Int = 6, 96 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 97 numBr: Int = 2, 98 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 99 ((resp_in: BranchPredictionResp, p: Parameters) => { 100 val ftb = Module(new FTB()(p)) 101 val ubtb =Module(new FauFTB()(p)) 102 // val bim = Module(new BIM()(p)) 103 val tage = Module(new Tage_SC()(p)) 104 val ras = Module(new RAS()(p)) 105 val ittage = Module(new ITTage()(p)) 106 val preds = Seq(ubtb, tage, ftb, ittage, ras) 107 preds.map(_.io := DontCare) 108 109 // ubtb.io.resp_in(0) := resp_in 110 // bim.io.resp_in(0) := ubtb.io.resp 111 // btb.io.resp_in(0) := bim.io.resp 112 // tage.io.resp_in(0) := btb.io.resp 113 // loop.io.resp_in(0) := tage.io.resp 114 ubtb.io.in.bits.resp_in(0) := resp_in 115 tage.io.in.bits.resp_in(0) := ubtb.io.out 116 ftb.io.in.bits.resp_in(0) := tage.io.out 117 ittage.io.in.bits.resp_in(0) := ftb.io.out 118 ras.io.in.bits.resp_in(0) := ittage.io.out 119 120 (preds, ras.io.out) 121 }), 122 IBufSize: Int = 48, 123 DecodeWidth: Int = 6, 124 RenameWidth: Int = 6, 125 CommitWidth: Int = 6, 126 FtqSize: Int = 64, 127 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 128 IssQueSize: Int = 16, 129 NRPhyRegs: Int = 192, 130 LoadQueueSize: Int = 80, 131 StoreQueueSize: Int = 64, 132 RobSize: Int = 256, 133 dpParams: DispatchParameters = DispatchParameters( 134 IntDqSize = 16, 135 FpDqSize = 16, 136 LsDqSize = 16, 137 IntDqDeqWidth = 4, 138 FpDqDeqWidth = 4, 139 LsDqDeqWidth = 4 140 ), 141 exuParameters: ExuParameters = ExuParameters( 142 JmpCnt = 1, 143 AluCnt = 4, 144 MulCnt = 0, 145 MduCnt = 2, 146 FmacCnt = 4, 147 FmiscCnt = 2, 148 FmiscDivSqrtCnt = 0, 149 LduCnt = 2, 150 StuCnt = 2 151 ), 152 LoadPipelineWidth: Int = 2, 153 StorePipelineWidth: Int = 2, 154 StoreBufferSize: Int = 16, 155 StoreBufferThreshold: Int = 7, 156 EnsbufferWidth: Int = 2, 157 EnableLoadToLoadForward: Boolean = true, 158 EnableFastForward: Boolean = false, 159 EnableLdVioCheckAfterReset: Boolean = true, 160 EnableSoftPrefetchAfterReset: Boolean = true, 161 EnableCacheErrorAfterReset: Boolean = true, 162 EnableAccurateLoadError: Boolean = true, 163 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 164 itlbParameters: TLBParameters = TLBParameters( 165 name = "itlb", 166 fetchi = true, 167 useDmode = false, 168 normalNWays = 32, 169 normalReplacer = Some("plru"), 170 superNWays = 4, 171 superReplacer = Some("plru") 172 ), 173 ldtlbParameters: TLBParameters = TLBParameters( 174 name = "ldtlb", 175 normalNSets = 64, 176 normalNWays = 1, 177 normalAssociative = "sa", 178 normalReplacer = Some("setplru"), 179 superNWays = 16, 180 normalAsVictim = true, 181 outReplace = false, 182 partialStaticPMP = true, 183 outsideRecvFlush = true, 184 saveLevel = true 185 ), 186 sttlbParameters: TLBParameters = TLBParameters( 187 name = "sttlb", 188 normalNSets = 64, 189 normalNWays = 1, 190 normalAssociative = "sa", 191 normalReplacer = Some("setplru"), 192 superNWays = 16, 193 normalAsVictim = true, 194 outReplace = false, 195 partialStaticPMP = true, 196 outsideRecvFlush = true, 197 saveLevel = true 198 ), 199 refillBothTlb: Boolean = false, 200 btlbParameters: TLBParameters = TLBParameters( 201 name = "btlb", 202 normalNSets = 1, 203 normalNWays = 64, 204 superNWays = 4, 205 ), 206 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 207 NumPerfCounters: Int = 16, 208 icacheParameters: ICacheParameters = ICacheParameters( 209 tagECC = Some("parity"), 210 dataECC = Some("parity"), 211 replacer = Some("setplru"), 212 nMissEntries = 2, 213 nProbeEntries = 2, 214 nPrefetchEntries = 2, 215 hasPrefetch = true, 216 ), 217 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 218 tagECC = Some("secded"), 219 dataECC = Some("secded"), 220 replacer = Some("setplru"), 221 nMissEntries = 16, 222 nProbeEntries = 8, 223 nReleaseEntries = 18 224 )), 225 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 226 name = "l2", 227 level = 2, 228 ways = 8, 229 sets = 1024, // default 512KB L2 230 prefetch = Some(huancun.prefetch.BOPParameters()) 231 )), 232 L2NBanks: Int = 1, 233 usePTWRepeater: Boolean = false, 234 softPTW: Boolean = false // dpi-c debug only 235){ 236 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 237 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 238 239 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 240 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 241 242 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 243 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 244 245 val fpExuConfigs = 246 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 247 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 248 249 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 250} 251 252case object DebugOptionsKey extends Field[DebugOptions] 253 254case class DebugOptions 255( 256 FPGAPlatform: Boolean = false, 257 EnableDifftest: Boolean = false, 258 AlwaysBasicDiff: Boolean = true, 259 EnableDebug: Boolean = false, 260 EnablePerfDebug: Boolean = true, 261 UseDRAMSim: Boolean = false 262) 263 264trait HasXSParameter { 265 266 implicit val p: Parameters 267 268 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 269 270 val coreParams = p(XSCoreParamsKey) 271 val env = p(DebugOptionsKey) 272 273 val XLEN = coreParams.XLEN 274 val minFLen = 32 275 val fLen = 64 276 def xLen = XLEN 277 278 val HasMExtension = coreParams.HasMExtension 279 val HasCExtension = coreParams.HasCExtension 280 val HasDiv = coreParams.HasDiv 281 val HasIcache = coreParams.HasICache 282 val HasDcache = coreParams.HasDCache 283 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 284 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 285 val AsidLength = coreParams.AsidLength 286 val AddrBytes = AddrBits / 8 // unused 287 val DataBits = XLEN 288 val DataBytes = DataBits / 8 289 val HasFPU = coreParams.HasFPU 290 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 291 val FetchWidth = coreParams.FetchWidth 292 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 293 val EnableBPU = coreParams.EnableBPU 294 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 295 val EnableRAS = coreParams.EnableRAS 296 val EnableLB = coreParams.EnableLB 297 val EnableLoop = coreParams.EnableLoop 298 val EnableSC = coreParams.EnableSC 299 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 300 val HistoryLength = coreParams.HistoryLength 301 val EnableGHistDiff = coreParams.EnableGHistDiff 302 val UbtbGHRLength = coreParams.UbtbGHRLength 303 val UbtbSize = coreParams.UbtbSize 304 val EnableFauFTB = coreParams.EnableFauFTB 305 val FtbSize = coreParams.FtbSize 306 val FtbWays = coreParams.FtbWays 307 val RasSize = coreParams.RasSize 308 309 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 310 coreParams.branchPredictor(resp_in, p) 311 } 312 val numBr = coreParams.numBr 313 val TageTableInfos = coreParams.TageTableInfos 314 val TageBanks = coreParams.numBr 315 val SCNRows = coreParams.SCNRows 316 val SCCtrBits = coreParams.SCCtrBits 317 val SCHistLens = coreParams.SCHistLens 318 val SCNTables = coreParams.SCNTables 319 320 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 321 case ((n, cb), h) => (n, cb, h) 322 } 323 val ITTageTableInfos = coreParams.ITTageTableInfos 324 type FoldedHistoryInfo = Tuple2[Int, Int] 325 val foldedGHistInfos = 326 (TageTableInfos.map{ case (nRows, h, t) => 327 if (h > 0) 328 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 329 else 330 Set[FoldedHistoryInfo]() 331 }.reduce(_++_).toSet ++ 332 SCTableInfos.map{ case (nRows, _, h) => 333 if (h > 0) 334 Set((h, min(log2Ceil(nRows/TageBanks), h))) 335 else 336 Set[FoldedHistoryInfo]() 337 }.reduce(_++_).toSet ++ 338 ITTageTableInfos.map{ case (nRows, h, t) => 339 if (h > 0) 340 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 341 else 342 Set[FoldedHistoryInfo]() 343 }.reduce(_++_) ++ 344 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 345 ).toList 346 347 348 349 val CacheLineSize = coreParams.CacheLineSize 350 val CacheLineHalfWord = CacheLineSize / 16 351 val ExtHistoryLength = HistoryLength + 64 352 val IBufSize = coreParams.IBufSize 353 val DecodeWidth = coreParams.DecodeWidth 354 val RenameWidth = coreParams.RenameWidth 355 val CommitWidth = coreParams.CommitWidth 356 val FtqSize = coreParams.FtqSize 357 val IssQueSize = coreParams.IssQueSize 358 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 359 val NRPhyRegs = coreParams.NRPhyRegs 360 val PhyRegIdxWidth = log2Up(NRPhyRegs) 361 val RobSize = coreParams.RobSize 362 val IntRefCounterWidth = log2Ceil(RobSize) 363 val LoadQueueSize = coreParams.LoadQueueSize 364 val StoreQueueSize = coreParams.StoreQueueSize 365 val dpParams = coreParams.dpParams 366 val exuParameters = coreParams.exuParameters 367 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 368 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 369 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 370 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 371 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 372 val LoadPipelineWidth = coreParams.LoadPipelineWidth 373 val StorePipelineWidth = coreParams.StorePipelineWidth 374 val StoreBufferSize = coreParams.StoreBufferSize 375 val StoreBufferThreshold = coreParams.StoreBufferThreshold 376 val EnsbufferWidth = coreParams.EnsbufferWidth 377 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 378 val EnableFastForward = coreParams.EnableFastForward 379 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 380 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 381 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 382 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 383 val asidLen = coreParams.MMUAsidLen 384 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 385 val refillBothTlb = coreParams.refillBothTlb 386 val itlbParams = coreParams.itlbParameters 387 val ldtlbParams = coreParams.ldtlbParameters 388 val sttlbParams = coreParams.sttlbParameters 389 val btlbParams = coreParams.btlbParameters 390 val l2tlbParams = coreParams.l2tlbParameters 391 val NumPerfCounters = coreParams.NumPerfCounters 392 393 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 394 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 395 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 396 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 397 398 val instBytes = if (HasCExtension) 2 else 4 399 val instOffsetBits = log2Ceil(instBytes) 400 401 val icacheParameters = coreParams.icacheParameters 402 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 403 404 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 405 // for constrained LR/SC loop 406 val LRSCCycles = 64 407 // for lr storm 408 val LRSCBackOff = 8 409 410 // cache hierarchy configurations 411 val l1BusDataWidth = 256 412 413 // load violation predict 414 val ResetTimeMax2Pow = 20 //1078576 415 val ResetTimeMin2Pow = 10 //1024 416 // wait table parameters 417 val WaitTableSize = 1024 418 val MemPredPCWidth = log2Up(WaitTableSize) 419 val LWTUse2BitCounter = true 420 // store set parameters 421 val SSITSize = WaitTableSize 422 val LFSTSize = 32 423 val SSIDWidth = log2Up(LFSTSize) 424 val LFSTWidth = 4 425 val StoreSetEnable = true // LWT will be disabled if SS is enabled 426 427 val loadExuConfigs = coreParams.loadExuConfigs 428 val storeExuConfigs = coreParams.storeExuConfigs 429 430 val intExuConfigs = coreParams.intExuConfigs 431 432 val fpExuConfigs = coreParams.fpExuConfigs 433 434 val exuConfigs = coreParams.exuConfigs 435 436 val PCntIncrStep: Int = 6 437 val numPCntHc: Int = 25 438 val numPCntPtw: Int = 19 439 440 val numCSRPCntFrontend = 8 441 val numCSRPCntCtrl = 8 442 val numCSRPCntLsu = 8 443 val numCSRPCntHc = 5 444} 445