1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 34 35import scala.math.min 36 37case object XSTileKey extends Field[Seq[XSCoreParameters]] 38 39case object XSCoreParamsKey extends Field[XSCoreParameters] 40 41case class XSCoreParameters 42( 43 HasPrefetch: Boolean = false, 44 HartId: Int = 0, 45 XLEN: Int = 64, 46 HasMExtension: Boolean = true, 47 HasCExtension: Boolean = true, 48 HasDiv: Boolean = true, 49 HasICache: Boolean = true, 50 HasDCache: Boolean = true, 51 AddrBits: Int = 64, 52 VAddrBits: Int = 39, 53 HasFPU: Boolean = true, 54 HasCustomCSRCacheOp: Boolean = true, 55 FetchWidth: Int = 8, 56 AsidLength: Int = 16, 57 EnableBPU: Boolean = true, 58 EnableBPD: Boolean = true, 59 EnableRAS: Boolean = true, 60 EnableLB: Boolean = false, 61 EnableLoop: Boolean = true, 62 EnableSC: Boolean = true, 63 EnbaleTlbDebug: Boolean = false, 64 EnableJal: Boolean = false, 65 EnableFauFTB: Boolean = true, 66 UbtbGHRLength: Int = 4, 67 // HistoryLength: Int = 512, 68 EnableGHistDiff: Boolean = true, 69 UbtbSize: Int = 256, 70 FtbSize: Int = 2048, 71 RasSize: Int = 32, 72 CacheLineSize: Int = 512, 73 FtbWays: Int = 4, 74 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 75 // Sets Hist Tag 76 // Seq(( 2048, 2, 8), 77 // ( 2048, 9, 8), 78 // ( 2048, 13, 8), 79 // ( 2048, 20, 8), 80 // ( 2048, 26, 8), 81 // ( 2048, 44, 8), 82 // ( 2048, 73, 8), 83 // ( 2048, 256, 8)), 84 Seq(( 4096, 8, 8), 85 ( 4096, 13, 8), 86 ( 4096, 32, 8), 87 ( 4096, 119, 8)), 88 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 89 // Sets Hist Tag 90 Seq(( 256, 4, 9), 91 ( 256, 8, 9), 92 ( 512, 13, 9), 93 ( 512, 16, 9), 94 ( 512, 32, 9)), 95 SCNRows: Int = 512, 96 SCNTables: Int = 4, 97 SCCtrBits: Int = 6, 98 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 99 numBr: Int = 2, 100 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 101 ((resp_in: BranchPredictionResp, p: Parameters) => { 102 val ftb = Module(new FTB()(p)) 103 val ubtb =Module(new FauFTB()(p)) 104 // val bim = Module(new BIM()(p)) 105 val tage = Module(new Tage_SC()(p)) 106 val ras = Module(new RAS()(p)) 107 val ittage = Module(new ITTage()(p)) 108 val preds = Seq(ubtb, tage, ftb, ittage, ras) 109 preds.map(_.io := DontCare) 110 111 // ubtb.io.resp_in(0) := resp_in 112 // bim.io.resp_in(0) := ubtb.io.resp 113 // btb.io.resp_in(0) := bim.io.resp 114 // tage.io.resp_in(0) := btb.io.resp 115 // loop.io.resp_in(0) := tage.io.resp 116 ubtb.io.in.bits.resp_in(0) := resp_in 117 tage.io.in.bits.resp_in(0) := ubtb.io.out 118 ftb.io.in.bits.resp_in(0) := tage.io.out 119 ittage.io.in.bits.resp_in(0) := ftb.io.out 120 ras.io.in.bits.resp_in(0) := ittage.io.out 121 122 (preds, ras.io.out) 123 }), 124 IBufSize: Int = 48, 125 DecodeWidth: Int = 6, 126 RenameWidth: Int = 6, 127 CommitWidth: Int = 6, 128 FtqSize: Int = 64, 129 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 130 IssQueSize: Int = 16, 131 NRPhyRegs: Int = 192, 132 LoadQueueSize: Int = 80, 133 LoadQueueNWriteBanks: Int = 8, 134 StoreQueueSize: Int = 64, 135 StoreQueueNWriteBanks: Int = 8, 136 VlsQueueSize: Int = 8, 137 RobSize: Int = 256, 138 dpParams: DispatchParameters = DispatchParameters( 139 IntDqSize = 16, 140 FpDqSize = 16, 141 LsDqSize = 16, 142 IntDqDeqWidth = 4, 143 FpDqDeqWidth = 4, 144 LsDqDeqWidth = 4 145 ), 146 exuParameters: ExuParameters = ExuParameters( 147 JmpCnt = 1, 148 AluCnt = 4, 149 MulCnt = 0, 150 MduCnt = 2, 151 FmacCnt = 4, 152 FmiscCnt = 2, 153 FmiscDivSqrtCnt = 0, 154 LduCnt = 2, 155 StuCnt = 2 156 ), 157 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 158 LoadPipelineWidth: Int = 2, 159 StorePipelineWidth: Int = 2, 160 VecMemSrcInWidth: Int = 2, 161 VecMemInstWbWidth: Int = 1, 162 VecMemDispatchWidth: Int = 1, 163 StoreBufferSize: Int = 16, 164 StoreBufferThreshold: Int = 7, 165 EnsbufferWidth: Int = 2, 166 UncacheBufferSize: Int = 4, 167 EnableLoadToLoadForward: Boolean = true, 168 EnableFastForward: Boolean = false, 169 EnableLdVioCheckAfterReset: Boolean = true, 170 EnableSoftPrefetchAfterReset: Boolean = true, 171 EnableCacheErrorAfterReset: Boolean = true, 172 EnableDCacheWPU: Boolean = false, 173 EnableAccurateLoadError: Boolean = true, 174 EnableUncacheWriteOutstanding: Boolean = true, 175 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 176 ReSelectLen: Int = 6, // load replay queue replay select counter len 177 itlbParameters: TLBParameters = TLBParameters( 178 name = "itlb", 179 fetchi = true, 180 useDmode = false, 181 normalNWays = 32, 182 normalReplacer = Some("plru"), 183 superNWays = 4, 184 superReplacer = Some("plru") 185 ), 186 ldtlbParameters: TLBParameters = TLBParameters( 187 name = "ldtlb", 188 normalNSets = 64, 189 normalNWays = 1, 190 normalAssociative = "sa", 191 normalReplacer = Some("setplru"), 192 superNWays = 16, 193 normalAsVictim = true, 194 outReplace = false, 195 partialStaticPMP = true, 196 outsideRecvFlush = true, 197 saveLevel = true 198 ), 199 sttlbParameters: TLBParameters = TLBParameters( 200 name = "sttlb", 201 normalNSets = 64, 202 normalNWays = 1, 203 normalAssociative = "sa", 204 normalReplacer = Some("setplru"), 205 superNWays = 16, 206 normalAsVictim = true, 207 outReplace = false, 208 partialStaticPMP = true, 209 outsideRecvFlush = true, 210 saveLevel = true 211 ), 212 refillBothTlb: Boolean = false, 213 btlbParameters: TLBParameters = TLBParameters( 214 name = "btlb", 215 normalNSets = 1, 216 normalNWays = 64, 217 superNWays = 4, 218 ), 219 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 220 NumPerfCounters: Int = 16, 221 icacheParameters: ICacheParameters = ICacheParameters( 222 tagECC = Some("parity"), 223 dataECC = Some("parity"), 224 replacer = Some("setplru"), 225 nMissEntries = 2, 226 nProbeEntries = 2, 227 nPrefetchEntries = 2, 228 hasPrefetch = true, 229 ), 230 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 231 tagECC = Some("secded"), 232 dataECC = Some("secded"), 233 replacer = Some("setplru"), 234 nMissEntries = 16, 235 nProbeEntries = 8, 236 nReleaseEntries = 18 237 )), 238 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 239 name = "l2", 240 level = 2, 241 ways = 8, 242 sets = 1024, // default 512KB L2 243 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()) 244 )), 245 L2NBanks: Int = 1, 246 usePTWRepeater: Boolean = false, 247 softPTW: Boolean = false, // dpi-c debug only 248 softPTWDelay: Int = 1 249){ 250 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 251 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 252 253 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 254 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 255 256 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 257 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 258 259 val fpExuConfigs = 260 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 261 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 262 263 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 264} 265 266case object DebugOptionsKey extends Field[DebugOptions] 267 268case class DebugOptions 269( 270 FPGAPlatform: Boolean = false, 271 EnableDifftest: Boolean = false, 272 AlwaysBasicDiff: Boolean = true, 273 EnableDebug: Boolean = false, 274 EnablePerfDebug: Boolean = true, 275 UseDRAMSim: Boolean = false, 276 EnableTopDown: Boolean = false 277) 278 279trait HasXSParameter { 280 281 implicit val p: Parameters 282 283 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 284 285 val coreParams = p(XSCoreParamsKey) 286 val env = p(DebugOptionsKey) 287 288 val XLEN = coreParams.XLEN 289 val minFLen = 32 290 val fLen = 64 291 def xLen = XLEN 292 293 val HasMExtension = coreParams.HasMExtension 294 val HasCExtension = coreParams.HasCExtension 295 val HasDiv = coreParams.HasDiv 296 val HasIcache = coreParams.HasICache 297 val HasDcache = coreParams.HasDCache 298 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 299 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 300 val AsidLength = coreParams.AsidLength 301 val ReSelectLen = coreParams.ReSelectLen 302 val AddrBytes = AddrBits / 8 // unused 303 val DataBits = XLEN 304 val DataBytes = DataBits / 8 305 val HasFPU = coreParams.HasFPU 306 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 307 val FetchWidth = coreParams.FetchWidth 308 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 309 val EnableBPU = coreParams.EnableBPU 310 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 311 val EnableRAS = coreParams.EnableRAS 312 val EnableLB = coreParams.EnableLB 313 val EnableLoop = coreParams.EnableLoop 314 val EnableSC = coreParams.EnableSC 315 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 316 val HistoryLength = coreParams.HistoryLength 317 val EnableGHistDiff = coreParams.EnableGHistDiff 318 val UbtbGHRLength = coreParams.UbtbGHRLength 319 val UbtbSize = coreParams.UbtbSize 320 val EnableFauFTB = coreParams.EnableFauFTB 321 val FtbSize = coreParams.FtbSize 322 val FtbWays = coreParams.FtbWays 323 val RasSize = coreParams.RasSize 324 325 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 326 coreParams.branchPredictor(resp_in, p) 327 } 328 val numBr = coreParams.numBr 329 val TageTableInfos = coreParams.TageTableInfos 330 val TageBanks = coreParams.numBr 331 val SCNRows = coreParams.SCNRows 332 val SCCtrBits = coreParams.SCCtrBits 333 val SCHistLens = coreParams.SCHistLens 334 val SCNTables = coreParams.SCNTables 335 336 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 337 case ((n, cb), h) => (n, cb, h) 338 } 339 val ITTageTableInfos = coreParams.ITTageTableInfos 340 type FoldedHistoryInfo = Tuple2[Int, Int] 341 val foldedGHistInfos = 342 (TageTableInfos.map{ case (nRows, h, t) => 343 if (h > 0) 344 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 345 else 346 Set[FoldedHistoryInfo]() 347 }.reduce(_++_).toSet ++ 348 SCTableInfos.map{ case (nRows, _, h) => 349 if (h > 0) 350 Set((h, min(log2Ceil(nRows/TageBanks), h))) 351 else 352 Set[FoldedHistoryInfo]() 353 }.reduce(_++_).toSet ++ 354 ITTageTableInfos.map{ case (nRows, h, t) => 355 if (h > 0) 356 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 357 else 358 Set[FoldedHistoryInfo]() 359 }.reduce(_++_) ++ 360 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 361 ).toList 362 363 364 365 val CacheLineSize = coreParams.CacheLineSize 366 val CacheLineHalfWord = CacheLineSize / 16 367 val ExtHistoryLength = HistoryLength + 64 368 val IBufSize = coreParams.IBufSize 369 val DecodeWidth = coreParams.DecodeWidth 370 val RenameWidth = coreParams.RenameWidth 371 val CommitWidth = coreParams.CommitWidth 372 val FtqSize = coreParams.FtqSize 373 val IssQueSize = coreParams.IssQueSize 374 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 375 val NRPhyRegs = coreParams.NRPhyRegs 376 val PhyRegIdxWidth = log2Up(NRPhyRegs) 377 val RobSize = coreParams.RobSize 378 val IntRefCounterWidth = log2Ceil(RobSize) 379 val LoadQueueSize = coreParams.LoadQueueSize 380 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 381 val StoreQueueSize = coreParams.StoreQueueSize 382 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 383 val VlsQueueSize = coreParams.VlsQueueSize 384 val dpParams = coreParams.dpParams 385 val exuParameters = coreParams.exuParameters 386 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 387 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 388 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 389 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 390 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 391 val LoadPipelineWidth = coreParams.LoadPipelineWidth 392 val StorePipelineWidth = coreParams.StorePipelineWidth 393 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 394 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 395 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 396 val StoreBufferSize = coreParams.StoreBufferSize 397 val StoreBufferThreshold = coreParams.StoreBufferThreshold 398 val EnsbufferWidth = coreParams.EnsbufferWidth 399 val UncacheBufferSize = coreParams.UncacheBufferSize 400 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 401 val EnableFastForward = coreParams.EnableFastForward 402 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 403 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 404 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 405 val EnableDCacheWPU = coreParams.EnableDCacheWPU 406 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 407 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 408 val asidLen = coreParams.MMUAsidLen 409 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 410 val refillBothTlb = coreParams.refillBothTlb 411 val itlbParams = coreParams.itlbParameters 412 val ldtlbParams = coreParams.ldtlbParameters 413 val ld_tlb_ports = if(coreParams.prefetcher.nonEmpty) 3 else 2 414 val sttlbParams = coreParams.sttlbParameters 415 val btlbParams = coreParams.btlbParameters 416 val l2tlbParams = coreParams.l2tlbParameters 417 val NumPerfCounters = coreParams.NumPerfCounters 418 419 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 420 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 421 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 422 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 423 424 val instBytes = if (HasCExtension) 2 else 4 425 val instOffsetBits = log2Ceil(instBytes) 426 427 val icacheParameters = coreParams.icacheParameters 428 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 429 430 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 431 // for constrained LR/SC loop 432 val LRSCCycles = 64 433 // for lr storm 434 val LRSCBackOff = 8 435 436 // cache hierarchy configurations 437 val l1BusDataWidth = 256 438 439 // load violation predict 440 val ResetTimeMax2Pow = 20 //1078576 441 val ResetTimeMin2Pow = 10 //1024 442 // wait table parameters 443 val WaitTableSize = 1024 444 val MemPredPCWidth = log2Up(WaitTableSize) 445 val LWTUse2BitCounter = true 446 // store set parameters 447 val SSITSize = WaitTableSize 448 val LFSTSize = 32 449 val SSIDWidth = log2Up(LFSTSize) 450 val LFSTWidth = 4 451 val StoreSetEnable = true // LWT will be disabled if SS is enabled 452 453 val loadExuConfigs = coreParams.loadExuConfigs 454 val storeExuConfigs = coreParams.storeExuConfigs 455 456 val intExuConfigs = coreParams.intExuConfigs 457 458 val fpExuConfigs = coreParams.fpExuConfigs 459 460 val exuConfigs = coreParams.exuConfigs 461 462 val PCntIncrStep: Int = 6 463 val numPCntHc: Int = 25 464 val numPCntPtw: Int = 19 465 466 val numCSRPCntFrontend = 8 467 val numCSRPCntCtrl = 8 468 val numCSRPCntLsu = 8 469 val numCSRPCntHc = 5 470} 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