xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision 73faecdc3b68e7fdacd4c95f2fdeda671edeb235) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import xiangshan.backend.exu._
23import xiangshan.backend.dispatch.DispatchParameters
24import xiangshan.cache.DCacheParameters
25import xiangshan.cache.prefetch._
26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB}
27import xiangshan.frontend.icache.ICacheParameters
28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
29import freechips.rocketchip.diplomacy.AddressSet
30import system.SoCParamsKey
31import huancun._
32import huancun.debug._
33import scala.math.min
34
35case object XSTileKey extends Field[Seq[XSCoreParameters]]
36
37case object XSCoreParamsKey extends Field[XSCoreParameters]
38
39case class XSCoreParameters
40(
41  HasPrefetch: Boolean = false,
42  HartId: Int = 0,
43  XLEN: Int = 64,
44  VLEN: Int = 128,
45  HasMExtension: Boolean = true,
46  HasCExtension: Boolean = true,
47  HasDiv: Boolean = true,
48  HasICache: Boolean = true,
49  HasDCache: Boolean = true,
50  AddrBits: Int = 64,
51  VAddrBits: Int = 39,
52  HasFPU: Boolean = true,
53  HasVPU: Boolean = false,
54  HasCustomCSRCacheOp: Boolean = true,
55  FetchWidth: Int = 8,
56  AsidLength: Int = 16,
57  EnableBPU: Boolean = true,
58  EnableBPD: Boolean = true,
59  EnableRAS: Boolean = true,
60  EnableLB: Boolean = false,
61  EnableLoop: Boolean = true,
62  EnableSC: Boolean = true,
63  EnbaleTlbDebug: Boolean = false,
64  EnableJal: Boolean = false,
65  EnableFauFTB: Boolean = true,
66  UbtbGHRLength: Int = 4,
67  // HistoryLength: Int = 512,
68  EnableGHistDiff: Boolean = true,
69  UbtbSize: Int = 256,
70  FtbSize: Int = 2048,
71  RasSize: Int = 32,
72  CacheLineSize: Int = 512,
73  FtbWays: Int = 4,
74  TageTableInfos: Seq[Tuple3[Int,Int,Int]] =
75  //       Sets  Hist   Tag
76    // Seq(( 2048,    2,    8),
77    //     ( 2048,    9,    8),
78    //     ( 2048,   13,    8),
79    //     ( 2048,   20,    8),
80    //     ( 2048,   26,    8),
81    //     ( 2048,   44,    8),
82    //     ( 2048,   73,    8),
83    //     ( 2048,  256,    8)),
84    Seq(( 4096,    8,    8),
85        ( 4096,   13,    8),
86        ( 4096,   32,    8),
87        ( 4096,  119,    8)),
88  ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] =
89  //      Sets  Hist   Tag
90    Seq(( 256,    4,    9),
91        ( 256,    8,    9),
92        ( 512,   13,    9),
93        ( 512,   16,    9),
94        ( 512,   32,    9)),
95  SCNRows: Int = 512,
96  SCNTables: Int = 4,
97  SCCtrBits: Int = 6,
98  SCHistLens: Seq[Int] = Seq(0, 4, 10, 16),
99  numBr: Int = 2,
100  branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] =
101    ((resp_in: BranchPredictionResp, p: Parameters) => {
102      val ftb = Module(new FTB()(p))
103      val ubtb =Module(new FauFTB()(p))
104      // val bim = Module(new BIM()(p))
105      val tage = Module(new Tage_SC()(p))
106      val ras = Module(new RAS()(p))
107      val ittage = Module(new ITTage()(p))
108      val preds = Seq(ubtb, tage, ftb, ittage, ras)
109      preds.map(_.io := DontCare)
110
111      // ubtb.io.resp_in(0)  := resp_in
112      // bim.io.resp_in(0)   := ubtb.io.resp
113      // btb.io.resp_in(0)   := bim.io.resp
114      // tage.io.resp_in(0)  := btb.io.resp
115      // loop.io.resp_in(0)  := tage.io.resp
116      ubtb.io.in.bits.resp_in(0) := resp_in
117      tage.io.in.bits.resp_in(0) := ubtb.io.out
118      ftb.io.in.bits.resp_in(0)  := tage.io.out
119      ittage.io.in.bits.resp_in(0)  := ftb.io.out
120      ras.io.in.bits.resp_in(0) := ittage.io.out
121
122      (preds, ras.io.out)
123    }),
124  IBufSize: Int = 48,
125  DecodeWidth: Int = 6,
126  RenameWidth: Int = 6,
127  CommitWidth: Int = 6,
128  FtqSize: Int = 64,
129  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
130  IssQueSize: Int = 16,
131  NRPhyRegs: Int = 192,
132  IntPhyRegs: Int = 192,
133  VfPhyRegs: Int = 192,
134  LoadQueueSize: Int = 80,
135  LoadQueueNWriteBanks: Int = 8,
136  StoreQueueSize: Int = 64,
137  StoreQueueNWriteBanks: Int = 8,
138  VlsQueueSize: Int = 8,
139  RobSize: Int = 256,
140  dpParams: DispatchParameters = DispatchParameters(
141    IntDqSize = 16,
142    FpDqSize = 16,
143    LsDqSize = 16,
144    IntDqDeqWidth = 4,
145    FpDqDeqWidth = 4,
146    LsDqDeqWidth = 4
147  ),
148  exuParameters: ExuParameters = ExuParameters(
149    JmpCnt = 1,
150    AluCnt = 4,
151    MulCnt = 0,
152    MduCnt = 2,
153    FmacCnt = 4,
154    FmiscCnt = 2,
155    FmiscDivSqrtCnt = 0,
156    LduCnt = 2,
157    StuCnt = 2
158  ),
159  LoadPipelineWidth: Int = 2,
160  StorePipelineWidth: Int = 2,
161  VecMemSrcInWidth: Int = 2,
162  VecMemInstWbWidth: Int = 1,
163  VecMemDispatchWidth: Int = 1,
164  StoreBufferSize: Int = 16,
165  StoreBufferThreshold: Int = 7,
166  EnsbufferWidth: Int = 2,
167  UncacheBufferSize: Int = 4,
168  EnableLoadToLoadForward: Boolean = true,
169  EnableFastForward: Boolean = false,
170  EnableLdVioCheckAfterReset: Boolean = true,
171  EnableSoftPrefetchAfterReset: Boolean = true,
172  EnableCacheErrorAfterReset: Boolean = true,
173  EnableAccurateLoadError: Boolean = true,
174  EnableUncacheWriteOutstanding: Boolean = true,
175  MMUAsidLen: Int = 16, // max is 16, 0 is not supported now
176  ReSelectLen: Int = 6, // load replay queue replay select counter len
177  itlbParameters: TLBParameters = TLBParameters(
178    name = "itlb",
179    fetchi = true,
180    useDmode = false,
181    normalNWays = 32,
182    normalReplacer = Some("plru"),
183    superNWays = 4,
184    superReplacer = Some("plru")
185  ),
186  ldtlbParameters: TLBParameters = TLBParameters(
187    name = "ldtlb",
188    normalNSets = 64,
189    normalNWays = 1,
190    normalAssociative = "sa",
191    normalReplacer = Some("setplru"),
192    superNWays = 16,
193    normalAsVictim = true,
194    outReplace = false,
195    partialStaticPMP = true,
196    outsideRecvFlush = true,
197    saveLevel = true
198  ),
199  sttlbParameters: TLBParameters = TLBParameters(
200    name = "sttlb",
201    normalNSets = 64,
202    normalNWays = 1,
203    normalAssociative = "sa",
204    normalReplacer = Some("setplru"),
205    superNWays = 16,
206    normalAsVictim = true,
207    outReplace = false,
208    partialStaticPMP = true,
209    outsideRecvFlush = true,
210    saveLevel = true
211  ),
212  refillBothTlb: Boolean = false,
213  btlbParameters: TLBParameters = TLBParameters(
214    name = "btlb",
215    normalNSets = 1,
216    normalNWays = 64,
217    superNWays = 4,
218  ),
219  l2tlbParameters: L2TLBParameters = L2TLBParameters(),
220  NumPerfCounters: Int = 16,
221  icacheParameters: ICacheParameters = ICacheParameters(
222    tagECC = Some("parity"),
223    dataECC = Some("parity"),
224    replacer = Some("setplru"),
225    nMissEntries = 2,
226    nProbeEntries = 2,
227    nPrefetchEntries = 2,
228    hasPrefetch = true,
229  ),
230  dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters(
231    tagECC = Some("secded"),
232    dataECC = Some("secded"),
233    replacer = Some("setplru"),
234    nMissEntries = 16,
235    nProbeEntries = 8,
236    nReleaseEntries = 18
237  )),
238  L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
239    name = "l2",
240    level = 2,
241    ways = 8,
242    sets = 1024, // default 512KB L2
243    prefetch = Some(huancun.prefetch.BOPParameters())
244  )),
245  L2NBanks: Int = 1,
246  usePTWRepeater: Boolean = false,
247  softPTW: Boolean = false // dpi-c debug only
248){
249  val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength
250  val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now
251
252  val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
253  val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg)
254
255  val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++
256    Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg)
257
258  val fpExuConfigs =
259    Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++
260      Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg)
261
262  val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs
263}
264
265case object DebugOptionsKey extends Field[DebugOptions]
266
267case class DebugOptions
268(
269  FPGAPlatform: Boolean = false,
270  EnableDifftest: Boolean = false,
271  AlwaysBasicDiff: Boolean = true,
272  EnableDebug: Boolean = false,
273  EnablePerfDebug: Boolean = true,
274  UseDRAMSim: Boolean = false,
275  EnableTopDown: Boolean = false
276)
277
278trait HasXSParameter {
279
280  implicit val p: Parameters
281
282  val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits
283
284  val coreParams = p(XSCoreParamsKey)
285  val env = p(DebugOptionsKey)
286
287  val XLEN = coreParams.XLEN
288  val VLEN = coreParams.VLEN
289  val minFLen = 32
290  val fLen = 64
291  def xLen = XLEN
292
293  val HasMExtension = coreParams.HasMExtension
294  val HasCExtension = coreParams.HasCExtension
295  val HasDiv = coreParams.HasDiv
296  val HasIcache = coreParams.HasICache
297  val HasDcache = coreParams.HasDCache
298  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
299  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
300  val AsidLength = coreParams.AsidLength
301  val ReSelectLen = coreParams.ReSelectLen
302  val AddrBytes = AddrBits / 8 // unused
303  val DataBits = XLEN
304  val DataBytes = DataBits / 8
305  val HasFPU = coreParams.HasFPU
306  val HasVPU = coreParams.HasVPU
307  val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp
308  val FetchWidth = coreParams.FetchWidth
309  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
310  val EnableBPU = coreParams.EnableBPU
311  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
312  val EnableRAS = coreParams.EnableRAS
313  val EnableLB = coreParams.EnableLB
314  val EnableLoop = coreParams.EnableLoop
315  val EnableSC = coreParams.EnableSC
316  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
317  val HistoryLength = coreParams.HistoryLength
318  val EnableGHistDiff = coreParams.EnableGHistDiff
319  val UbtbGHRLength = coreParams.UbtbGHRLength
320  val UbtbSize = coreParams.UbtbSize
321  val EnableFauFTB = coreParams.EnableFauFTB
322  val FtbSize = coreParams.FtbSize
323  val FtbWays = coreParams.FtbWays
324  val RasSize = coreParams.RasSize
325
326  def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = {
327    coreParams.branchPredictor(resp_in, p)
328  }
329  val numBr = coreParams.numBr
330  val TageTableInfos = coreParams.TageTableInfos
331  val TageBanks = coreParams.numBr
332  val SCNRows = coreParams.SCNRows
333  val SCCtrBits = coreParams.SCCtrBits
334  val SCHistLens = coreParams.SCHistLens
335  val SCNTables = coreParams.SCNTables
336
337  val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map {
338    case ((n, cb), h) => (n, cb, h)
339  }
340  val ITTageTableInfos = coreParams.ITTageTableInfos
341  type FoldedHistoryInfo = Tuple2[Int, Int]
342  val foldedGHistInfos =
343    (TageTableInfos.map{ case (nRows, h, t) =>
344      if (h > 0)
345        Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1)))
346      else
347        Set[FoldedHistoryInfo]()
348    }.reduce(_++_).toSet ++
349    SCTableInfos.map{ case (nRows, _, h) =>
350      if (h > 0)
351        Set((h, min(log2Ceil(nRows/TageBanks), h)))
352      else
353        Set[FoldedHistoryInfo]()
354    }.reduce(_++_).toSet ++
355    ITTageTableInfos.map{ case (nRows, h, t) =>
356      if (h > 0)
357        Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1)))
358      else
359        Set[FoldedHistoryInfo]()
360    }.reduce(_++_) ++
361      Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize)))
362    ).toList
363
364
365
366  val CacheLineSize = coreParams.CacheLineSize
367  val CacheLineHalfWord = CacheLineSize / 16
368  val ExtHistoryLength = HistoryLength + 64
369  val IBufSize = coreParams.IBufSize
370  val DecodeWidth = coreParams.DecodeWidth
371  val RenameWidth = coreParams.RenameWidth
372  val CommitWidth = coreParams.CommitWidth
373  val FtqSize = coreParams.FtqSize
374  val IssQueSize = coreParams.IssQueSize
375  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
376  val NRPhyRegs = coreParams.NRPhyRegs
377  val PhyRegIdxWidth = log2Up(NRPhyRegs)
378  val IntPhyRegs = coreParams.IntPhyRegs
379  val VfPhyRegs = coreParams.VfPhyRegs
380  val IntPregIdxWidth = log2Up(IntPhyRegs)
381  val VfPregIdxWidth = log2Up(VfPhyRegs)
382  val RobSize = coreParams.RobSize
383  val IntRefCounterWidth = log2Ceil(RobSize)
384  val LoadQueueSize = coreParams.LoadQueueSize
385  val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks
386  val StoreQueueSize = coreParams.StoreQueueSize
387  val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks
388  val VlsQueueSize = coreParams.VlsQueueSize
389  val dpParams = coreParams.dpParams
390  val exuParameters = coreParams.exuParameters
391  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
392  val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts
393  val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt
394  val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt
395  val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt
396  val LoadPipelineWidth = coreParams.LoadPipelineWidth
397  val StorePipelineWidth = coreParams.StorePipelineWidth
398  val VecMemSrcInWidth = coreParams.VecMemSrcInWidth
399  val VecMemInstWbWidth = coreParams.VecMemInstWbWidth
400  val VecMemDispatchWidth = coreParams.VecMemDispatchWidth
401  val StoreBufferSize = coreParams.StoreBufferSize
402  val StoreBufferThreshold = coreParams.StoreBufferThreshold
403  val EnsbufferWidth = coreParams.EnsbufferWidth
404  val UncacheBufferSize = coreParams.UncacheBufferSize
405  val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward
406  val EnableFastForward = coreParams.EnableFastForward
407  val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset
408  val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset
409  val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset
410  val EnableAccurateLoadError = coreParams.EnableAccurateLoadError
411  val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding
412  val asidLen = coreParams.MMUAsidLen
413  val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
414  val refillBothTlb = coreParams.refillBothTlb
415  val itlbParams = coreParams.itlbParameters
416  val ldtlbParams = coreParams.ldtlbParameters
417  val sttlbParams = coreParams.sttlbParameters
418  val btlbParams = coreParams.btlbParameters
419  val l2tlbParams = coreParams.l2tlbParameters
420  val NumPerfCounters = coreParams.NumPerfCounters
421
422  val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 +
423              (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 +  + (exuParameters.FmiscCnt+1)/2 +
424              (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 +
425              (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2
426
427  val instBytes = if (HasCExtension) 2 else 4
428  val instOffsetBits = log2Ceil(instBytes)
429
430  val icacheParameters = coreParams.icacheParameters
431  val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters())
432
433  // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles
434  // for constrained LR/SC loop
435  val LRSCCycles = 64
436  // for lr storm
437  val LRSCBackOff = 8
438
439  // cache hierarchy configurations
440  val l1BusDataWidth = 256
441
442  // load violation predict
443  val ResetTimeMax2Pow = 20 //1078576
444  val ResetTimeMin2Pow = 10 //1024
445  // wait table parameters
446  val WaitTableSize = 1024
447  val MemPredPCWidth = log2Up(WaitTableSize)
448  val LWTUse2BitCounter = true
449  // store set parameters
450  val SSITSize = WaitTableSize
451  val LFSTSize = 32
452  val SSIDWidth = log2Up(LFSTSize)
453  val LFSTWidth = 4
454  val StoreSetEnable = true // LWT will be disabled if SS is enabled
455
456  val loadExuConfigs = coreParams.loadExuConfigs
457  val storeExuConfigs = coreParams.storeExuConfigs
458
459  val intExuConfigs = coreParams.intExuConfigs
460
461  val fpExuConfigs = coreParams.fpExuConfigs
462
463  val exuConfigs = coreParams.exuConfigs
464
465  val PCntIncrStep: Int = 6
466  val numPCntHc: Int = 25
467  val numPCntPtw: Int = 19
468
469  val numCSRPCntFrontend = 8
470  val numCSRPCntCtrl     = 8
471  val numCSRPCntLsu      = 8
472  val numCSRPCntHc       = 5
473}
474