1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 VLEN: Int = 128, 45 HasMExtension: Boolean = true, 46 HasCExtension: Boolean = true, 47 HasDiv: Boolean = true, 48 HasICache: Boolean = true, 49 HasDCache: Boolean = true, 50 AddrBits: Int = 64, 51 VAddrBits: Int = 39, 52 HasFPU: Boolean = true, 53 HasVPU: Boolean = false, 54 HasCustomCSRCacheOp: Boolean = true, 55 FetchWidth: Int = 8, 56 AsidLength: Int = 16, 57 EnableBPU: Boolean = true, 58 EnableBPD: Boolean = true, 59 EnableRAS: Boolean = true, 60 EnableLB: Boolean = false, 61 EnableLoop: Boolean = true, 62 EnableSC: Boolean = true, 63 EnbaleTlbDebug: Boolean = false, 64 EnableJal: Boolean = false, 65 EnableFauFTB: Boolean = true, 66 UbtbGHRLength: Int = 4, 67 // HistoryLength: Int = 512, 68 EnableGHistDiff: Boolean = true, 69 UbtbSize: Int = 256, 70 FtbSize: Int = 2048, 71 RasSize: Int = 32, 72 CacheLineSize: Int = 512, 73 FtbWays: Int = 4, 74 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 75 // Sets Hist Tag 76 // Seq(( 2048, 2, 8), 77 // ( 2048, 9, 8), 78 // ( 2048, 13, 8), 79 // ( 2048, 20, 8), 80 // ( 2048, 26, 8), 81 // ( 2048, 44, 8), 82 // ( 2048, 73, 8), 83 // ( 2048, 256, 8)), 84 Seq(( 4096, 8, 8), 85 ( 4096, 13, 8), 86 ( 4096, 32, 8), 87 ( 4096, 119, 8)), 88 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 89 // Sets Hist Tag 90 Seq(( 256, 4, 9), 91 ( 256, 8, 9), 92 ( 512, 13, 9), 93 ( 512, 16, 9), 94 ( 512, 32, 9)), 95 SCNRows: Int = 512, 96 SCNTables: Int = 4, 97 SCCtrBits: Int = 6, 98 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 99 numBr: Int = 2, 100 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 101 ((resp_in: BranchPredictionResp, p: Parameters) => { 102 val ftb = Module(new FTB()(p)) 103 val ubtb =Module(new FauFTB()(p)) 104 // val bim = Module(new BIM()(p)) 105 val tage = Module(new Tage_SC()(p)) 106 val ras = Module(new RAS()(p)) 107 val ittage = Module(new ITTage()(p)) 108 val preds = Seq(ubtb, tage, ftb, ittage, ras) 109 preds.map(_.io := DontCare) 110 111 // ubtb.io.resp_in(0) := resp_in 112 // bim.io.resp_in(0) := ubtb.io.resp 113 // btb.io.resp_in(0) := bim.io.resp 114 // tage.io.resp_in(0) := btb.io.resp 115 // loop.io.resp_in(0) := tage.io.resp 116 ubtb.io.in.bits.resp_in(0) := resp_in 117 tage.io.in.bits.resp_in(0) := ubtb.io.out 118 ftb.io.in.bits.resp_in(0) := tage.io.out 119 ittage.io.in.bits.resp_in(0) := ftb.io.out 120 ras.io.in.bits.resp_in(0) := ittage.io.out 121 122 (preds, ras.io.out) 123 }), 124 IBufSize: Int = 48, 125 DecodeWidth: Int = 6, 126 RenameWidth: Int = 6, 127 CommitWidth: Int = 6, 128 FtqSize: Int = 64, 129 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 130 IssQueSize: Int = 16, 131 NRPhyRegs: Int = 192, 132 LoadQueueSize: Int = 80, 133 LoadQueueNWriteBanks: Int = 8, 134 StoreQueueSize: Int = 64, 135 StoreQueueNWriteBanks: Int = 8, 136 VlsQueueSize: Int = 8, 137 RobSize: Int = 256, 138 dpParams: DispatchParameters = DispatchParameters( 139 IntDqSize = 16, 140 FpDqSize = 16, 141 LsDqSize = 16, 142 IntDqDeqWidth = 4, 143 FpDqDeqWidth = 4, 144 LsDqDeqWidth = 4 145 ), 146 exuParameters: ExuParameters = ExuParameters( 147 JmpCnt = 1, 148 AluCnt = 4, 149 MulCnt = 0, 150 MduCnt = 2, 151 FmacCnt = 4, 152 FmiscCnt = 2, 153 FmiscDivSqrtCnt = 0, 154 LduCnt = 2, 155 StuCnt = 2 156 ), 157 LoadPipelineWidth: Int = 2, 158 StorePipelineWidth: Int = 2, 159 VecMemSrcInWidth: Int = 2, 160 VecMemInstWbWidth: Int = 1, 161 VecMemDispatchWidth: Int = 1, 162 StoreBufferSize: Int = 16, 163 StoreBufferThreshold: Int = 7, 164 EnsbufferWidth: Int = 2, 165 UncacheBufferSize: Int = 4, 166 EnableLoadToLoadForward: Boolean = true, 167 EnableFastForward: Boolean = false, 168 EnableLdVioCheckAfterReset: Boolean = true, 169 EnableSoftPrefetchAfterReset: Boolean = true, 170 EnableCacheErrorAfterReset: Boolean = true, 171 EnableAccurateLoadError: Boolean = true, 172 EnableUncacheWriteOutstanding: Boolean = true, 173 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 174 ReSelectLen: Int = 6, // load replay queue replay select counter len 175 itlbParameters: TLBParameters = TLBParameters( 176 name = "itlb", 177 fetchi = true, 178 useDmode = false, 179 normalNWays = 32, 180 normalReplacer = Some("plru"), 181 superNWays = 4, 182 superReplacer = Some("plru") 183 ), 184 ldtlbParameters: TLBParameters = TLBParameters( 185 name = "ldtlb", 186 normalNSets = 64, 187 normalNWays = 1, 188 normalAssociative = "sa", 189 normalReplacer = Some("setplru"), 190 superNWays = 16, 191 normalAsVictim = true, 192 outReplace = false, 193 partialStaticPMP = true, 194 outsideRecvFlush = true, 195 saveLevel = true 196 ), 197 sttlbParameters: TLBParameters = TLBParameters( 198 name = "sttlb", 199 normalNSets = 64, 200 normalNWays = 1, 201 normalAssociative = "sa", 202 normalReplacer = Some("setplru"), 203 superNWays = 16, 204 normalAsVictim = true, 205 outReplace = false, 206 partialStaticPMP = true, 207 outsideRecvFlush = true, 208 saveLevel = true 209 ), 210 refillBothTlb: Boolean = false, 211 btlbParameters: TLBParameters = TLBParameters( 212 name = "btlb", 213 normalNSets = 1, 214 normalNWays = 64, 215 superNWays = 4, 216 ), 217 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 218 NumPerfCounters: Int = 16, 219 icacheParameters: ICacheParameters = ICacheParameters( 220 tagECC = Some("parity"), 221 dataECC = Some("parity"), 222 replacer = Some("setplru"), 223 nMissEntries = 2, 224 nProbeEntries = 2, 225 nPrefetchEntries = 2, 226 hasPrefetch = true, 227 ), 228 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 229 tagECC = Some("secded"), 230 dataECC = Some("secded"), 231 replacer = Some("setplru"), 232 nMissEntries = 16, 233 nProbeEntries = 8, 234 nReleaseEntries = 18 235 )), 236 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 237 name = "l2", 238 level = 2, 239 ways = 8, 240 sets = 1024, // default 512KB L2 241 prefetch = Some(huancun.prefetch.BOPParameters()) 242 )), 243 L2NBanks: Int = 1, 244 usePTWRepeater: Boolean = false, 245 softPTW: Boolean = false // dpi-c debug only 246){ 247 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 248 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 249 250 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 251 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 252 253 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 254 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 255 256 val fpExuConfigs = 257 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 258 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 259 260 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 261} 262 263case object DebugOptionsKey extends Field[DebugOptions] 264 265case class DebugOptions 266( 267 FPGAPlatform: Boolean = false, 268 EnableDifftest: Boolean = false, 269 AlwaysBasicDiff: Boolean = true, 270 EnableDebug: Boolean = false, 271 EnablePerfDebug: Boolean = true, 272 UseDRAMSim: Boolean = false, 273 EnableTopDown: Boolean = false 274) 275 276trait HasXSParameter { 277 278 implicit val p: Parameters 279 280 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 281 282 val coreParams = p(XSCoreParamsKey) 283 val env = p(DebugOptionsKey) 284 285 val XLEN = coreParams.XLEN 286 val VLEN = coreParams.VLEN 287 val minFLen = 32 288 val fLen = 64 289 def xLen = XLEN 290 291 val HasMExtension = coreParams.HasMExtension 292 val HasCExtension = coreParams.HasCExtension 293 val HasDiv = coreParams.HasDiv 294 val HasIcache = coreParams.HasICache 295 val HasDcache = coreParams.HasDCache 296 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 297 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 298 val AsidLength = coreParams.AsidLength 299 val ReSelectLen = coreParams.ReSelectLen 300 val AddrBytes = AddrBits / 8 // unused 301 val DataBits = XLEN 302 val DataBytes = DataBits / 8 303 val HasFPU = coreParams.HasFPU 304 val HasVPU = coreParams.HasVPU 305 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 306 val FetchWidth = coreParams.FetchWidth 307 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 308 val EnableBPU = coreParams.EnableBPU 309 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 310 val EnableRAS = coreParams.EnableRAS 311 val EnableLB = coreParams.EnableLB 312 val EnableLoop = coreParams.EnableLoop 313 val EnableSC = coreParams.EnableSC 314 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 315 val HistoryLength = coreParams.HistoryLength 316 val EnableGHistDiff = coreParams.EnableGHistDiff 317 val UbtbGHRLength = coreParams.UbtbGHRLength 318 val UbtbSize = coreParams.UbtbSize 319 val EnableFauFTB = coreParams.EnableFauFTB 320 val FtbSize = coreParams.FtbSize 321 val FtbWays = coreParams.FtbWays 322 val RasSize = coreParams.RasSize 323 324 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 325 coreParams.branchPredictor(resp_in, p) 326 } 327 val numBr = coreParams.numBr 328 val TageTableInfos = coreParams.TageTableInfos 329 val TageBanks = coreParams.numBr 330 val SCNRows = coreParams.SCNRows 331 val SCCtrBits = coreParams.SCCtrBits 332 val SCHistLens = coreParams.SCHistLens 333 val SCNTables = coreParams.SCNTables 334 335 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 336 case ((n, cb), h) => (n, cb, h) 337 } 338 val ITTageTableInfos = coreParams.ITTageTableInfos 339 type FoldedHistoryInfo = Tuple2[Int, Int] 340 val foldedGHistInfos = 341 (TageTableInfos.map{ case (nRows, h, t) => 342 if (h > 0) 343 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 344 else 345 Set[FoldedHistoryInfo]() 346 }.reduce(_++_).toSet ++ 347 SCTableInfos.map{ case (nRows, _, h) => 348 if (h > 0) 349 Set((h, min(log2Ceil(nRows/TageBanks), h))) 350 else 351 Set[FoldedHistoryInfo]() 352 }.reduce(_++_).toSet ++ 353 ITTageTableInfos.map{ case (nRows, h, t) => 354 if (h > 0) 355 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 356 else 357 Set[FoldedHistoryInfo]() 358 }.reduce(_++_) ++ 359 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 360 ).toList 361 362 363 364 val CacheLineSize = coreParams.CacheLineSize 365 val CacheLineHalfWord = CacheLineSize / 16 366 val ExtHistoryLength = HistoryLength + 64 367 val IBufSize = coreParams.IBufSize 368 val DecodeWidth = coreParams.DecodeWidth 369 val RenameWidth = coreParams.RenameWidth 370 val CommitWidth = coreParams.CommitWidth 371 val FtqSize = coreParams.FtqSize 372 val IssQueSize = coreParams.IssQueSize 373 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 374 val NRPhyRegs = coreParams.NRPhyRegs 375 val PhyRegIdxWidth = log2Up(NRPhyRegs) 376 val RobSize = coreParams.RobSize 377 val IntRefCounterWidth = log2Ceil(RobSize) 378 val LoadQueueSize = coreParams.LoadQueueSize 379 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 380 val StoreQueueSize = coreParams.StoreQueueSize 381 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 382 val VlsQueueSize = coreParams.VlsQueueSize 383 val dpParams = coreParams.dpParams 384 val exuParameters = coreParams.exuParameters 385 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 386 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 387 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 388 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 389 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 390 val LoadPipelineWidth = coreParams.LoadPipelineWidth 391 val StorePipelineWidth = coreParams.StorePipelineWidth 392 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 393 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 394 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 395 val StoreBufferSize = coreParams.StoreBufferSize 396 val StoreBufferThreshold = coreParams.StoreBufferThreshold 397 val EnsbufferWidth = coreParams.EnsbufferWidth 398 val UncacheBufferSize = coreParams.UncacheBufferSize 399 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 400 val EnableFastForward = coreParams.EnableFastForward 401 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 402 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 403 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 404 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 405 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 406 val asidLen = coreParams.MMUAsidLen 407 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 408 val refillBothTlb = coreParams.refillBothTlb 409 val itlbParams = coreParams.itlbParameters 410 val ldtlbParams = coreParams.ldtlbParameters 411 val sttlbParams = coreParams.sttlbParameters 412 val btlbParams = coreParams.btlbParameters 413 val l2tlbParams = coreParams.l2tlbParameters 414 val NumPerfCounters = coreParams.NumPerfCounters 415 416 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 417 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 418 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 419 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 420 421 val instBytes = if (HasCExtension) 2 else 4 422 val instOffsetBits = log2Ceil(instBytes) 423 424 val icacheParameters = coreParams.icacheParameters 425 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 426 427 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 428 // for constrained LR/SC loop 429 val LRSCCycles = 64 430 // for lr storm 431 val LRSCBackOff = 8 432 433 // cache hierarchy configurations 434 val l1BusDataWidth = 256 435 436 // load violation predict 437 val ResetTimeMax2Pow = 20 //1078576 438 val ResetTimeMin2Pow = 10 //1024 439 // wait table parameters 440 val WaitTableSize = 1024 441 val MemPredPCWidth = log2Up(WaitTableSize) 442 val LWTUse2BitCounter = true 443 // store set parameters 444 val SSITSize = WaitTableSize 445 val LFSTSize = 32 446 val SSIDWidth = log2Up(LFSTSize) 447 val LFSTWidth = 4 448 val StoreSetEnable = true // LWT will be disabled if SS is enabled 449 450 val loadExuConfigs = coreParams.loadExuConfigs 451 val storeExuConfigs = coreParams.storeExuConfigs 452 453 val intExuConfigs = coreParams.intExuConfigs 454 455 val fpExuConfigs = coreParams.fpExuConfigs 456 457 val exuConfigs = coreParams.exuConfigs 458 459 val PCntIncrStep: Int = 6 460 val numPCntHc: Int = 25 461 val numPCntPtw: Int = 19 462 463 val numCSRPCntFrontend = 8 464 val numCSRPCntCtrl = 8 465 val numCSRPCntLsu = 8 466 val numCSRPCntHc = 5 467} 468