1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasVPU: Boolean = false, 53 HasCustomCSRCacheOp: Boolean = true, 54 FetchWidth: Int = 8, 55 AsidLength: Int = 16, 56 EnableBPU: Boolean = true, 57 EnableBPD: Boolean = true, 58 EnableRAS: Boolean = true, 59 EnableLB: Boolean = false, 60 EnableLoop: Boolean = true, 61 EnableSC: Boolean = true, 62 EnbaleTlbDebug: Boolean = false, 63 EnableJal: Boolean = false, 64 EnableUBTB: Boolean = true, 65 UbtbGHRLength: Int = 4, 66 // HistoryLength: Int = 512, 67 EnableGHistDiff: Boolean = true, 68 UbtbSize: Int = 256, 69 FtbSize: Int = 2048, 70 RasSize: Int = 32, 71 CacheLineSize: Int = 512, 72 FtbWays: Int = 4, 73 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 74 // Sets Hist Tag 75 // Seq(( 2048, 2, 8), 76 // ( 2048, 9, 8), 77 // ( 2048, 13, 8), 78 // ( 2048, 20, 8), 79 // ( 2048, 26, 8), 80 // ( 2048, 44, 8), 81 // ( 2048, 73, 8), 82 // ( 2048, 256, 8)), 83 Seq(( 4096, 8, 8), 84 ( 4096, 13, 8), 85 ( 4096, 32, 8), 86 ( 4096, 119, 8)), 87 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 88 // Sets Hist Tag 89 Seq(( 256, 4, 9), 90 ( 256, 8, 9), 91 ( 512, 13, 9), 92 ( 512, 16, 9), 93 ( 512, 32, 9)), 94 SCNRows: Int = 512, 95 SCNTables: Int = 4, 96 SCCtrBits: Int = 6, 97 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 98 numBr: Int = 2, 99 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 100 ((resp_in: BranchPredictionResp, p: Parameters) => { 101 // val loop = Module(new LoopPredictor) 102 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 103 // else Module(new Tage) } 104 // else { Module(new FakeTage) }) 105 val ftb = Module(new FTB()(p)) 106 val ubtb = Module(new MicroBTB()(p)) 107 // val bim = Module(new BIM()(p)) 108 val tage = Module(new Tage_SC()(p)) 109 val ras = Module(new RAS()(p)) 110 val ittage = Module(new ITTage()(p)) 111 // val tage = Module(new Tage()(p)) 112 // val fake = Module(new FakePredictor()(p)) 113 114 // val preds = Seq(loop, tage, btb, ubtb, bim) 115 val preds = Seq(ubtb, tage, ftb, ittage, ras) 116 preds.map(_.io := DontCare) 117 118 // ubtb.io.resp_in(0) := resp_in 119 // bim.io.resp_in(0) := ubtb.io.resp 120 // btb.io.resp_in(0) := bim.io.resp 121 // tage.io.resp_in(0) := btb.io.resp 122 // loop.io.resp_in(0) := tage.io.resp 123 ubtb.io.in.bits.resp_in(0) := resp_in 124 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 125 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 126 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 127 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 128 129 (preds, ras.io.out.resp) 130 }), 131 IBufSize: Int = 48, 132 DecodeWidth: Int = 6, 133 RenameWidth: Int = 6, 134 CommitWidth: Int = 6, 135 FtqSize: Int = 64, 136 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 137 IssQueSize: Int = 16, 138 NRPhyRegs: Int = 192, 139 LoadQueueSize: Int = 80, 140 StoreQueueSize: Int = 64, 141 RobSize: Int = 256, 142 dpParams: DispatchParameters = DispatchParameters( 143 IntDqSize = 16, 144 FpDqSize = 16, 145 LsDqSize = 16, 146 IntDqDeqWidth = 4, 147 FpDqDeqWidth = 4, 148 LsDqDeqWidth = 4 149 ), 150 exuParameters: ExuParameters = ExuParameters( 151 JmpCnt = 1, 152 AluCnt = 4, 153 MulCnt = 0, 154 MduCnt = 2, 155 FmacCnt = 4, 156 FmiscCnt = 2, 157 FmiscDivSqrtCnt = 0, 158 LduCnt = 2, 159 StuCnt = 2 160 ), 161 LoadPipelineWidth: Int = 2, 162 StorePipelineWidth: Int = 2, 163 StoreBufferSize: Int = 16, 164 StoreBufferThreshold: Int = 7, 165 EnsbufferWidth: Int = 2, 166 EnableLoadToLoadForward: Boolean = true, 167 EnableFastForward: Boolean = false, 168 EnableLdVioCheckAfterReset: Boolean = true, 169 EnableSoftPrefetchAfterReset: Boolean = true, 170 EnableCacheErrorAfterReset: Boolean = true, 171 EnableAccurateLoadError: Boolean = true, 172 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 173 itlbParameters: TLBParameters = TLBParameters( 174 name = "itlb", 175 fetchi = true, 176 useDmode = false, 177 normalNWays = 32, 178 normalReplacer = Some("plru"), 179 superNWays = 4, 180 superReplacer = Some("plru") 181 ), 182 ldtlbParameters: TLBParameters = TLBParameters( 183 name = "ldtlb", 184 normalNSets = 64, 185 normalNWays = 1, 186 normalAssociative = "sa", 187 normalReplacer = Some("setplru"), 188 superNWays = 16, 189 normalAsVictim = true, 190 outReplace = false, 191 partialStaticPMP = true, 192 outsideRecvFlush = true, 193 saveLevel = true 194 ), 195 sttlbParameters: TLBParameters = TLBParameters( 196 name = "sttlb", 197 normalNSets = 64, 198 normalNWays = 1, 199 normalAssociative = "sa", 200 normalReplacer = Some("setplru"), 201 superNWays = 16, 202 normalAsVictim = true, 203 outReplace = false, 204 partialStaticPMP = true, 205 outsideRecvFlush = true, 206 saveLevel = true 207 ), 208 refillBothTlb: Boolean = false, 209 btlbParameters: TLBParameters = TLBParameters( 210 name = "btlb", 211 normalNSets = 1, 212 normalNWays = 64, 213 superNWays = 4, 214 ), 215 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 216 NumPerfCounters: Int = 16, 217 icacheParameters: ICacheParameters = ICacheParameters( 218 tagECC = Some("parity"), 219 dataECC = Some("parity"), 220 replacer = Some("setplru"), 221 nMissEntries = 2, 222 nProbeEntries = 2, 223 nPrefetchEntries = 2, 224 hasPrefetch = true, 225 ), 226 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 227 tagECC = Some("secded"), 228 dataECC = Some("secded"), 229 replacer = Some("setplru"), 230 nMissEntries = 16, 231 nProbeEntries = 8, 232 nReleaseEntries = 18 233 )), 234 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 235 name = "l2", 236 level = 2, 237 ways = 8, 238 sets = 1024, // default 512KB L2 239 prefetch = Some(huancun.prefetch.BOPParameters()) 240 )), 241 L2NBanks: Int = 1, 242 usePTWRepeater: Boolean = false, 243 softPTW: Boolean = false // dpi-c debug only 244){ 245 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 246 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 247 248 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 249 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 250 251 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 252 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 253 254 val fpExuConfigs = 255 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 256 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 257 258 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 259} 260 261case object DebugOptionsKey extends Field[DebugOptions] 262 263case class DebugOptions 264( 265 FPGAPlatform: Boolean = false, 266 EnableDifftest: Boolean = false, 267 AlwaysBasicDiff: Boolean = true, 268 EnableDebug: Boolean = false, 269 EnablePerfDebug: Boolean = true, 270 UseDRAMSim: Boolean = false 271) 272 273trait HasXSParameter { 274 275 implicit val p: Parameters 276 277 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 278 279 val coreParams = p(XSCoreParamsKey) 280 val env = p(DebugOptionsKey) 281 282 val XLEN = coreParams.XLEN 283 val minFLen = 32 284 val fLen = 64 285 def xLen = XLEN 286 287 val HasMExtension = coreParams.HasMExtension 288 val HasCExtension = coreParams.HasCExtension 289 val HasDiv = coreParams.HasDiv 290 val HasIcache = coreParams.HasICache 291 val HasDcache = coreParams.HasDCache 292 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 293 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 294 val AsidLength = coreParams.AsidLength 295 val AddrBytes = AddrBits / 8 // unused 296 val DataBits = XLEN 297 val DataBytes = DataBits / 8 298 val HasFPU = coreParams.HasFPU 299 val HasVPU = coreParams.HasVPU 300 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 301 val FetchWidth = coreParams.FetchWidth 302 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 303 val EnableBPU = coreParams.EnableBPU 304 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 305 val EnableRAS = coreParams.EnableRAS 306 val EnableLB = coreParams.EnableLB 307 val EnableLoop = coreParams.EnableLoop 308 val EnableSC = coreParams.EnableSC 309 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 310 val HistoryLength = coreParams.HistoryLength 311 val EnableGHistDiff = coreParams.EnableGHistDiff 312 val UbtbGHRLength = coreParams.UbtbGHRLength 313 val UbtbSize = coreParams.UbtbSize 314 val FtbSize = coreParams.FtbSize 315 val FtbWays = coreParams.FtbWays 316 val RasSize = coreParams.RasSize 317 318 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 319 coreParams.branchPredictor(resp_in, p) 320 } 321 val numBr = coreParams.numBr 322 val TageTableInfos = coreParams.TageTableInfos 323 val TageBanks = coreParams.numBr 324 val SCNRows = coreParams.SCNRows 325 val SCCtrBits = coreParams.SCCtrBits 326 val SCHistLens = coreParams.SCHistLens 327 val SCNTables = coreParams.SCNTables 328 329 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 330 case ((n, cb), h) => (n, cb, h) 331 } 332 val ITTageTableInfos = coreParams.ITTageTableInfos 333 type FoldedHistoryInfo = Tuple2[Int, Int] 334 val foldedGHistInfos = 335 (TageTableInfos.map{ case (nRows, h, t) => 336 if (h > 0) 337 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 338 else 339 Set[FoldedHistoryInfo]() 340 }.reduce(_++_).toSet ++ 341 SCTableInfos.map{ case (nRows, _, h) => 342 if (h > 0) 343 Set((h, min(log2Ceil(nRows/TageBanks), h))) 344 else 345 Set[FoldedHistoryInfo]() 346 }.reduce(_++_).toSet ++ 347 ITTageTableInfos.map{ case (nRows, h, t) => 348 if (h > 0) 349 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 350 else 351 Set[FoldedHistoryInfo]() 352 }.reduce(_++_) ++ 353 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 354 ).toList 355 356 357 358 val CacheLineSize = coreParams.CacheLineSize 359 val CacheLineHalfWord = CacheLineSize / 16 360 val ExtHistoryLength = HistoryLength + 64 361 val IBufSize = coreParams.IBufSize 362 val DecodeWidth = coreParams.DecodeWidth 363 val RenameWidth = coreParams.RenameWidth 364 val CommitWidth = coreParams.CommitWidth 365 val FtqSize = coreParams.FtqSize 366 val IssQueSize = coreParams.IssQueSize 367 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 368 val NRPhyRegs = coreParams.NRPhyRegs 369 val PhyRegIdxWidth = log2Up(NRPhyRegs) 370 val RobSize = coreParams.RobSize 371 val IntRefCounterWidth = log2Ceil(RobSize) 372 val LoadQueueSize = coreParams.LoadQueueSize 373 val StoreQueueSize = coreParams.StoreQueueSize 374 val dpParams = coreParams.dpParams 375 val exuParameters = coreParams.exuParameters 376 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 377 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 378 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 379 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 380 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 381 val LoadPipelineWidth = coreParams.LoadPipelineWidth 382 val StorePipelineWidth = coreParams.StorePipelineWidth 383 val StoreBufferSize = coreParams.StoreBufferSize 384 val StoreBufferThreshold = coreParams.StoreBufferThreshold 385 val EnsbufferWidth = coreParams.EnsbufferWidth 386 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 387 val EnableFastForward = coreParams.EnableFastForward 388 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 389 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 390 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 391 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 392 val asidLen = coreParams.MMUAsidLen 393 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 394 val refillBothTlb = coreParams.refillBothTlb 395 val itlbParams = coreParams.itlbParameters 396 val ldtlbParams = coreParams.ldtlbParameters 397 val sttlbParams = coreParams.sttlbParameters 398 val btlbParams = coreParams.btlbParameters 399 val l2tlbParams = coreParams.l2tlbParameters 400 val NumPerfCounters = coreParams.NumPerfCounters 401 402 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 403 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 404 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 405 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 406 407 val instBytes = if (HasCExtension) 2 else 4 408 val instOffsetBits = log2Ceil(instBytes) 409 410 val icacheParameters = coreParams.icacheParameters 411 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 412 413 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 414 // for constrained LR/SC loop 415 val LRSCCycles = 64 416 // for lr storm 417 val LRSCBackOff = 8 418 419 // cache hierarchy configurations 420 val l1BusDataWidth = 256 421 422 // load violation predict 423 val ResetTimeMax2Pow = 20 //1078576 424 val ResetTimeMin2Pow = 10 //1024 425 // wait table parameters 426 val WaitTableSize = 1024 427 val MemPredPCWidth = log2Up(WaitTableSize) 428 val LWTUse2BitCounter = true 429 // store set parameters 430 val SSITSize = WaitTableSize 431 val LFSTSize = 32 432 val SSIDWidth = log2Up(LFSTSize) 433 val LFSTWidth = 4 434 val StoreSetEnable = true // LWT will be disabled if SS is enabled 435 436 val loadExuConfigs = coreParams.loadExuConfigs 437 val storeExuConfigs = coreParams.storeExuConfigs 438 439 val intExuConfigs = coreParams.intExuConfigs 440 441 val fpExuConfigs = coreParams.fpExuConfigs 442 443 val exuConfigs = coreParams.exuConfigs 444 445 val PCntIncrStep: Int = 6 446 val numPCntHc: Int = 25 447 val numPCntPtw: Int = 19 448 449 val numCSRPCntFrontend = 8 450 val numCSRPCntCtrl = 8 451 val numCSRPCntLsu = 8 452 val numCSRPCntHc = 5 453} 454