1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableFauFTB: Boolean = true, 64 UbtbGHRLength: Int = 4, 65 // HistoryLength: Int = 512, 66 EnableGHistDiff: Boolean = true, 67 UbtbSize: Int = 256, 68 FtbSize: Int = 2048, 69 RasSize: Int = 32, 70 CacheLineSize: Int = 512, 71 FtbWays: Int = 4, 72 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 73 // Sets Hist Tag 74 // Seq(( 2048, 2, 8), 75 // ( 2048, 9, 8), 76 // ( 2048, 13, 8), 77 // ( 2048, 20, 8), 78 // ( 2048, 26, 8), 79 // ( 2048, 44, 8), 80 // ( 2048, 73, 8), 81 // ( 2048, 256, 8)), 82 Seq(( 4096, 8, 8), 83 ( 4096, 13, 8), 84 ( 4096, 32, 8), 85 ( 4096, 119, 8)), 86 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 87 // Sets Hist Tag 88 Seq(( 256, 4, 9), 89 ( 256, 8, 9), 90 ( 512, 13, 9), 91 ( 512, 16, 9), 92 ( 512, 32, 9)), 93 SCNRows: Int = 512, 94 SCNTables: Int = 4, 95 SCCtrBits: Int = 6, 96 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 97 numBr: Int = 2, 98 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 99 ((resp_in: BranchPredictionResp, p: Parameters) => { 100 val ftb = Module(new FTB()(p)) 101 val ubtb =Module(new FauFTB()(p)) 102 // val bim = Module(new BIM()(p)) 103 val tage = Module(new Tage_SC()(p)) 104 val ras = Module(new RAS()(p)) 105 val ittage = Module(new ITTage()(p)) 106 val preds = Seq(ubtb, tage, ftb, ittage, ras) 107 preds.map(_.io := DontCare) 108 109 // ubtb.io.resp_in(0) := resp_in 110 // bim.io.resp_in(0) := ubtb.io.resp 111 // btb.io.resp_in(0) := bim.io.resp 112 // tage.io.resp_in(0) := btb.io.resp 113 // loop.io.resp_in(0) := tage.io.resp 114 ubtb.io.in.bits.resp_in(0) := resp_in 115 tage.io.in.bits.resp_in(0) := ubtb.io.out 116 ftb.io.in.bits.resp_in(0) := tage.io.out 117 ittage.io.in.bits.resp_in(0) := ftb.io.out 118 ras.io.in.bits.resp_in(0) := ittage.io.out 119 120 (preds, ras.io.out) 121 }), 122 IBufSize: Int = 48, 123 DecodeWidth: Int = 6, 124 RenameWidth: Int = 6, 125 CommitWidth: Int = 6, 126 FtqSize: Int = 64, 127 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 128 IssQueSize: Int = 16, 129 NRPhyRegs: Int = 192, 130 LoadQueueSize: Int = 80, 131 LoadQueueNWriteBanks: Int = 8, 132 StoreQueueSize: Int = 64, 133 StoreQueueNWriteBanks: Int = 8, 134 RobSize: Int = 256, 135 dpParams: DispatchParameters = DispatchParameters( 136 IntDqSize = 16, 137 FpDqSize = 16, 138 LsDqSize = 16, 139 IntDqDeqWidth = 4, 140 FpDqDeqWidth = 4, 141 LsDqDeqWidth = 4 142 ), 143 exuParameters: ExuParameters = ExuParameters( 144 JmpCnt = 1, 145 AluCnt = 4, 146 MulCnt = 0, 147 MduCnt = 2, 148 FmacCnt = 4, 149 FmiscCnt = 2, 150 FmiscDivSqrtCnt = 0, 151 LduCnt = 2, 152 StuCnt = 2 153 ), 154 LoadPipelineWidth: Int = 2, 155 StorePipelineWidth: Int = 2, 156 StoreBufferSize: Int = 16, 157 StoreBufferThreshold: Int = 7, 158 EnsbufferWidth: Int = 2, 159 EnableLoadToLoadForward: Boolean = true, 160 EnableFastForward: Boolean = false, 161 EnableLdVioCheckAfterReset: Boolean = true, 162 EnableSoftPrefetchAfterReset: Boolean = true, 163 EnableCacheErrorAfterReset: Boolean = true, 164 EnableAccurateLoadError: Boolean = true, 165 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 166 itlbParameters: TLBParameters = TLBParameters( 167 name = "itlb", 168 fetchi = true, 169 useDmode = false, 170 normalNWays = 32, 171 normalReplacer = Some("plru"), 172 superNWays = 4, 173 superReplacer = Some("plru") 174 ), 175 ldtlbParameters: TLBParameters = TLBParameters( 176 name = "ldtlb", 177 normalNSets = 64, 178 normalNWays = 1, 179 normalAssociative = "sa", 180 normalReplacer = Some("setplru"), 181 superNWays = 16, 182 normalAsVictim = true, 183 outReplace = false, 184 partialStaticPMP = true, 185 outsideRecvFlush = true, 186 saveLevel = true 187 ), 188 sttlbParameters: TLBParameters = TLBParameters( 189 name = "sttlb", 190 normalNSets = 64, 191 normalNWays = 1, 192 normalAssociative = "sa", 193 normalReplacer = Some("setplru"), 194 superNWays = 16, 195 normalAsVictim = true, 196 outReplace = false, 197 partialStaticPMP = true, 198 outsideRecvFlush = true, 199 saveLevel = true 200 ), 201 refillBothTlb: Boolean = false, 202 btlbParameters: TLBParameters = TLBParameters( 203 name = "btlb", 204 normalNSets = 1, 205 normalNWays = 64, 206 superNWays = 4, 207 ), 208 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 209 NumPerfCounters: Int = 16, 210 icacheParameters: ICacheParameters = ICacheParameters( 211 tagECC = Some("parity"), 212 dataECC = Some("parity"), 213 replacer = Some("setplru"), 214 nMissEntries = 2, 215 nProbeEntries = 2, 216 nPrefetchEntries = 2, 217 hasPrefetch = true, 218 ), 219 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 220 tagECC = Some("secded"), 221 dataECC = Some("secded"), 222 replacer = Some("setplru"), 223 nMissEntries = 16, 224 nProbeEntries = 8, 225 nReleaseEntries = 18 226 )), 227 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 228 name = "l2", 229 level = 2, 230 ways = 8, 231 sets = 1024, // default 512KB L2 232 prefetch = Some(huancun.prefetch.BOPParameters()) 233 )), 234 L2NBanks: Int = 1, 235 usePTWRepeater: Boolean = false, 236 softPTW: Boolean = false // dpi-c debug only 237){ 238 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 239 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 240 241 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 242 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 243 244 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 245 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 246 247 val fpExuConfigs = 248 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 249 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 250 251 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 252} 253 254case object DebugOptionsKey extends Field[DebugOptions] 255 256case class DebugOptions 257( 258 FPGAPlatform: Boolean = false, 259 EnableDifftest: Boolean = false, 260 AlwaysBasicDiff: Boolean = true, 261 EnableDebug: Boolean = false, 262 EnablePerfDebug: Boolean = true, 263 UseDRAMSim: Boolean = false 264) 265 266trait HasXSParameter { 267 268 implicit val p: Parameters 269 270 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 271 272 val coreParams = p(XSCoreParamsKey) 273 val env = p(DebugOptionsKey) 274 275 val XLEN = coreParams.XLEN 276 val minFLen = 32 277 val fLen = 64 278 def xLen = XLEN 279 280 val HasMExtension = coreParams.HasMExtension 281 val HasCExtension = coreParams.HasCExtension 282 val HasDiv = coreParams.HasDiv 283 val HasIcache = coreParams.HasICache 284 val HasDcache = coreParams.HasDCache 285 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 286 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 287 val AsidLength = coreParams.AsidLength 288 val AddrBytes = AddrBits / 8 // unused 289 val DataBits = XLEN 290 val DataBytes = DataBits / 8 291 val HasFPU = coreParams.HasFPU 292 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 293 val FetchWidth = coreParams.FetchWidth 294 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 295 val EnableBPU = coreParams.EnableBPU 296 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 297 val EnableRAS = coreParams.EnableRAS 298 val EnableLB = coreParams.EnableLB 299 val EnableLoop = coreParams.EnableLoop 300 val EnableSC = coreParams.EnableSC 301 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 302 val HistoryLength = coreParams.HistoryLength 303 val EnableGHistDiff = coreParams.EnableGHistDiff 304 val UbtbGHRLength = coreParams.UbtbGHRLength 305 val UbtbSize = coreParams.UbtbSize 306 val EnableFauFTB = coreParams.EnableFauFTB 307 val FtbSize = coreParams.FtbSize 308 val FtbWays = coreParams.FtbWays 309 val RasSize = coreParams.RasSize 310 311 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 312 coreParams.branchPredictor(resp_in, p) 313 } 314 val numBr = coreParams.numBr 315 val TageTableInfos = coreParams.TageTableInfos 316 val TageBanks = coreParams.numBr 317 val SCNRows = coreParams.SCNRows 318 val SCCtrBits = coreParams.SCCtrBits 319 val SCHistLens = coreParams.SCHistLens 320 val SCNTables = coreParams.SCNTables 321 322 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 323 case ((n, cb), h) => (n, cb, h) 324 } 325 val ITTageTableInfos = coreParams.ITTageTableInfos 326 type FoldedHistoryInfo = Tuple2[Int, Int] 327 val foldedGHistInfos = 328 (TageTableInfos.map{ case (nRows, h, t) => 329 if (h > 0) 330 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 331 else 332 Set[FoldedHistoryInfo]() 333 }.reduce(_++_).toSet ++ 334 SCTableInfos.map{ case (nRows, _, h) => 335 if (h > 0) 336 Set((h, min(log2Ceil(nRows/TageBanks), h))) 337 else 338 Set[FoldedHistoryInfo]() 339 }.reduce(_++_).toSet ++ 340 ITTageTableInfos.map{ case (nRows, h, t) => 341 if (h > 0) 342 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 343 else 344 Set[FoldedHistoryInfo]() 345 }.reduce(_++_) ++ 346 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 347 ).toList 348 349 350 351 val CacheLineSize = coreParams.CacheLineSize 352 val CacheLineHalfWord = CacheLineSize / 16 353 val ExtHistoryLength = HistoryLength + 64 354 val IBufSize = coreParams.IBufSize 355 val DecodeWidth = coreParams.DecodeWidth 356 val RenameWidth = coreParams.RenameWidth 357 val CommitWidth = coreParams.CommitWidth 358 val FtqSize = coreParams.FtqSize 359 val IssQueSize = coreParams.IssQueSize 360 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 361 val NRPhyRegs = coreParams.NRPhyRegs 362 val PhyRegIdxWidth = log2Up(NRPhyRegs) 363 val RobSize = coreParams.RobSize 364 val IntRefCounterWidth = log2Ceil(RobSize) 365 val LoadQueueSize = coreParams.LoadQueueSize 366 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 367 val StoreQueueSize = coreParams.StoreQueueSize 368 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 369 val dpParams = coreParams.dpParams 370 val exuParameters = coreParams.exuParameters 371 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 372 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 373 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 374 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 375 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 376 val LoadPipelineWidth = coreParams.LoadPipelineWidth 377 val StorePipelineWidth = coreParams.StorePipelineWidth 378 val StoreBufferSize = coreParams.StoreBufferSize 379 val StoreBufferThreshold = coreParams.StoreBufferThreshold 380 val EnsbufferWidth = coreParams.EnsbufferWidth 381 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 382 val EnableFastForward = coreParams.EnableFastForward 383 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 384 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 385 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 386 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 387 val asidLen = coreParams.MMUAsidLen 388 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 389 val refillBothTlb = coreParams.refillBothTlb 390 val itlbParams = coreParams.itlbParameters 391 val ldtlbParams = coreParams.ldtlbParameters 392 val sttlbParams = coreParams.sttlbParameters 393 val btlbParams = coreParams.btlbParameters 394 val l2tlbParams = coreParams.l2tlbParameters 395 val NumPerfCounters = coreParams.NumPerfCounters 396 397 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 398 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 399 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 400 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 401 402 val instBytes = if (HasCExtension) 2 else 4 403 val instOffsetBits = log2Ceil(instBytes) 404 405 val icacheParameters = coreParams.icacheParameters 406 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 407 408 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 409 // for constrained LR/SC loop 410 val LRSCCycles = 64 411 // for lr storm 412 val LRSCBackOff = 8 413 414 // cache hierarchy configurations 415 val l1BusDataWidth = 256 416 417 // load violation predict 418 val ResetTimeMax2Pow = 20 //1078576 419 val ResetTimeMin2Pow = 10 //1024 420 // wait table parameters 421 val WaitTableSize = 1024 422 val MemPredPCWidth = log2Up(WaitTableSize) 423 val LWTUse2BitCounter = true 424 // store set parameters 425 val SSITSize = WaitTableSize 426 val LFSTSize = 32 427 val SSIDWidth = log2Up(LFSTSize) 428 val LFSTWidth = 4 429 val StoreSetEnable = true // LWT will be disabled if SS is enabled 430 431 val loadExuConfigs = coreParams.loadExuConfigs 432 val storeExuConfigs = coreParams.storeExuConfigs 433 434 val intExuConfigs = coreParams.intExuConfigs 435 436 val fpExuConfigs = coreParams.fpExuConfigs 437 438 val exuConfigs = coreParams.exuConfigs 439 440 val PCntIncrStep: Int = 6 441 val numPCntHc: Int = 25 442 val numPCntPtw: Int = 19 443 444 val numCSRPCntFrontend = 8 445 val numCSRPCntCtrl = 8 446 val numCSRPCntLsu = 8 447 val numCSRPCntHc = 5 448} 449