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/nrf52832-nimble/nordic/nrfx/hal/
H A Dnrf_spi.h11 * 2. Redistributions in binary form must reproduce the above copyright
83 NRF_SPI_FREQ_1M = SPI_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps.
84 NRF_SPI_FREQ_2M = SPI_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps.
85 NRF_SPI_FREQ_4M = SPI_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps.
88 NRF_SPI_FREQ_8M = (int)SPI_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps.
H A Dnrf_spim.h11 * 2. Redistributions in binary form must reproduce the above copyright
133 NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps.
134 NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps.
135 NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps.
138 NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8, ///< 8 Mbps.
140 NRF_SPIM_FREQ_16M = SPIM_FREQUENCY_FREQUENCY_M16, ///< 16 Mbps.
143 NRF_SPIM_FREQ_32M = SPIM_FREQUENCY_FREQUENCY_M32 ///< 32 Mbps.
H A Dnrf_ccm.h11 * 2. Redistributions in binary form must reproduce the above copyright
100 NRF_CCM_DATARATE_1M = CCM_MODE_DATARATE_1Mbit, ///< 1 Mbps.
101 NRF_CCM_DATARATE_2M = CCM_MODE_DATARATE_2Mbit, ///< 2 Mbps.
/nrf52832-nimble/packages/NimBLE-latest/nimble/controller/include/controller/
H A Dble_phy.h30 #error LE 2M PHY can only be enabled on nRF52xxx
45 #define BLE_PHY_CHAN_SPACING_MHZ (2)
70 #define BLE_PHY_STATE_TX (2)
75 #define BLE_PHY_TRANSITION_TX_RX (2)
79 #define BLE_PHY_ERR_INIT (2)
85 /* Maximun PDU length. Includes LL header of 2 bytes and 255 bytes payload. */
166 * that the data channel PDU is composed of a 2-byte header, the payload, and
193 * the PHY modes for 1Mbps and 2Mbps are the same here. For the coded phy
199 #define BLE_PHY_MODE_2M (2)
230 * Mode values are set in a way that 1M, 2M and Coded(S=2) are equivalent in ble_ll_phy_to_phy_mode()
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/nrf52832-nimble/packages/NimBLE-latest/nimble/controller/src/
H A Dble_ll_sched.c58 * 2) Need to determine how we really want to handle the case when we execute
340 * request. At 1 Mbps, this is 1752 usecs, or 57.41 ticks. Using 57 ticks in ble_ll_sched_master_new()
360 * use a transmit window of 2. We do this because we dont quite know the in ble_ll_sched_master_new()
373 * a transmit window of 1 as opposed to 2, but for now we dont care. in ble_ll_sched_master_new()
380 * PDU on 1 Mbps - we do as described above. in ble_ll_sched_master_new()
505 * 2 when using a 32768 crystal. in ble_ll_sched_master_new()
556 * sent at 1Mbps. in ble_ll_sched_master_new()
570 * request. At 1 Mbps, this is 1752 usecs, or 57.41 ticks. Using 57 ticks in ble_ll_sched_master_new()
590 * use a transmit window of 2. We do this because we dont quite know the in ble_ll_sched_master_new()
603 * a transmit window of 1 as opposed to 2, but for now we dont care. in ble_ll_sched_master_new()
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H A Dble_ll_ctrl.c50 * 2) Should we create pool of control pdu's?. Dont need more
197 ctrl_req.max_rx_time = get_le16(dptr + 2); in ble_ll_ctrl_len_proc()
254 req->interval_max = get_le16(dptr + 2); in ble_ll_ctrl_conn_param_pdu_proc()
354 rspbuf[2] = ble_err; in ble_ll_ctrl_conn_param_pdu_proc()
602 * BLE_HCI_LE_PHY_2M (2)
646 * -> if 2Mbps available, use it.
647 * -> If 1Mbps available, use it.
755 put_le16(ctrdata + 2, instant); in ble_ll_ctrl_phy_update_ind_make()
927 instant = get_le16(dptr + 2); in ble_ll_ctrl_rx_phy_update_ind()
1090 opcode = rxpdu->om_data[2]; in ble_ll_ctrl_enc_allowed_pdu_rx()
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H A Dble_ll_conn.c62 * 2) Make sure we check incoming data packets for size and all that. You
106 * 2) I think one way to handle the problem of losing up to a microsecond
229 * and we are currently at 1Mbps or lower data rate and we could use
527 /* Upper 6 bits must have 2 transitions */ in ble_ll_conn_calc_access_addr()
1002 * 2) We successfully sent the reject reason. in ble_ll_conn_chk_csm_flags()
1544 * 2) The address rx time and jitter is accounted for in the in ble_ll_conn_event_start_cb()
1548 (2 * connsm->slave_cur_window_widening); in ble_ll_conn_event_start_cb()
1629 usecs += (BLE_LL_IFS * 2) + connsm->eff_max_rx_time; in ble_ll_conn_can_send_next_pdu()
1758 if (hcc->min_ce_len > (connsm->conn_itvl * 2)) { in ble_ll_conn_master_init()
1759 connsm->min_ce_len = connsm->conn_itvl * 2; in ble_ll_conn_master_init()
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/nrf52832-nimble/packages/NimBLE-latest/nimble/controller/
H A Dsyscfg.yml55 # SCA between 101 and 150 ppm (inclusive); master sca = 2
63 # if your clock drift is 101 ppm, your master should be set to 2.
85 value: '(2 * OS_TICKS_PER_SEC)'
151 ensure interoperability with such devices set this value to 2 (or more).
195 # in v4.2, Vol 6 Part B Section 4.6.
254 Selection Algorithm #2.
259 This option is used to enable/disable support for the 2Mbps PHY.
/nrf52832-nimble/rt-thread/components/drivers/wlan/
H A Dwlan_cmd.c96 if (argc > 2) in wifi_status()
107 info.bssid[2], in wifi_status()
127 info.bssid[2], in wifi_status()
147 if (argc > 2) in wifi_scan()
158 … rt_kprintf(" SSID MAC security rssi chn Mbps\n"); in wifi_scan()
166 scan_result->info[index].bssid[2], in wifi_scan()
227 if (argc == 2) in wifi_join()
244 ssid = argv[2]; in wifi_join()
248 ssid = argv[2]; in wifi_join()
267 ssid = argv[2]; in wifi_ap()
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/nrf52832-nimble/nordic/nrfx/mdk/
H A Dnrf52840_bitfields.h11 2. Redistributions in binary form must reproduce the above copyright
79 /* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */
80 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
103 /* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */
104 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
189 /* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */
190 #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
266 /* Bit 2 : Write '1' to enable interrupt for ERROR event */
267 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
290 /* Bit 2 : Write '1' to disable interrupt for ERROR event */
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H A Dnrf52810_bitfields.h11 2. Redistributions in binary form must reproduce the above copyright
79 /* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */
80 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
103 /* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */
104 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
349 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
350 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
448 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
449 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
540 /* Bit 2 : Write '1' to enable interrupt for ERROR event */
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H A Dnrf52_bitfields.h11 2. Redistributions in binary form must reproduce the above copyright
44 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
45 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
68 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
69 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
314 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
315 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
509 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
510 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
537 /* Description: Block protect configuration register 2 */
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H A Dnrf51_bitfields.h11 2. Redistributions in binary form must reproduce the above copyright
44 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
45 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
68 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
69 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
171 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
178 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
179 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
191 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescal…
194 /* Bits 4..2 : ADC input selection. */
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H A Dnrf52840.svd19 2. Redistributions in binary form must reproduce the above copyright\n
396 <description>2 MByte FLASH</description>
733 <description>Unique identifier byte 2</description>
927 <description>Sample count for ring oscillator 2</description>
934 <description>Sample count for ring oscillator 2</description>
1211 <msb>2</msb>
1219 <name>2V1</name>
1224 <name>2V4</name>
1226 <value>2</value>
1229 <name>2V7</name>
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H A Dnrf52810.svd19 2. Redistributions in binary form must reproduce the above copyright\n
857 <description>Enable protection for region 2. Write '0' has no effect.</description>
858 <lsb>2</lsb>
859 <msb>2</msb>
1442 <lsb>2</lsb>
1443 <msb>2</msb>
2241 <value>2</value>
2290 <value>2</value>
2321 <value>2</value>
2470 <lsb>2</lsb>
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H A Dnrf9160_bitfields.h11 2. Redistributions in binary form must reproduce the above copyright
279 #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
289 #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
299 #define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
493 /* Bit 2 : Enable or disable channel 2 */
494 #define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
605 /* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */
606 #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
720 /* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */
721 #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
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H A Dnrf52.svd19 2. Redistributions in binary form must reproduce the above copyright\n
104 <dim>2</dim>
182 <dim>2</dim>
691 <description>Unique identifier byte 2</description>
893 <dim>2</dim>
1039 <description>Enable protection for region 2. Write '0' has no effect.</description>
1040 <lsb>2</lsb>
1041 <msb>2</msb>
1624 <lsb>2</lsb>
1625 <msb>2</msb>
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H A Dnrf51.svd19 2. Redistributions in binary form must reproduce the above copyright\n
54 …<nvicPrioBits>2</nvicPrioBits> <!-- Number of NVIC Priority Bits {8.…
117 <lsb>2</lsb> <msb>2</msb>
150 <lsb>2</lsb> <msb>2</msb>
218 <lsb>2</lsb> <msb>2</msb>
345 <description>RAM block 2 status.</description>
346 <lsb>2</lsb> <msb>2</msb>
350 <description>RAM block 2 is off or powering up.</description>
355 <description>RAM block 2 is on.</description>
426 <lsb>1</lsb> <msb>2</msb>
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H A Dnrf9160.svd19 2. Redistributions in binary form must reproduce the above copyright\n
399 <description>Sample count for ring oscillator 2</description>
406 <description>Sample count for ring oscillator 2</description>
707 <lsb>2</lsb>
708 <msb>2</msb>
919 <description>Pin number configuration for TRACEDATA[2]</description>
1010 <value>2</value>
1014 <description>4 MHz Trace Port clock (TRACECLK = 2 MHz)</description>
1258 <lsb>2</lsb>
1259 <msb>2</msb>
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