Lines Matching +full:2 +full:mbps

11 2. Redistributions in binary form must reproduce the above copyright
279 #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
289 #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
299 #define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
493 /* Bit 2 : Enable or disable channel 2 */
494 #define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
605 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
606 #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
720 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
721 #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
822 /* Bit 2 : Include or exclude channel 2 */
823 #define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
968 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
969 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1080 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
1081 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1195 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
1196 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1342 /* Description: Sample count for ring oscillator 2 */
1344 /* Bits 31..0 : Sample count for ring oscillator 2 */
1518 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
1519 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
1584 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
1585 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
1619 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode:…
1758 /* Bit 2 : Enable or disable interrupt for event STOPPED */
1759 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
1780 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */
1781 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
1804 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */
1805 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
1891 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
1907 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
1935 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
2103 /* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
2104 #define IPC_INTEN_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
2159 /* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
2160 #define IPC_INTENSET_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
2218 /* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
2219 #define IPC_INTENCLR_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
2272 /* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
2273 #define IPC_INTPEND_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
2323 /* Bit 2 : Enable broadcasting on channel 2. */
2324 #define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
2374 /* Bit 2 : Enable subscription to channel 2. */
2375 #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
2441 /* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */
2442 #define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
2462 /* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */
2463 #define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
2486 /* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */
2487 #define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
2510 /* Bit 2 : Read pending status of interrupt for event KEYSLOT_ERROR */
2511 #define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
2575 /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and wr…
2580 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
2636 #define NVMC_CONFIGNS_WEN_Een (2UL) /*!< Erase enabled */
2861 /* Bit 2 : Pin 2 */
2862 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3085 /* Bit 2 : Pin 2 */
3086 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3312 /* Bit 2 : Pin 2 */
3313 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3510 /* Bit 2 : Pin 2 */
3511 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3705 /* Bit 2 : Pin 2 */
3706 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3929 /* Bit 2 : Set as output pin 2 */
3930 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
4156 /* Bit 2 : Set as input pin 2 */
4157 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
4354 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to cle…
4355 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
4397 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
4405 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
4412 /* Bits 3..2 : Pull configuration */
4413 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
4546 /* Bit 2 : Enable or disable interrupt for event END */
4547 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
4567 /* Bit 2 : Write '1' to enable interrupt for event END */
4568 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
4591 /* Bit 2 : Write '1' to disable interrupt for event END */
4592 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
4845 /* Bit 2 : Enable or disable interrupt for event POFWARN */
4846 #define POWER_INTEN_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4868 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
4869 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4892 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
4893 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4926 /* Bit 2 : Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from…
4927 #define POWER_RESETREAS_OFF_Pos (2UL) /*!< Position of OFF field. */
5152 /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
5153 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
5203 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
5204 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5253 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
5254 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5305 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
5306 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5347 /* Bits 2..0 : Prescaler of PWM_CLK */
5351 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */
5352 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */
5353 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */
5372 …ER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
5373 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4t…
5374 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th …
5635 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
5680 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
5724 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
5764 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
5809 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
6246 /* Bit 2 : Enable or disable interrupt for event DONE */
6247 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
6400 /* Bit 2 : Write '1' to enable interrupt for event DONE */
6401 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
6557 /* Bit 2 : Write '1' to disable interrupt for event DONE */
6558 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
6604 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
6621 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
6637 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE nu…
6650 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
6666 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
6668 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
6670 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
6678 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
6679 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
6686 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
6687 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
6703 /* Bits 2..0 : Set the resolution */
6708 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
6718 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
6719 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
7101 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
7102 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
7103 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
7104 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
7169 /* Bit 2 : Serial clock (SCK) polarity */
7170 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
7309 /* Bit 2 : Shortcut between event END and task ACQUIRE */
7310 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
7371 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
7398 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
7497 /* Bit 2 : Serial clock (SCK) polarity */
7498 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
7602 /* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */
7603 #define SPU_INTEN_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
7623 /* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */
7624 #define SPU_INTENSET_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
7647 /* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */
7648 #define SPU_INTENCLR_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
7697 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute f…
7780 /* Bit 2 : Select secure attribute. */
7781 #define SPU_DPPI_PERM_CHANNEL2_Pos (2UL) /*!< Position of CHANNEL2 field. */
7984 /* Bit 2 : Select secure attribute attribute for PIN 2. */
7985 #define SPU_GPIOPORT_PERM_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7987 #define SPU_GPIOPORT_PERM_PIN2_NonSecure (0UL) /*!< Pin 2 has its non-secure attribute set */
7988 #define SPU_GPIOPORT_PERM_PIN2_Secure (1UL) /*!< Pin 2 has its secure attribute set */
8038 #define SPU_FLASHNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a …
8073 #define SPU_RAMNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64…
8096 /* Bit 2 : Configure read permissions for flash region n */
8097 #define SPU_FLASHREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
8129 /* Bit 2 : Configure read permissions for RAM region n */
8130 #define SPU_RAMREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
8174 /* Bits 3..2 : Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned …
8175 #define SPU_PERIPHID_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */
8179 #define SPU_PERIPHID_PERM_DMA_SeparateAttribute (2UL) /*!< Peripheral has DMA and DMA transfers can…
8186 #define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute fo…
8242 /* Description: Pin number configuration for TRACEDATA[2] */
8275 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz)…
8276 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz)…
8451 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
8487 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
8488 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
8529 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
8574 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
8603 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
8613 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
9084 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
9085 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
9608 /* Bit 2 : NACK sent after receiving a data byte */
9609 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
10150 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
10151 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10227 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
10228 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10307 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
10308 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10337 /* Bit 2 : Framing error occurred */
10338 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
10588 /* Bit 2 : Push permission for key slot */
10589 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL) /*!< Position of PUSH field. */
10650 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
10651 #define VMC_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
10696 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
10697 #define VMC_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
10739 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
10740 #define VMC_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
10863 /* Bit 2 : Request status for RR[2] register */
10864 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
10866 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are alre…
10867 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not y…
10921 /* Bit 2 : Enable or disable RR[2] register */
10922 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
10924 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
10925 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */