Lines Matching +full:2 +full:mbps
19 2. Redistributions in binary form must reproduce the above copyright\n
104 <dim>2</dim>
182 <dim>2</dim>
691 <description>Unique identifier byte 2</description>
893 <dim>2</dim>
1039 <description>Enable protection for region 2. Write '0' has no effect.</description>
1040 <lsb>2</lsb>
1041 <msb>2</msb>
1624 <lsb>2</lsb>
1625 <msb>2</msb>
2198 <description>Block protect configuration register 2</description>
2241 <lsb>2</lsb>
2242 <msb>2</msb>
2825 <lsb>2</lsb>
2826 <msb>2</msb>
3422 <lsb>2</lsb>
3423 <msb>2</msb>
3511 <lsb>2</lsb>
3512 <msb>2</msb>
3636 <lsb>2</lsb>
3637 <msb>2</msb>
3788 <description>RAM block 2 is on or off/powering up</description>
3789 <lsb>2</lsb>
3790 <msb>2</msb>
4057 <description>Keep RAM block 2 on or off in system ON Mode</description>
4093 … <description>Keep retention on RAM block 2 when RAM block is switched off</description>
4803 <value>2</value>
4852 <value>2</value>
4883 <value>2</value>
4965 <value>2</value>
4969 <description>4 MHz Trace Port clock (TRACECLK = 2 MHz)</description>
4993 <value>2</value>
5182 <lsb>2</lsb>
5183 <msb>2</msb>
5352 <lsb>2</lsb>
5353 <msb>2</msb>
5657 <lsb>2</lsb>
5658 <msb>2</msb>
5935 <msb>2</msb>
5963 <msb>2</msb>
6099 <description>2 Mbit/s Nordic proprietary radio mode</description>
6105 <value>2</value>
6114 <description>2 Mbit/s Bluetooth Low Energy</description>
6293 <description>Address prefix 2.</description>
6347 <msb>2</msb>
6395 <description>Enable or disable reception on logical address 2.</description>
6396 <lsb>2</lsb>
6397 <msb>2</msb>
6528 <value>2</value>
6645 <value>2</value>
6786 … <description>Enable or disable device address matching using device address 2</description>
6787 <lsb>2</lsb>
6788 <msb>2</msb>
6906 <description>TxAdd for device address 2</description>
6986 <value>2</value>
7035 <value>2</value>
7223 <lsb>2</lsb>
7224 <msb>2</msb>
7447 <lsb>2</lsb>
7448 <msb>2</msb>
7752 <lsb>2</lsb>
7753 <msb>2</msb>
8042 <lsb>2</lsb>
8043 <msb>2</msb>
8507 <value>2</value>
8683 <lsb>2</lsb>
8684 <msb>2</msb>
8853 <lsb>2</lsb>
8854 <msb>2</msb>
9008 <lsb>2</lsb>
9009 <msb>2</msb>
9885 <description>1 Mbps</description>
9890 <description>2 Mbps</description>
9895 <description>4 Mbps</description>
9900 <description>8 Mbps</description>
9964 <msb>2</msb>
10038 <msb>2</msb>
10100 <lsb>2</lsb>
10101 <msb>2</msb>
10190 <lsb>2</lsb>
10191 <msb>2</msb>
10411 <value>2</value>
10504 <value>2</value>
10789 <lsb>2</lsb>
10790 <msb>2</msb>
11598 <lsb>2</lsb>
11599 <msb>2</msb>
11802 <msb>2</msb>
11876 <msb>2</msb>
12521 <lsb>2</lsb>
12522 <msb>2</msb>
12765 <dim>2</dim>
12874 <lsb>2</lsb>
12875 <msb>2</msb>
12909 <lsb>2</lsb>
12910 <msb>2</msb>
13092 <description>1 Mbps</description>
13097 <description>2 Mbps</description>
13102 <description>4 Mbps</description>
13107 <description>8 Mbps</description>
13159 <lsb>2</lsb>
13160 <msb>2</msb>
13342 <lsb>2</lsb>
13343 <msb>2</msb>
13512 <lsb>2</lsb>
13513 <msb>2</msb>
13710 <lsb>2</lsb>
13711 <msb>2</msb>
14179 <lsb>2</lsb>
14180 <msb>2</msb>
14475 <lsb>2</lsb>
14476 <msb>2</msb>
14888 <lsb>2</lsb>
14889 <msb>2</msb>
15254 <lsb>2</lsb>
15255 <msb>2</msb>
15297 <lsb>2</lsb>
15298 <msb>2</msb>
15448 <value>2</value>
15537 <lsb>2</lsb>
15538 <msb>2</msb>
15582 <msb>2</msb>
15625 <lsb>2</lsb>
15626 <msb>2</msb>
15670 <msb>2</msb>
15792 <value>2</value>
15836 <value>2</value>
15842 …<description>Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in …
15869 <lsb>2</lsb>
15870 <msb>2</msb>
16022 <description>Write '1' to Enable interrupt for IN[2] event</description>
16023 <lsb>2</lsb>
16024 <msb>2</msb>
16273 <description>Write '1' to Disable interrupt for IN[2] event</description>
16274 <lsb>2</lsb>
16275 <msb>2</msb>
16518 <value>2</value>
16689 <lsb>2</lsb>
16690 <msb>2</msb>
16832 <description>Enable or disable interrupt for CH[2].LIMITH event</description>
16850 <description>Enable or disable interrupt for CH[2].LIMITL event</description>
17111 <lsb>2</lsb>
17112 <msb>2</msb>
17326 <description>Write '1' to Enable interrupt for CH[2].LIMITH event</description>
17353 <description>Write '1' to Enable interrupt for CH[2].LIMITL event</description>
17713 <lsb>2</lsb>
17714 <msb>2</msb>
17928 <description>Write '1' to Disable interrupt for CH[2].LIMITH event</description>
17955 <description>Write '1' to Disable interrupt for CH[2].LIMITL event</description>
18336 <value>2</value>
18403 <value>2</value>
18470 <value>2</value>
18474 <description>Set input at VDD/2</description>
18498 <value>2</value>
18502 <description>Set input at VDD/2</description>
18526 <value>2</value>
18535 <description>1/2</description>
18545 <description>2</description>
18592 <value>2</value>
18642 …<description>Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, …
18682 <msb>2</msb>
18697 <value>2</value>
18727 <description>Oversample 2x</description>
18733 <value>2</value>
18957 <description>Shortcut between COMPARE[2] event and CLEAR task</description>
18958 <lsb>2</lsb>
18959 <msb>2</msb>
19065 <description>Shortcut between COMPARE[2] event and STOP task</description>
19199 <description>Write '1' to Enable interrupt for COMPARE[2] event</description>
19369 <description>Write '1' to Disable interrupt for COMPARE[2] event</description>
19502 <value>2</value>
19533 <value>2</value>
19588 <description>Timer/Counter 2</description>
19772 <description>Write '1' to Enable interrupt for COMPARE[2] event</description>
19942 <description>Write '1' to Disable interrupt for COMPARE[2] event</description>
20076 <description>Enable or disable event routing for COMPARE[2] event</description>
20228 <description>Write '1' to Enable event routing for COMPARE[2] event</description>
20398 <description>Write '1' to Disable event routing for COMPARE[2] event</description>
20634 <description>Slope of 2nd piece wise linear function</description>
20641 <description>Slope of 2nd piece wise linear function</description>
20724 <description>y-intercept of 2nd piece wise linear function</description>
20731 <description>y-intercept of 2nd piece wise linear function</description>
20814 <description>End point of 2nd piece wise linear function</description>
20821 <description>End point of 2nd piece wise linear function</description>
21367 <lsb>2</lsb>
21368 <msb>2</msb>
21456 <lsb>2</lsb>
21457 <msb>2</msb>
21528 <value>2</value>
21571 <name>2Mbit</name>
21572 <description>In synch with 2 Mbit data rate</description>
21765 <lsb>2</lsb>
21766 <msb>2</msb>
21854 <lsb>2</lsb>
21855 <msb>2</msb>
22148 <description>Request status for RR[2] register</description>
22149 <lsb>2</lsb>
22150 <msb>2</msb>
22154 … <description>RR[2] register is not enabled, or are already requesting reload</description>
22159 … <description>RR[2] register is enabled, and are not yet requesting reload</description>
22316 <description>Enable or disable RR[2] register</description>
22317 <lsb>2</lsb>
22318 <msb>2</msb>
22322 <description>Disable RR[2] register</description>
22327 <description>Enable RR[2] register</description>
22624 <lsb>2</lsb>
22625 <msb>2</msb>
22776 <lsb>2</lsb>
22777 <msb>2</msb>
22919 <lsb>2</lsb>
22920 <msb>2</msb>
23076 <value>2</value>
23162 <value>2</value>
23381 …er accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).</description>
23506 <lsb>2</lsb>
23507 <msb>2</msb>
23604 <lsb>2</lsb>
23605 <msb>2</msb>
23702 <lsb>2</lsb>
23703 <msb>2</msb>
23818 <lsb>2</lsb>
23819 <msb>2</msb>
23917 <value>2</value>
23933 <msb>2</msb>
23948 <value>2</value>
23990 <msb>2</msb>
24005 <value>2</value>
24031 <msb>2</msb>
24046 <value>2</value>
24123 <value>2</value>
24198 <value>2</value>
24315 <lsb>2</lsb>
24316 <msb>2</msb>
24431 <lsb>2</lsb>
24432 <msb>2</msb>
24547 <lsb>2</lsb>
24548 <msb>2</msb>
24662 <msb>2</msb>
24677 <value>2</value>
24728 <description>VDD * 2/8 selected as reference</description>
24734 <value>2</value>
24856 <value>2</value>
24994 <description>Enable or disable interrupt for TRIGGERED[2] event</description>
24995 <lsb>2</lsb>
24996 <msb>2</msb>
25308 <description>Write '1' to Enable interrupt for TRIGGERED[2] event</description>
25309 <lsb>2</lsb>
25310 <msb>2</msb>
25748 <description>Write '1' to Disable interrupt for TRIGGERED[2] event</description>
25749 <lsb>2</lsb>
25750 <msb>2</msb>
26149 <description>Software interrupt 2</description>
26158 <description>Event Generator Unit 2</description>
26265 <dim>2</dim>
26285 <dim>2</dim>
26293 <dim>2</dim>
26357 <lsb>2</lsb>
26358 <msb>2</msb>
26437 <lsb>2</lsb>
26438 <msb>2</msb>
26580 <lsb>2</lsb>
26581 <msb>2</msb>
26777 <lsb>2</lsb>
26778 <msb>2</msb>
27018 <msb>2</msb>
27027 <description>Divide by 2 ( 8MHz)</description>
27033 <value>2</value>
27037 <description>Divide by 8 ( 2MHz)</description>
27084 … <description>1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3</description>
27089 … <description>1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3</description>
27090 <value>2</value>
27094 … <description>1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP</description>
27142 <dim>2</dim>
27357 <lsb>2</lsb>
27358 <msb>2</msb>
27437 <lsb>2</lsb>
27438 <msb>2</msb>
27526 <lsb>2</lsb>
27527 <msb>2</msb>
27889 <value>2</value>
28140 <description>Enable or disable channel 2</description>
28141 <lsb>2</lsb>
28142 <msb>2</msb>
28743 <description>Channel 2 enable set register. Writing '0' has no effect</description>
28744 <lsb>2</lsb>
28745 <msb>2</msb>
29616 <description>Channel 2 enable clear register. Writing '0' has no effect</description>
29617 <lsb>2</lsb>
29618 <msb>2</msb>
30507 <description>Include or exclude channel 2</description>
30508 <lsb>2</lsb>
30509 <msb>2</msb>
31106 <dim>2</dim>
31169 <lsb>2</lsb>
31170 <msb>2</msb>
31204 <description>Enable or disable interrupt for REGION[2].WA event</description>
31222 <description>Enable or disable interrupt for REGION[2].RA event</description>
31411 <lsb>2</lsb>
31412 <msb>2</msb>
31464 <description>Write '1' to Enable interrupt for REGION[2].WA event</description>
31491 <description>Write '1' to Enable interrupt for REGION[2].RA event</description>
31743 <lsb>2</lsb>
31744 <msb>2</msb>
31796 <description>Write '1' to Disable interrupt for REGION[2].WA event</description>
31823 <description>Write '1' to Disable interrupt for REGION[2].RA event</description>
32057 <lsb>2</lsb>
32058 <msb>2</msb>
32092 … <description>Enable or disable non-maskable interrupt for REGION[2].WA event</description>
32110 … <description>Enable or disable non-maskable interrupt for REGION[2].RA event</description>
32299 <lsb>2</lsb>
32300 <msb>2</msb>
32352 … <description>Write '1' to Enable non-maskable interrupt for REGION[2].WA event</description>
32379 … <description>Write '1' to Enable non-maskable interrupt for REGION[2].RA event</description>
32631 <lsb>2</lsb>
32632 <msb>2</msb>
32684 … <description>Write '1' to Disable non-maskable interrupt for REGION[2].WA event</description>
32711 … <description>Write '1' to Disable non-maskable interrupt for REGION[2].RA event</description>
32901 <dim>2</dim>
32951 <description>Subregion 2 in region 0 (write '1' to clear)</description>
32952 <lsb>2</lsb>
32953 <msb>2</msb>
33536 <description>Subregion 2 in region 0 (write '1' to clear)</description>
33537 <lsb>2</lsb>
33538 <msb>2</msb>
34122 <lsb>2</lsb>
34123 <msb>2</msb>
34157 <description>Enable/disable write access watch in region[2]</description>
34175 <description>Enable/disable read access watch in region[2]</description>
34364 <lsb>2</lsb>
34365 <msb>2</msb>
34417 <description>Enable write access watch in region[2]</description>
34444 <description>Enable read access watch in region[2]</description>
34696 <lsb>2</lsb>
34697 <msb>2</msb>
34749 <description>Disable write access watch in region[2]</description>
34776 <description>Disable read access watch in region[2]</description>
35002 <dim>2</dim>
35080 <description>Include or exclude subregion 2 in region</description>
35081 <lsb>2</lsb>
35082 <msb>2</msb>
35634 <description>Pulse Width Modulation Unit 2</description>
35643 <description>Serial Peripheral Interface Master with EasyDMA 2</description>
35652 <description>SPI Slave 2</description>
35662 <description>Serial Peripheral Interface 2</description>
35672 <description>Real time counter 2</description>
35752 <lsb>2</lsb>
35753 <msb>2</msb>
35823 <lsb>2</lsb>
35824 <msb>2</msb>
35912 <lsb>2</lsb>
35913 <msb>2</msb>
36119 <description>32 MHz / 2 = 16.0 MHz</description>
36237 <value>2</value>
36299 <value>2</value>
36385 <value>2</value>
36706 <description>Pin 2</description>
36707 <lsb>2</lsb>
36708 <msb>2</msb>
37309 <description>Pin 2</description>
37310 <lsb>2</lsb>
37311 <msb>2</msb>
38182 <description>Pin 2</description>
38183 <lsb>2</lsb>
38184 <msb>2</msb>
39036 <description>Pin 2</description>
39037 <lsb>2</lsb>
39038 <msb>2</msb>
39620 <description>Pin 2</description>
39621 <lsb>2</lsb>
39622 <msb>2</msb>
40223 <description>Set as output pin 2</description>
40224 <lsb>2</lsb>
40225 <msb>2</msb>
41096 <description>Set as input pin 2</description>
41097 <lsb>2</lsb>
41098 <msb>2</msb>
41951 <lsb>2</lsb>
41952 <msb>2</msb>
42564 <lsb>2</lsb>
42603 <value>2</value>
42646 <value>2</value>