Lines Matching +full:2 +full:mbps
19 2. Redistributions in binary form must reproduce the above copyright\n
857 <description>Enable protection for region 2. Write '0' has no effect.</description>
858 <lsb>2</lsb>
859 <msb>2</msb>
1442 <lsb>2</lsb>
1443 <msb>2</msb>
2241 <value>2</value>
2290 <value>2</value>
2321 <value>2</value>
2470 <lsb>2</lsb>
2471 <msb>2</msb>
2559 <lsb>2</lsb>
2560 <msb>2</msb>
2684 <lsb>2</lsb>
2685 <msb>2</msb>
3458 <lsb>2</lsb>
3459 <msb>2</msb>
3628 <lsb>2</lsb>
3629 <msb>2</msb>
3933 <lsb>2</lsb>
3934 <msb>2</msb>
4211 <msb>2</msb>
4239 <msb>2</msb>
4375 <description>2 Mbit/s Nordic proprietary radio mode</description>
4385 <description>2 Mbit/s Bluetooth Low Energy</description>
4564 <description>Address prefix 2.</description>
4618 <msb>2</msb>
4666 <description>Enable or disable reception on logical address 2.</description>
4667 <lsb>2</lsb>
4668 <msb>2</msb>
4799 <value>2</value>
4916 <value>2</value>
5057 … <description>Enable or disable device address matching using device address 2</description>
5058 <lsb>2</lsb>
5059 <msb>2</msb>
5177 <description>TxAdd for device address 2</description>
5257 <value>2</value>
5304 <value>2</value>
5606 <lsb>2</lsb>
5607 <msb>2</msb>
5830 <lsb>2</lsb>
5831 <msb>2</msb>
6135 <lsb>2</lsb>
6136 <msb>2</msb>
6425 <lsb>2</lsb>
6426 <msb>2</msb>
7756 <lsb>2</lsb>
7757 <msb>2</msb>
7960 <msb>2</msb>
8034 <msb>2</msb>
8756 <lsb>2</lsb>
8757 <msb>2</msb>
9683 <description>1 Mbps</description>
9688 <description>2 Mbps</description>
9693 <description>4 Mbps</description>
9698 <description>8 Mbps</description>
9762 <msb>2</msb>
9836 <msb>2</msb>
9898 <lsb>2</lsb>
9899 <msb>2</msb>
10023 <lsb>2</lsb>
10024 <msb>2</msb>
10244 <value>2</value>
10337 <value>2</value>
10622 <lsb>2</lsb>
10623 <msb>2</msb>
10820 <description>Write '1' to enable interrupt for IN[2] event</description>
10821 <lsb>2</lsb>
10822 <msb>2</msb>
11071 <description>Write '1' to disable interrupt for IN[2] event</description>
11072 <lsb>2</lsb>
11073 <msb>2</msb>
11316 <value>2</value>
11572 <lsb>2</lsb>
11573 <msb>2</msb>
11715 <description>Enable or disable interrupt for CH[2].LIMITH event</description>
11733 <description>Enable or disable interrupt for CH[2].LIMITL event</description>
11994 <lsb>2</lsb>
11995 <msb>2</msb>
12209 <description>Write '1' to enable interrupt for CH[2].LIMITH event</description>
12236 <description>Write '1' to enable interrupt for CH[2].LIMITL event</description>
12596 <lsb>2</lsb>
12597 <msb>2</msb>
12811 <description>Write '1' to disable interrupt for CH[2].LIMITH event</description>
12838 <description>Write '1' to disable interrupt for CH[2].LIMITL event</description>
13220 <value>2</value>
13287 <value>2</value>
13354 <value>2</value>
13358 <description>Set input at VDD/2</description>
13382 <value>2</value>
13386 <description>Set input at VDD/2</description>
13410 <value>2</value>
13419 <description>1/2</description>
13429 <description>2</description>
13476 <value>2</value>
13526 …<description>Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, …
13566 <msb>2</msb>
13581 <value>2</value>
13611 <description>Oversample 2x</description>
13617 <value>2</value>
13891 <description>Shortcut between COMPARE[2] event and CLEAR task</description>
13892 <lsb>2</lsb>
13893 <msb>2</msb>
13999 <description>Shortcut between COMPARE[2] event and STOP task</description>
14133 <description>Write '1' to enable interrupt for COMPARE[2] event</description>
14303 <description>Write '1' to disable interrupt for COMPARE[2] event</description>
14436 <value>2</value>
14467 <value>2</value>
14522 <description>Timer/Counter 2</description>
14755 <description>Write '1' to enable interrupt for COMPARE[2] event</description>
14925 <description>Write '1' to disable interrupt for COMPARE[2] event</description>
15059 <description>Enable or disable event routing for COMPARE[2] event</description>
15211 <description>Write '1' to enable event routing for COMPARE[2] event</description>
15381 <description>Write '1' to disable event routing for COMPARE[2] event</description>
15638 <description>Slope of 2nd piece wise linear function</description>
15645 <description>Slope of 2nd piece wise linear function</description>
15728 <description>y-intercept of 2nd piece wise linear function</description>
15735 <description>y-intercept of 2nd piece wise linear function</description>
15818 <description>End point of 2nd piece wise linear function</description>
15825 <description>End point of 2nd piece wise linear function</description>
16423 <lsb>2</lsb>
16424 <msb>2</msb>
16512 <lsb>2</lsb>
16513 <msb>2</msb>
16834 <lsb>2</lsb>
16835 <msb>2</msb>
16923 <lsb>2</lsb>
16924 <msb>2</msb>
16995 <value>2</value>
17034 <description>1 Mbps</description>
17038 <name>2Mbit</name>
17039 <description>2 Mbps</description>
17045 <value>2</value>
17161 <description>1 Mbps</description>
17165 <name>2Mbit</name>
17166 <description>2 Mbps</description>
17172 <value>2</value>
17368 <description>Request status for RR[2] register</description>
17369 <lsb>2</lsb>
17370 <msb>2</msb>
17374 … <description>RR[2] register is not enabled, or are already requesting reload</description>
17379 … <description>RR[2] register is enabled, and are not yet requesting reload</description>
17536 <description>Enable or disable RR[2] register</description>
17537 <lsb>2</lsb>
17538 <msb>2</msb>
17542 <description>Disable RR[2] register</description>
17547 <description>Enable RR[2] register</description>
17914 <lsb>2</lsb>
17915 <msb>2</msb>
18066 <lsb>2</lsb>
18067 <msb>2</msb>
18209 <lsb>2</lsb>
18210 <msb>2</msb>
18366 <value>2</value>
18452 <value>2</value>
18672 …er accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).</description>
18846 <lsb>2</lsb>
18847 <msb>2</msb>
18944 <lsb>2</lsb>
18945 <msb>2</msb>
19042 <lsb>2</lsb>
19043 <msb>2</msb>
19158 <lsb>2</lsb>
19159 <msb>2</msb>
19257 <value>2</value>
19273 <msb>2</msb>
19288 <value>2</value>
19312 <description>VDD/2 selected as analog input</description>
19330 <msb>2</msb>
19345 <value>2</value>
19371 <msb>2</msb>
19386 <value>2</value>
19463 <value>2</value>
19606 <description>Enable or disable interrupt for TRIGGERED[2] event</description>
19607 <lsb>2</lsb>
19608 <msb>2</msb>
19920 <description>Write '1' to enable interrupt for TRIGGERED[2] event</description>
19921 <lsb>2</lsb>
19922 <msb>2</msb>
20360 <description>Write '1' to disable interrupt for TRIGGERED[2] event</description>
20361 <lsb>2</lsb>
20362 <msb>2</msb>
20788 <description>Software interrupt 2</description>
20994 <lsb>2</lsb>
20995 <msb>2</msb>
21074 <lsb>2</lsb>
21075 <msb>2</msb>
21217 <lsb>2</lsb>
21218 <msb>2</msb>
21414 <lsb>2</lsb>
21415 <msb>2</msb>
21655 <msb>2</msb>
21664 <description>Divide by 2 (8 MHz)</description>
21670 <value>2</value>
21674 <description>Divide by 8 (2 MHz)</description>
21721 … <description>1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3</description>
21726 … <description>1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3</description>
21727 <value>2</value>
21731 … <description>1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP</description>
21779 <dim>2</dim>
22029 <lsb>2</lsb>
22030 <msb>2</msb>
22109 <lsb>2</lsb>
22110 <msb>2</msb>
22198 <lsb>2</lsb>
22199 <msb>2</msb>
22564 <value>2</value>
22786 <description>Enable or disable channel 2</description>
22787 <lsb>2</lsb>
22788 <msb>2</msb>
23389 <description>Channel 2 enable set register. Writing '0' has no effect</description>
23390 <lsb>2</lsb>
23391 <msb>2</msb>
24262 <description>Channel 2 enable clear register. Writing '0' has no effect</description>
24263 <lsb>2</lsb>
24264 <msb>2</msb>
25154 <description>Include or exclude channel 2</description>
25155 <lsb>2</lsb>
25156 <msb>2</msb>
25775 <description>Pin 2</description>
25776 <lsb>2</lsb>
25777 <msb>2</msb>
26378 <description>Pin 2</description>
26379 <lsb>2</lsb>
26380 <msb>2</msb>
27251 <description>Pin 2</description>
27252 <lsb>2</lsb>
27253 <msb>2</msb>
28105 <description>Pin 2</description>
28106 <lsb>2</lsb>
28107 <msb>2</msb>
28689 <description>Pin 2</description>
28690 <lsb>2</lsb>
28691 <msb>2</msb>
29292 <description>Set as output pin 2</description>
29293 <lsb>2</lsb>
29294 <msb>2</msb>
30165 <description>Set as input pin 2</description>
30166 <lsb>2</lsb>
30167 <msb>2</msb>
31020 <lsb>2</lsb>
31021 <msb>2</msb>
31633 <lsb>2</lsb>
31672 <value>2</value>
31715 <value>2</value>