Lines Matching +full:2 +full:mbps
19 2. Redistributions in binary form must reproduce the above copyright\n
396 <description>2 MByte FLASH</description>
733 <description>Unique identifier byte 2</description>
927 <description>Sample count for ring oscillator 2</description>
934 <description>Sample count for ring oscillator 2</description>
1211 <msb>2</msb>
1219 <name>2V1</name>
1224 <name>2V4</name>
1226 <value>2</value>
1229 <name>2V7</name>
1900 <value>2</value>
1949 <value>2</value>
1980 <value>2</value>
2089 <value>2</value>
2093 <description>4 MHz trace port clock (TRACECLK = 2 MHz)</description>
2117 <value>2</value>
2300 <lsb>2</lsb>
2301 <msb>2</msb>
2470 <lsb>2</lsb>
2471 <msb>2</msb>
2676 <lsb>2</lsb>
2677 <msb>2</msb>
2846 <description>RAM block 2 is on or off/powering up</description>
2847 <lsb>2</lsb>
2848 <msb>2</msb>
3059 <value>2</value>
3290 <lsb>2</lsb>
3291 <msb>2</msb>
3865 <lsb>2</lsb>
3866 <msb>2</msb>
4290 <lsb>2</lsb>
4291 <msb>2</msb>
5198 <lsb>2</lsb>
5199 <msb>2</msb>
5566 <lsb>2</lsb>
5567 <msb>2</msb>
6168 <lsb>2</lsb>
6169 <msb>2</msb>
6743 <msb>2</msb>
6771 <msb>2</msb>
6803 <msb>2</msb>
6910 <description>+2 dBm</description>
6976 <description>2 Mbit/s Nordic proprietary radio mode</description>
6986 <description>2 Mbit/s BLE</description>
7075 <value>2</value>
7220 <description>Address prefix 2.</description>
7274 <msb>2</msb>
7322 <description>Enable or disable reception on logical address 2.</description>
7323 <lsb>2</lsb>
7324 <msb>2</msb>
7455 <value>2</value>
7483 <value>2</value>
7571 <value>2</value>
7712 … <description>Enable or disable device address matching using device address 2</description>
7713 <lsb>2</lsb>
7714 <msb>2</msb>
7832 <description>TxAdd for device address 2</description>
7924 <value>2</value>
7986 <msb>2</msb>
8001 <value>2</value>
8076 <value>2</value>
8331 <lsb>2</lsb>
8332 <msb>2</msb>
8501 <lsb>2</lsb>
8502 <msb>2</msb>
8656 <lsb>2</lsb>
8657 <msb>2</msb>
9076 <value>2</value>
9378 <lsb>2</lsb>
9379 <msb>2</msb>
9602 <lsb>2</lsb>
9603 <msb>2</msb>
9907 <lsb>2</lsb>
9908 <msb>2</msb>
10197 <lsb>2</lsb>
10198 <msb>2</msb>
10728 <lsb>2</lsb>
10729 <msb>2</msb>
10763 <lsb>2</lsb>
10764 <msb>2</msb>
10997 <description>1 Mbps</description>
11002 <description>2 Mbps</description>
11007 <description>4 Mbps</description>
11012 <description>8 Mbps</description>
11064 <lsb>2</lsb>
11065 <msb>2</msb>
11793 <description>1 Mbps</description>
11798 <description>2 Mbps</description>
11803 <description>4 Mbps</description>
11808 <description>8 Mbps</description>
11813 <description>16 Mbps</description>
11818 <description>32 Mbps</description>
12018 <lsb>2</lsb>
12019 <msb>2</msb>
12051 <msb>2</msb>
12259 <lsb>2</lsb>
12260 <msb>2</msb>
12480 <value>2</value>
12573 <value>2</value>
12882 <lsb>2</lsb>
12883 <msb>2</msb>
13170 <lsb>2</lsb>
13171 <msb>2</msb>
13340 <lsb>2</lsb>
13341 <msb>2</msb>
13522 <lsb>2</lsb>
13523 <msb>2</msb>
14591 <lsb>2</lsb>
14592 <msb>2</msb>
14807 <msb>2</msb>
14881 <msb>2</msb>
15603 <lsb>2</lsb>
15604 <msb>2</msb>
16403 <lsb>2</lsb>
16404 <msb>2</msb>
16699 <lsb>2</lsb>
16700 <msb>2</msb>
17112 <lsb>2</lsb>
17113 <msb>2</msb>
17510 <lsb>2</lsb>
17511 <msb>2</msb>
17556 <msb>2</msb>
17566 <value>2</value>
17721 <value>2</value>
17812 <lsb>2</lsb>
17813 <msb>2</msb>
17857 <msb>2</msb>
17901 <lsb>2</lsb>
17902 <msb>2</msb>
17946 <msb>2</msb>
18095 <value>2</value>
18139 <value>2</value>
18145 …<description>Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in …
18172 <lsb>2</lsb>
18173 <msb>2</msb>
18348 <description>Write '1' to enable interrupt for IN[2] event</description>
18349 <lsb>2</lsb>
18350 <msb>2</msb>
18599 <description>Write '1' to disable interrupt for IN[2] event</description>
18600 <lsb>2</lsb>
18601 <msb>2</msb>
18850 <value>2</value>
19106 <lsb>2</lsb>
19107 <msb>2</msb>
19249 <description>Enable or disable interrupt for CH[2].LIMITH event</description>
19267 <description>Enable or disable interrupt for CH[2].LIMITL event</description>
19528 <lsb>2</lsb>
19529 <msb>2</msb>
19743 <description>Write '1' to enable interrupt for CH[2].LIMITH event</description>
19770 <description>Write '1' to enable interrupt for CH[2].LIMITL event</description>
20130 <lsb>2</lsb>
20131 <msb>2</msb>
20345 <description>Write '1' to disable interrupt for CH[2].LIMITH event</description>
20372 <description>Write '1' to disable interrupt for CH[2].LIMITL event</description>
20754 <value>2</value>
20826 <value>2</value>
20898 <value>2</value>
20902 <description>Set input at VDD/2</description>
20926 <value>2</value>
20930 <description>Set input at VDD/2</description>
20954 <value>2</value>
20963 <description>1/2</description>
20973 <description>2</description>
21020 <value>2</value>
21070 …<description>Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, …
21110 <msb>2</msb>
21125 <value>2</value>
21155 <description>Oversample 2x</description>
21161 <value>2</value>
21435 <description>Shortcut between COMPARE[2] event and CLEAR task</description>
21436 <lsb>2</lsb>
21437 <msb>2</msb>
21543 <description>Shortcut between COMPARE[2] event and STOP task</description>
21677 <description>Write '1' to enable interrupt for COMPARE[2] event</description>
21847 <description>Write '1' to disable interrupt for COMPARE[2] event</description>
21980 <value>2</value>
22011 <value>2</value>
22066 <description>Timer/Counter 2</description>
22299 <description>Write '1' to enable interrupt for COMPARE[2] event</description>
22469 <description>Write '1' to disable interrupt for COMPARE[2] event</description>
22603 <description>Enable or disable event routing for COMPARE[2] event</description>
22755 <description>Write '1' to enable event routing for COMPARE[2] event</description>
22925 <description>Write '1' to disable event routing for COMPARE[2] event</description>
23182 <description>Slope of 2nd piece wise linear function</description>
23189 <description>Slope of 2nd piece wise linear function</description>
23272 <description>y-intercept of 2nd piece wise linear function</description>
23279 <description>y-intercept of 2nd piece wise linear function</description>
23362 <description>End point of 2nd piece wise linear function</description>
23369 <description>End point of 2nd piece wise linear function</description>
23967 <lsb>2</lsb>
23968 <msb>2</msb>
24056 <lsb>2</lsb>
24057 <msb>2</msb>
24378 <lsb>2</lsb>
24379 <msb>2</msb>
24467 <lsb>2</lsb>
24468 <msb>2</msb>
24539 <value>2</value>
24578 <description>1 Mbps</description>
24582 <name>2Mbit</name>
24583 <description>2 Mbps</description>
24589 <value>2</value>
24705 <description>1 Mbps</description>
24709 <name>2Mbit</name>
24710 <description>2 Mbps</description>
24716 <value>2</value>
24912 <description>Request status for RR[2] register</description>
24913 <lsb>2</lsb>
24914 <msb>2</msb>
24918 … <description>RR[2] register is not enabled, or are already requesting reload</description>
24923 … <description>RR[2] register is enabled, and are not yet requesting reload</description>
25080 <description>Enable or disable RR[2] register</description>
25081 <lsb>2</lsb>
25082 <msb>2</msb>
25086 <description>Disable RR[2] register</description>
25091 <description>Enable RR[2] register</description>
25458 <lsb>2</lsb>
25459 <msb>2</msb>
25610 <lsb>2</lsb>
25611 <msb>2</msb>
25753 <lsb>2</lsb>
25754 <msb>2</msb>
25910 <value>2</value>
25996 <value>2</value>
26234 …er accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).</description>
26408 <lsb>2</lsb>
26409 <msb>2</msb>
26506 <lsb>2</lsb>
26507 <msb>2</msb>
26604 <lsb>2</lsb>
26605 <msb>2</msb>
26720 <lsb>2</lsb>
26721 <msb>2</msb>
26819 <value>2</value>
26835 <msb>2</msb>
26850 <value>2</value>
26892 <msb>2</msb>
26907 <value>2</value>
26933 <msb>2</msb>
26948 <value>2</value>
27025 <value>2</value>
27230 <lsb>2</lsb>
27231 <msb>2</msb>
27346 <lsb>2</lsb>
27347 <msb>2</msb>
27462 <lsb>2</lsb>
27463 <msb>2</msb>
27577 <msb>2</msb>
27592 <value>2</value>
27643 <description>VDD * 2/8 selected as reference</description>
27649 <value>2</value>
27771 <value>2</value>
27896 <description>Enable or disable interrupt for TRIGGERED[2] event</description>
27897 <lsb>2</lsb>
27898 <msb>2</msb>
28210 <description>Write '1' to enable interrupt for TRIGGERED[2] event</description>
28211 <lsb>2</lsb>
28212 <msb>2</msb>
28650 <description>Write '1' to disable interrupt for TRIGGERED[2] event</description>
28651 <lsb>2</lsb>
28652 <msb>2</msb>
29078 <description>Event Generator Unit 2</description>
29087 <description>Software interrupt 2</description>
29342 <lsb>2</lsb>
29343 <msb>2</msb>
29422 <lsb>2</lsb>
29423 <msb>2</msb>
29565 <lsb>2</lsb>
29566 <msb>2</msb>
29762 <lsb>2</lsb>
29763 <msb>2</msb>
30003 <msb>2</msb>
30012 <description>Divide by 2 (8 MHz)</description>
30018 <value>2</value>
30022 <description>Divide by 8 (2 MHz)</description>
30069 … <description>1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3</description>
30074 … <description>1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3</description>
30075 <value>2</value>
30079 … <description>1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP</description>
30127 <dim>2</dim>
30383 <lsb>2</lsb>
30384 <msb>2</msb>
30463 <lsb>2</lsb>
30464 <msb>2</msb>
30552 <lsb>2</lsb>
30553 <msb>2</msb>
30985 <lsb>2</lsb>
30986 <msb>2</msb>
31102 <value>2</value>
31397 <description>Enable or disable channel 2</description>
31398 <lsb>2</lsb>
31399 <msb>2</msb>
32000 <description>Channel 2 enable set register. Writing '0' has no effect</description>
32001 <lsb>2</lsb>
32002 <msb>2</msb>
32873 <description>Channel 2 enable clear register. Writing '0' has no effect</description>
32874 <lsb>2</lsb>
32875 <msb>2</msb>
33765 <description>Include or exclude channel 2</description>
33766 <lsb>2</lsb>
33767 <msb>2</msb>
34380 <dim>2</dim>
34458 <lsb>2</lsb>
34459 <msb>2</msb>
34493 <description>Enable or disable interrupt for REGION[2].WA event</description>
34511 <description>Enable or disable interrupt for REGION[2].RA event</description>
34700 <lsb>2</lsb>
34701 <msb>2</msb>
34753 <description>Write '1' to enable interrupt for REGION[2].WA event</description>
34780 <description>Write '1' to enable interrupt for REGION[2].RA event</description>
35032 <lsb>2</lsb>
35033 <msb>2</msb>
35085 <description>Write '1' to disable interrupt for REGION[2].WA event</description>
35112 <description>Write '1' to disable interrupt for REGION[2].RA event</description>
35346 <lsb>2</lsb>
35347 <msb>2</msb>
35381 … <description>Enable or disable non-maskable interrupt for REGION[2].WA event</description>
35399 … <description>Enable or disable non-maskable interrupt for REGION[2].RA event</description>
35588 <lsb>2</lsb>
35589 <msb>2</msb>
35641 … <description>Write '1' to enable non-maskable interrupt for REGION[2].WA event</description>
35668 … <description>Write '1' to enable non-maskable interrupt for REGION[2].RA event</description>
35920 <lsb>2</lsb>
35921 <msb>2</msb>
35973 … <description>Write '1' to disable non-maskable interrupt for REGION[2].WA event</description>
36000 … <description>Write '1' to disable non-maskable interrupt for REGION[2].RA event</description>
36190 <dim>2</dim>
36241 <description>Subregion 2 in region n (write '1' to clear)</description>
36242 <lsb>2</lsb>
36243 <msb>2</msb>
36826 <description>Subregion 2 in region n (write '1' to clear)</description>
36827 <lsb>2</lsb>
36828 <msb>2</msb>
37412 <lsb>2</lsb>
37413 <msb>2</msb>
37447 <description>Enable/disable write access watch in region[2]</description>
37465 <description>Enable/disable read access watch in region[2]</description>
37654 <lsb>2</lsb>
37655 <msb>2</msb>
37707 <description>Enable write access watch in region[2]</description>
37734 <description>Enable read access watch in region[2]</description>
37986 <lsb>2</lsb>
37987 <msb>2</msb>
38039 <description>Disable write access watch in region[2]</description>
38066 <description>Disable read access watch in region[2]</description>
38293 <dim>2</dim>
38372 <description>Include or exclude subregion 2 in region</description>
38373 <lsb>2</lsb>
38374 <msb>2</msb>
38926 <description>Pulse width modulation unit 2</description>
38935 <description>Serial Peripheral Interface 2</description>
38944 <description>Serial Peripheral Interface Master with EasyDMA 2</description>
38954 <description>SPI Slave 2</description>
38964 <description>Real time counter 2</description>
39081 <lsb>2</lsb>
39082 <msb>2</msb>
39152 <lsb>2</lsb>
39153 <msb>2</msb>
39241 <lsb>2</lsb>
39242 <msb>2</msb>
39449 <description>32 MHz / 2 = 16.0 MHz</description>
39567 <value>2</value>
39629 <value>2</value>
39715 <value>2</value>
40342 <lsb>2</lsb>
40343 <msb>2</msb>
40440 <lsb>2</lsb>
40441 <msb>2</msb>
40475 <description>Enable or disable interrupt for ENDEPIN[2] event</description>
40655 <description>Enable or disable interrupt for ENDEPOUT[2] event</description>
40916 <lsb>2</lsb>
40917 <msb>2</msb>
40969 <description>Write '1' to enable interrupt for ENDEPIN[2] event</description>
41239 <description>Write '1' to enable interrupt for ENDEPOUT[2] event</description>
41599 <lsb>2</lsb>
41600 <msb>2</msb>
41652 <description>Write '1' to disable interrupt for ENDEPIN[2] event</description>
41922 <description>Write '1' to disable interrupt for ENDEPOUT[2] event</description>
42426 <lsb>2</lsb>
42427 <msb>2</msb>
42741 <lsb>2</lsb>
42742 <msb>2</msb>
43014 <value>2</value>
43042 <value>2</value>
43140 <description>SETUP data, byte 2, LSB of wValue</description>
43147 <description>SETUP data, byte 2, LSB of wValue</description>
43355 <value>2</value>
43377 <msb>2</msb>
43416 <value>2</value>
43467 <description>Enable IN endpoint 2</description>
43468 <lsb>2</lsb>
43469 <msb>2</msb>
43473 <description>Disable endpoint IN 2 (no response to IN tokens)</description>
43478 <description>Enable endpoint IN 2 (response to IN tokens)</description>
43638 <description>Enable OUT endpoint 2</description>
43639 <lsb>2</lsb>
43640 <msb>2</msb>
43644 <description>Disable endpoint OUT 2 (no response to OUT tokens)</description>
43649 <description>Enable endpoint OUT 2 (response to OUT tokens)</description>
43776 <msb>2</msb>
44472 <value>2</value>
44743 <msb>2</msb>
44758 <value>2</value>
44791 <value>2</value>
44922 <lsb>2</lsb>
44923 <msb>2</msb>
45028 <value>2</value>
45100 <name>2B</name>
45102 <value>2</value>
45242 <description>Data byte 2</description>
45378 <description>Pin 2</description>
45379 <lsb>2</lsb>
45380 <msb>2</msb>
45981 <description>Pin 2</description>
45982 <lsb>2</lsb>
45983 <msb>2</msb>
46854 <description>Pin 2</description>
46855 <lsb>2</lsb>
46856 <msb>2</msb>
47708 <description>Pin 2</description>
47709 <lsb>2</lsb>
47710 <msb>2</msb>
48292 <description>Pin 2</description>
48293 <lsb>2</lsb>
48294 <msb>2</msb>
48895 <description>Set as output pin 2</description>
48896 <lsb>2</lsb>
48897 <msb>2</msb>
49768 <description>Set as input pin 2</description>
49769 <lsb>2</lsb>
49770 <msb>2</msb>
50623 <lsb>2</lsb>
50624 <msb>2</msb>
51236 <lsb>2</lsb>
51275 <value>2</value>
51318 <value>2</value>
51333 <description>GPIO Port 2</description>
51375 <value>2</value>
51479 <msb>2</msb>
51489 <value>2</value>