Lines Matching +full:2 +full:mbps

11 2. Redistributions in binary form must reproduce the above copyright
79 /* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */
80 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
103 /* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */
104 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
349 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
350 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
448 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
449 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
540 /* Bit 2 : Write '1' to enable interrupt for ERROR event */
541 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
564 /* Bit 2 : Write '1' to disable interrupt for ERROR event */
565 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
601 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
615 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
616 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
617 #define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */
668 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
669 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
670 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */
863 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
873 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
895 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
972 /* Bit 2 : Shortcut between DOWN event and STOP task */
973 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
999 /* Bit 2 : Enable or disable interrupt for UP event */
1000 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
1027 /* Bit 2 : Write '1' to enable interrupt for UP event */
1028 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
1058 /* Bit 2 : Write '1' to disable interrupt for UP event */
1059 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
1095 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1100 /* Bits 2..0 : Analog pin select */
1105 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
1110 #define COMP_PSEL_PSEL_VddDiv2 (7UL) /*!< VDD/2 selected as analog input */
1115 /* Bits 2..0 : Reference select */
1120 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 …
1127 /* Bits 2..0 : External analog reference select */
1132 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference …
1164 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1347 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
1348 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1459 /* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */
1460 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1574 /* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */
1575 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1906 /* Bit 2 : Write '1' to enable interrupt for IN[2] event */
1907 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
1972 /* Bit 2 : Write '1' to disable interrupt for IN[2] event */
1973 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
2007 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode:…
2042 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
2278 /* Bit 2 : Pin 2 */
2279 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2502 /* Bit 2 : Pin 2 */
2503 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2729 /* Bit 2 : Pin 2 */
2730 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2927 /* Bit 2 : Pin 2 */
2928 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3122 /* Bit 2 : Pin 2 */
3123 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3346 /* Bit 2 : Set as output pin 2 */
3347 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3573 /* Bit 2 : Set as input pin 2 */
3574 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3771 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to cle…
3772 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3805 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
3813 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
3820 /* Bits 3..2 : Pull configuration */
3821 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
3881 /* Bit 2 : Enable or disable interrupt for END event */
3882 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
3902 /* Bit 2 : Write '1' to enable interrupt for END event */
3903 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
3926 /* Bit 2 : Write '1' to disable interrupt for END event */
3927 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
4097 /* Bit 2 : Write '1' to enable interrupt for POFWARN event */
4098 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4121 /* Bit 2 : Write '1' to disable interrupt for POFWARN event */
4122 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4149 /* Bit 2 : Reset from soft reset detected */
4150 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
4491 /* Bit 2 : Enable or disable channel 2 */
4492 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
4715 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
4716 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
4942 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
4943 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
5154 /* Bit 2 : Include or exclude channel 2 */
5155 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
5254 /* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
5255 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
5305 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
5306 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5355 /* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */
5356 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5407 /* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */
5408 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5449 /* Bits 2..0 : Prescaler of PWM_CLK */
5453 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */
5454 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */
5455 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */
5474 …ER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
5475 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4t…
5476 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th …
5630 /* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
5631 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
5665 /* Bit 2 : Write '1' to enable interrupt for ACCOF event */
5666 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
5703 /* Bit 2 : Write '1' to disable interrupt for ACCOF event */
5704 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
5750 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
5775 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
5855 ….0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
6043 /* Bit 2 : Shortcut between DISABLED event and TXEN task */
6044 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
6120 /* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */
6121 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
6200 /* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */
6201 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
6233 /* Bits 2..0 : Received address */
6247 /* Bits 2..0 : Device address match index */
6295 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
6297 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */
6374 /* Bits 23..16 : Address prefix 2. */
6408 /* Bits 2..0 : Transmit address select */
6445 /* Bit 2 : Enable or disable reception on logical address 2. */
6446 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
6477 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
6516 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
6575 /* Bit 10 : TxAdd for device address 2 */
6617 /* Bit 2 : Enable or disable device address matching using device address 2 */
6618 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
6643 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
6793 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */
6838 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */
6882 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
6922 /* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */
6967 /* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */
7174 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
7180 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
7228 /* Bit 2 : Enable or disable interrupt for DONE event */
7229 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
7319 /* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */
7326 /* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */
7382 /* Bit 2 : Write '1' to enable interrupt for DONE event */
7383 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
7476 /* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */
7483 /* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */
7539 /* Bit 2 : Write '1' to disable interrupt for DONE event */
7540 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
7586 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
7603 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
7619 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE nu…
7632 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
7648 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
7650 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
7652 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
7660 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
7661 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
7668 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
7669 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
7685 /* Bits 2..0 : Set the resolution */
7690 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
7700 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
7701 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
7952 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
7953 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
7954 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
7955 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
7981 /* Bits 2..0 : List type */
8011 /* Bits 2..0 : List type */
8020 /* Bit 2 : Serial clock (SCK) polarity */
8021 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
8087 /* Bit 2 : Shortcut between END event and ACQUIRE task */
8088 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
8149 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
8176 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
8275 /* Bit 2 : Serial clock (SCK) polarity */
8276 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
8367 /* Description: Slope of 2nd piece wise linear function */
8369 /* Bits 11..0 : Slope of 2nd piece wise linear function */
8409 /* Description: y-intercept of 2nd piece wise linear function */
8411 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
8451 /* Description: End point of 2nd piece wise linear function */
8453 /* Bits 7..0 : End point of 2nd piece wise linear function */
8552 /* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
8588 /* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
8589 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
8630 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */
8675 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */
8704 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
8714 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
9010 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
9011 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
9097 /* Bits 2..0 : List type */
9127 /* Bits 2..0 : List type */
9374 /* Bit 2 : NACK sent after receiving a data byte */
9375 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
9681 /* Bit 2 : Enable or disable interrupt for RXDRDY event */
9682 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
9758 /* Bit 2 : Write '1' to enable interrupt for RXDRDY event */
9759 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
9838 /* Bit 2 : Write '1' to disable interrupt for RXDRDY event */
9839 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
9868 /* Bit 2 : Framing error occurred */
9869 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
10162 /* Bit 2 : Request status for RR[2] register */
10163 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
10165 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are alre…
10166 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not y…
10220 /* Bit 2 : Enable or disable RR[2] register */
10221 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
10223 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
10224 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */