Lines Matching +full:2 +full:mbps

11 2. Redistributions in binary form must reproduce the above copyright
44 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
45 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
68 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
69 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
171 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
178 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
179 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
191 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescal…
194 /* Bits 4..2 : ADC input selection. */
195 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
198 …gInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as…
200 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescalin…
242 /* Bit 2 : Enable interrupt on ERROR event. */
243 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
266 /* Bit 2 : Disable interrupt on ERROR event. */
267 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
436 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and…
446 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock…
456 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
750 /* Bit 2 : Pin 2. */
751 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
974 /* Bit 2 : Pin 2. */
975 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
1201 /* Bit 2 : Pin 2. */
1202 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
1399 /* Bit 2 : Pin 2. */
1400 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
1594 /* Bit 2 : Pin 2. */
1595 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
1818 /* Bit 2 : Set as output pin 2. */
1819 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2045 /* Bit 2 : Set as input pin 2. */
2046 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2088 /* Bits 3..2 : Pull-up or -down configuration. */
2089 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
2128 /* Bit 2 : Enable interrupt on IN[2] event. */
2129 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
2166 /* Bit 2 : Disable interrupt on IN[2] event. */
2167 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
2243 /* Bit 2 : Shortcut between DOWN event and STOP task. */
2244 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
2271 /* Bit 2 : Enable interrupt on UP event. */
2272 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
2302 /* Bit 2 : Disable interrupt on UP event. */
2303 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
2344 /* Bits 2..0 : Analog input pin select. */
2349 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
2359 /* Bits 2..0 : Reference select. */
2363 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler …
2364 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescale…
2388 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
2514 /* Bit 2 : UART0 region configuration. */
2515 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
2738 /* Bit 2 : Protection enable for region 2. */
2739 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
2965 /* Bit 2 : Protection enable for region 34. */
2966 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
3051 /* Bit 2 : Enable interrupt on POFWARN event. */
3052 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
3061 /* Bit 2 : Disable interrupt on POFWARN event. */
3062 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
3095 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
3096 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
3122 /* Bit 2 : RAM block 2 status. */
3123 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
3125 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
3126 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
3151 /* Bits 2..1 : Set threshold level. */
3217 /* Bit 16 : RAM block 2 behaviour in OFF mode. */
3220 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
3221 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
3229 /* Bit 0 : RAM block 2 behaviour in ON mode. */
3232 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
3233 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
3416 /* Bit 2 : Enable PPI channel 2. */
3417 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
3612 /* Bit 2 : Enable PPI channel 2. */
3613 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
3811 /* Bit 2 : Disable PPI channel 2. */
3812 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
3985 /* Bit 2 : Include CH2 in channel group. */
3986 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
4025 /* Bit 2 : Enable interrupt on ACCOF event. */
4026 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
4049 /* Bit 2 : Disable interrupt on ACCOF event. */
4050 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
4091 /* Bits 2..0 : Sample period. */
4106 /* Bits 31..0 : Last sample taken in compliment to 2. */
4113 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
4201 /* Bit 2 : Shortcut between DISABLED event and TXEN task.  */
4202 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
4264 /* Bit 2 : Enable interrupt on PAYLOAD event. */
4265 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
4330 /* Bit 2 : Disable interrupt on PAYLOAD event. */
4331 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
4363 /* Bits 2..0 : Logical address in which previous packet was received. */
4377 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. …
4410 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
4463 /* Bits 23..16 : Address prefix 2. Decision point: START task. */
4497 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
4534 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
4535 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
4566 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
4665 /* Bit 10 : TxAdd for device address 2. */
4707 /* Bit 2 : Enable or disable device address matching using device address 2. */
4708 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
4740 /* Description: Trim value override register 2. */
4742 /* Bits 31..0 : Trim value override 2. */
4847 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
4892 /* Bit 18 : Disable interrupt on COMPARE[2] event. */
4936 /* Bit 18 : COMPARE[2] event enable. */
4976 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
5021 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
5093 /* Bit 2 : Enable interrupt on READY event. */
5094 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
5103 /* Bit 2 : Disable interrupt on READY event. */
5104 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
5113 /* Bits 2..0 : Enable or disable SPI. */
5142 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
5143 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
5144 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
5145 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
5150 /* Bit 2 : Serial clock (SCK) polarity. */
5151 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
5184 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */
5185 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
5269 /* Bits 2..0 : Enable or disable SPIS. */
5306 /* Bit 2 : Serial clock (SCK) polarity. */
5307 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
5393 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */
5417 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
5418 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
5445 /* Bit 18 : Enable interrupt on COMPARE[2] */
5476 /* Bit 18 : Disable interrupt on COMPARE[2] */
5518 …prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
5583 /* Bit 2 : Enable interrupt on READY event. */
5584 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
5628 /* Bit 2 : Disable interrupt on RXDREADY event. */
5629 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
5645 /* Bit 2 : NACK received after sending a data byte. */
5646 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
5669 /* Bits 2..0 : Enable or disable W2M */
5758 /* Bit 2 : Enable interrupt on RXRDY event. */
5759 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
5803 /* Bit 2 : Disable interrupt on RXRDY event. */
5804 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
5834 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character …
5835 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
5858 /* Bits 2..0 : Enable or disable UART and acquire IOs. */
6028 /* Bit 2 : Request status for RR[2]. */
6029 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
6031 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has alrea…
6032 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not je…
6079 /* Bit 2 : Enable or disable RR[2] register. */
6080 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
6082 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
6083 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */