Lines Matching +full:2 +full:mbps

11 2. Redistributions in binary form must reproduce the above copyright
79 /* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */
80 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
103 /* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */
104 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
189 /* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */
190 #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
266 /* Bit 2 : Write '1' to enable interrupt for ERROR event */
267 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
290 /* Bit 2 : Write '1' to disable interrupt for ERROR event */
291 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
327 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
341 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
342 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
343 #define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */
394 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
395 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
396 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */
411 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session k…
459 /* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */
463 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL) /*!< CC310 operates in secure mode */
697 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
707 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
729 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
755 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< All trace signals (TRACECLK and TRACEDATA[n]…
762 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz trace port clock (TRACECLK = 4 MHz) …
763 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz trace port clock (TRACECLK = 2 MHz) …
848 /* Bit 2 : Shortcut between DOWN event and STOP task */
849 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
875 /* Bit 2 : Enable or disable interrupt for UP event */
876 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
903 /* Bit 2 : Write '1' to enable interrupt for UP event */
904 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
934 /* Bit 2 : Write '1' to disable interrupt for UP event */
935 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
971 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
976 /* Bits 2..0 : Analog pin select */
981 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
991 /* Bits 2..0 : Reference select */
996 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 …
1003 /* Bits 2..0 : External analog reference select */
1008 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference …
1040 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1236 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
1237 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1348 /* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */
1349 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1463 /* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */
1464 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1595 #define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */
1733 /* Bits 23..16 : Unique identifier byte 2 */
1838 /* Description: Sample count for ring oscillator 2 */
1840 /* Bits 31..0 : Sample count for ring oscillator 2 */
1942 /* Bit 2 : Write '1' to enable interrupt for IN[2] event */
1943 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
2008 /* Bit 2 : Write '1' to disable interrupt for IN[2] event */
2009 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
2043 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode:…
2111 /* Bit 2 : Enable or disable interrupt for STOPPED event */
2112 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2133 /* Bit 2 : Write '1' to enable interrupt for STOPPED event */
2134 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2157 /* Bit 2 : Write '1' to disable interrupt for STOPPED event */
2158 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2239 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
2249 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
2265 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
2293 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
2469 /* Bit 2 : Shortcut between DOWN event and STOP task */
2470 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
2497 /* Bit 2 : Write '1' to enable interrupt for UP event */
2498 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
2528 /* Bit 2 : Write '1' to disable interrupt for UP event */
2529 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
2570 /* Bits 2..0 : Analog pin select */
2575 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
2589 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
2590 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
2622 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
2704 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
2710 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
2722 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
2723 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2785 /* Bit 5 : Write '1' to enable interrupt for REGION[2].RA event */
2792 /* Bit 4 : Write '1' to enable interrupt for REGION[2].WA event */
2806 /* Bit 2 : Write '1' to enable interrupt for REGION[1].WA event */
2807 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2872 /* Bit 5 : Write '1' to disable interrupt for REGION[2].RA event */
2879 /* Bit 4 : Write '1' to disable interrupt for REGION[2].WA event */
2893 /* Bit 2 : Write '1' to disable interrupt for REGION[1].WA event */
2894 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2953 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
2959 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
2971 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
2972 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3034 /* Bit 5 : Write '1' to enable non-maskable interrupt for REGION[2].RA event */
3041 /* Bit 4 : Write '1' to enable non-maskable interrupt for REGION[2].WA event */
3055 /* Bit 2 : Write '1' to enable non-maskable interrupt for REGION[1].WA event */
3056 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3121 /* Bit 5 : Write '1' to disable non-maskable interrupt for REGION[2].RA event */
3128 /* Bit 4 : Write '1' to disable non-maskable interrupt for REGION[2].WA event */
3142 /* Bit 2 : Write '1' to disable non-maskable interrupt for REGION[1].WA event */
3143 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3340 /* Bit 2 : Subregion 2 in region n (write '1' to clear) */
3341 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3535 /* Bit 2 : Subregion 2 in region n (write '1' to clear) */
3536 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3592 /* Bit 5 : Enable/disable read access watch in region[2] */
3598 /* Bit 4 : Enable/disable write access watch in region[2] */
3610 /* Bit 2 : Enable/disable write access watch in region[1] */
3611 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3673 /* Bit 5 : Enable read access watch in region[2] */
3680 /* Bit 4 : Enable write access watch in region[2] */
3694 /* Bit 2 : Enable write access watch in region[1] */
3695 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3760 /* Bit 5 : Disable read access watch in region[2] */
3767 /* Bit 4 : Disable write access watch in region[2] */
3781 /* Bit 2 : Disable write access watch in region[1] */
3782 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
4007 /* Bit 2 : Include or exclude subregion 2 in region */
4008 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
4279 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */
4280 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4384 /* Bit 2 : Write '1' to enable interrupt for FIELDLOST event */
4385 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4492 /* Bit 2 : Write '1' to disable interrupt for FIELDLOST event */
4493 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4529 /* Bit 2 : Parity status of received frame */
4530 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
4544 /* Bits 2..0 : NfcTag state */
4548 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (2UL) /*!< RampUp */
4602 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAM…
4628 /* Bit 2 : Adding SoF or not in TX frames */
4629 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4653 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the…
4666 /* Bit 2 : SoF expected or not in RX frames */
4667 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4685 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but exc…
4754 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response i…
4763 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
4774 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
4794 /* Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol …
4795 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
4832 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
5097 /* Bit 2 : Pin 2 */
5098 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5321 /* Bit 2 : Pin 2 */
5322 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5548 /* Bit 2 : Pin 2 */
5549 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5746 /* Bit 2 : Pin 2 */
5747 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5941 /* Bit 2 : Pin 2 */
5942 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6165 /* Bit 2 : Set as output pin 2 */
6166 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6392 /* Bit 2 : Set as input pin 2 */
6393 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6590 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to cle…
6591 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6624 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
6632 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
6639 /* Bits 3..2 : Pull configuration */
6640 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
6700 /* Bit 2 : Enable or disable interrupt for END event */
6701 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
6721 /* Bit 2 : Write '1' to enable interrupt for END event */
6722 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
6745 /* Bit 2 : Write '1' to disable interrupt for END event */
6746 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
6978 /* Bit 2 : Write '1' to enable interrupt for POFWARN event */
6979 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
7023 /* Bit 2 : Write '1' to disable interrupt for POFWARN event */
7024 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
7069 /* Bit 2 : Reset from soft reset detected */
7070 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
7096 /* Bit 2 : RAM block 2 is on or off/powering up */
7097 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
7145 #define POWER_POFCON_THRESHOLDVDDH_V29 (2UL) /*!< Set threshold to 2.9 V */
7400 /* Bit 2 : Keep RAM section S2 on or off in System ON mode. */
7401 #define POWER_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
7566 /* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */
7567 #define POWER_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
7729 /* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */
7730 #define POWER_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
7939 /* Bit 2 : Enable or disable channel 2 */
7940 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
8163 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
8164 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
8390 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
8391 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
8602 /* Bit 2 : Include or exclude channel 2 */
8603 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
8702 /* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
8703 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
8753 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
8754 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8803 /* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */
8804 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8855 /* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */
8856 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8897 /* Bits 2..0 : Prescaler of PWM_CLK */
8901 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */
8902 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */
8903 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */
8922 …ER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
8923 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4t…
8924 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th …
9082 /* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
9083 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
9117 /* Bit 2 : Write '1' to enable interrupt for ACCOF event */
9118 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
9155 /* Bit 2 : Write '1' to disable interrupt for ACCOF event */
9156 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
9202 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
9227 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
9319 ….0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
9471 #define QSPI_ERASE_LEN_LEN_All (2UL) /*!< Erase all (flash command 0xC7) */
9608 #define QSPI_IFCONFIG0_WRITEOC_PP4O (2UL) /*!< Quad data line SPI. PP4O (opcode 0x32). */
9611 /* Bits 2..0 : Configure number of data lines and opcode used for reading. */
9616 #define QSPI_IFCONFIG0_READOC_READ2IO (2UL) /*!< Dual data line SPI. READ2IO (opcode 0xBB). */
9656 /* Bit 2 : Deep power-down mode (DPM) status of external flash. */
9657 #define QSPI_STATUS_DPM_Pos (2UL) /*!< Position of DPM field. */
9693 #define QSPI_ADDRCONF_MODE_OpByte0 (2UL) /*!< Send opcode, byte0. */
9746 #define QSPI_CINSTRCONF_LENGTH_2B (2UL) /*!< Send opcode, CINSTRDAT0.BYTE0. */
9766 /* Bits 23..16 : Data byte 2 */
10152 /* Bit 2 : Shortcut between DISABLED event and TXEN task */
10153 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
10306 /* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */
10307 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
10463 /* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */
10464 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
10496 /* Bits 2..0 : Received address */
10510 /* Bits 2..0 : Device address match index */
10517 /* Bits 2..1 : Status on what rate packet is received with in Long Range */
10556 #define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x2UL) /*!< +2 dBm */
10578 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
10580 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s BLE */
10603 #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */
10676 /* Bits 23..16 : Address prefix 2. */
10710 /* Bits 2..0 : Transmit address select */
10747 /* Bit 2 : Enable or disable reception on logical address 2. */
10748 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
10773 #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Start…
10780 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
10819 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
10878 /* Bit 10 : TxAdd for device address 2 */
10920 /* Bit 2 : Enable or disable device address matching using device address 2 */
10921 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
10946 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
10990 /* Bits 2..0 : CCA mode of operation */
10995 #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */
11141 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */
11186 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */
11230 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
11270 /* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */
11315 /* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */
11522 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
11528 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
11576 /* Bit 2 : Enable or disable interrupt for DONE event */
11577 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
11667 /* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */
11674 /* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */
11730 /* Bit 2 : Write '1' to enable interrupt for DONE event */
11731 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
11824 /* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */
11831 /* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */
11887 /* Bit 2 : Write '1' to disable interrupt for DONE event */
11888 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
11934 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
11952 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
11969 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE nu…
11982 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
11998 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
12000 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
12002 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
12010 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
12011 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
12018 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
12019 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
12035 /* Bits 2..0 : Set the resolution */
12040 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bits */
12050 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
12051 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
12107 /* Bit 2 : Write '1' to enable interrupt for READY event */
12108 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
12117 /* Bit 2 : Write '1' to disable interrupt for READY event */
12118 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
12207 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
12208 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
12209 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
12210 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
12215 /* Bit 2 : Serial clock (SCK) polarity */
12216 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
12486 #define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */
12487 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
12488 #define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */
12489 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
12490 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
12491 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
12556 /* Bit 2 : Serial clock (SCK) polarity */
12557 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
12577 /* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz…
12670 /* Bit 2 : Shortcut between END event and ACQUIRE task */
12671 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
12732 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
12759 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
12874 /* Bit 2 : Serial clock (SCK) polarity */
12875 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
12966 /* Description: Slope of 2nd piece wise linear function */
12968 /* Bits 11..0 : Slope of 2nd piece wise linear function */
13008 /* Description: y-intercept of 2nd piece wise linear function */
13010 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
13050 /* Description: End point of 2nd piece wise linear function */
13052 /* Bits 7..0 : End point of 2nd piece wise linear function */
13151 /* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
13187 /* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
13188 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
13229 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */
13274 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */
13303 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
13313 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
13457 /* Bit 2 : Write '1' to enable interrupt for RXDREADY event */
13458 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
13502 /* Bit 2 : Write '1' to disable interrupt for RXDREADY event */
13503 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
13519 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
13520 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
13890 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
13891 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
13985 /* Bits 2..0 : List type */
14015 /* Bits 2..0 : List type */
14262 /* Bit 2 : NACK sent after receiving a data byte */
14263 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
14515 /* Bit 2 : Write '1' to enable interrupt for RXDRDY event */
14516 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
14560 /* Bit 2 : Write '1' to disable interrupt for RXDRDY event */
14561 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
14590 /* Bit 2 : Framing error occurred */
14591 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
14921 /* Bit 2 : Enable or disable interrupt for RXDRDY event */
14922 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
14998 /* Bit 2 : Write '1' to enable interrupt for RXDRDY event */
14999 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15078 /* Bit 2 : Write '1' to disable interrupt for RXDRDY event */
15079 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15108 /* Bit 2 : Framing error occurred */
15109 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
15369 /* Bits 2..0 : Output voltage from of REG0 regulator stage. The maximum output voltage from this st…
15374 #define UICR_REGOUT0_VOUT_2V4 (2UL) /*!< 2.4 V */
15539 /* Bit 2 : Shortcut between EP0DATADONE event and EP0STATUS task */
15540 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */
15620 /* Bit 14 : Enable or disable interrupt for ENDEPOUT[2] event */
15680 /* Bit 4 : Enable or disable interrupt for ENDEPIN[2] event */
15692 /* Bit 2 : Enable or disable interrupt for ENDEPIN[0] event */
15693 #define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
15783 /* Bit 14 : Write '1' to enable interrupt for ENDEPOUT[2] event */
15853 /* Bit 4 : Write '1' to enable interrupt for ENDEPIN[2] event */
15867 /* Bit 2 : Write '1' to enable interrupt for ENDEPIN[0] event */
15868 #define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
15961 /* Bit 14 : Write '1' to disable interrupt for ENDEPOUT[2] event */
16031 /* Bit 4 : Write '1' to disable interrupt for ENDEPIN[2] event */
16045 /* Bit 2 : Write '1' to disable interrupt for ENDEPIN[0] event */
16046 #define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
16210 /* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16211 #define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
16303 /* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16304 #define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
16336 #define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL) /*!< Vendor */
16343 #define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL) /*!< Endpoint */
16365 /* Description: SETUP data, byte 2, LSB of wValue */
16367 /* Bits 7..0 : SETUP data, byte 2, LSB of wValue */
16451 #define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */
16462 #define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */
16470 /* Bits 2..0 : Select bulk endpoint number */
16513 /* Bit 2 : Enable IN endpoint 2 */
16514 #define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */
16516 #define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */
16517 #define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */
16570 /* Bit 2 : Enable OUT endpoint 2 */
16571 #define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */
16573 #define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */
16574 #define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */
16603 /* Bits 2..0 : Select endpoint number */
16805 /* Bit 2 : Request status for RR[2] register */
16806 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
16808 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are alre…
16809 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not y…
16863 /* Bit 2 : Enable or disable RR[2] register */
16864 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
16866 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
16867 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */