Lines Matching +full:2 +full:mbps

11 2. Redistributions in binary form must reproduce the above copyright
44 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
45 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
68 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
69 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
314 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
315 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
509 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
510 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
537 /* Description: Block protect configuration register 2 */
713 /* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
714 #define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
908 /* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
909 #define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
942 /* Bit 2 : Write '1' to Enable interrupt for ERROR event */
943 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
966 /* Bit 2 : Write '1' to Disable interrupt for ERROR event */
967 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
1003 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1018 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
1167 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1177 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1199 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1216 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.2…
1223 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) …
1224 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) …
1245 /* Bit 2 : Shortcut between DOWN event and STOP task */
1246 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
1272 /* Bit 2 : Enable or disable interrupt for UP event */
1273 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
1300 /* Bit 2 : Write '1' to Enable interrupt for UP event */
1301 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
1331 /* Bit 2 : Write '1' to Disable interrupt for UP event */
1332 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
1368 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1373 /* Bits 2..0 : Analog pin select */
1378 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
1388 /* Bits 2..0 : Reference select */
1393 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 …
1400 /* Bits 2..0 : External analog reference select */
1405 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference …
1437 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1456 #define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
1589 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
1590 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1701 /* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
1702 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1816 /* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
1817 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
2075 /* Bits 23..16 : Unique identifier byte 2 */
2193 /* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
2194 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
2259 /* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
2260 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
2294 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode:…
2321 /* Bit 2 : Enable or disable interrupt for STOPPED event */
2322 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2343 /* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
2344 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2367 /* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
2368 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2449 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
2459 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
2475 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
2503 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
2610 /* Bit 2 : Shortcut between DOWN event and STOP task */
2611 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
2638 /* Bit 2 : Write '1' to Enable interrupt for UP event */
2639 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
2669 /* Bit 2 : Write '1' to Disable interrupt for UP event */
2670 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
2711 /* Bits 2..0 : Analog pin select */
2716 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
2730 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
2731 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
2763 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
2817 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
2823 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
2835 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
2836 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2898 /* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
2905 /* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
2919 /* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
2920 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2985 /* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
2992 /* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
3006 /* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
3007 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3066 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
3072 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
3084 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
3085 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3147 /* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
3154 /* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
3168 /* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
3169 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3234 /* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
3241 /* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
3255 /* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
3256 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3453 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
3454 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3648 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
3649 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3705 /* Bit 5 : Enable/disable read access watch in region[2] */
3711 /* Bit 4 : Enable/disable write access watch in region[2] */
3723 /* Bit 2 : Enable/disable write access watch in region[1] */
3724 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3786 /* Bit 5 : Enable read access watch in region[2] */
3793 /* Bit 4 : Enable write access watch in region[2] */
3807 /* Bit 2 : Enable write access watch in region[1] */
3808 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3873 /* Bit 5 : Disable read access watch in region[2] */
3880 /* Bit 4 : Disable write access watch in region[2] */
3894 /* Bit 2 : Disable write access watch in region[1] */
3895 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
4120 /* Bit 2 : Include or exclude subregion 2 in region */
4121 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
4232 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */
4233 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4337 /* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
4338 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4445 /* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
4446 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4473 /* Bit 2 : Field level is too high at max load resistance */
4474 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
4490 /* Bit 2 : Parity status of received frame */
4491 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
4546 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAM…
4572 /* Bit 2 : Adding SoF or not in TX frames */
4573 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4597 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the…
4610 /* Bit 2 : SoF expected or not in RX frames */
4611 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4629 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but exc…
4689 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response i…
4698 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
4709 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
4729 /* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
4730 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
4760 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
5011 /* Bit 2 : Pin 2 */
5012 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5235 /* Bit 2 : Pin 2 */
5236 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5462 /* Bit 2 : Pin 2 */
5463 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5660 /* Bit 2 : Pin 2 */
5661 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5855 /* Bit 2 : Pin 2 */
5856 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6079 /* Bit 2 : Set as output pin 2 */
6080 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6306 /* Bit 2 : Set as input pin 2 */
6307 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6504 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to cle…
6505 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6538 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
6546 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
6553 /* Bits 3..2 : Pull configuration */
6554 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
6579 /* Bit 2 : Enable or disable interrupt for END event */
6580 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
6600 /* Bit 2 : Write '1' to Enable interrupt for END event */
6601 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
6624 /* Bit 2 : Write '1' to Disable interrupt for END event */
6625 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
6760 /* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
6761 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
6784 /* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
6785 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
6824 /* Bit 2 : Reset from soft reset detected */
6825 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
6851 /* Bit 2 : RAM block 2 is on or off/powering up */
6852 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
6952 /* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
6964 /* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
7233 /* Bit 2 : Enable or disable channel 2 */
7234 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
7457 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
7458 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
7684 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
7685 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
7896 /* Bit 2 : Include or exclude channel 2 */
7897 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
7940 /* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
7941 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
7991 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
7992 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8041 /* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
8042 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8093 /* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
8094 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8135 /* Bits 2..0 : Pre-scaler of PWM_CLK */
8139 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by   2 ( 8MHz) */
8140 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by   4 ( 4MHz) */
8141 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by   8 ( 2MHz) */
8160 …ER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
8161 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4t…
8162 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th …
8246 /* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
8247 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
8281 /* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
8282 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
8319 /* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
8320 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
8366 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
8391 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
8471 ….0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
8519 /* Bit 2 : Shortcut between DISABLED event and TXEN task */
8520 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
8596 /* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
8597 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
8676 /* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
8677 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
8709 /* Bits 2..0 : Received address */
8723 /* Bits 2..0 : Device address match index */
8771 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
8772 #define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator -  250 kbit/s Nordic proprieta…
8774 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */
8851 /* Bits 23..16 : Address prefix 2. */
8885 /* Bits 2..0 : Transmit address select */
8922 /* Bit 2 : Enable or disable reception on logical address 2. */
8923 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
8954 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
8993 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
9052 /* Bit 10 : TxAdd for device address 2 */
9094 /* Bit 2 : Enable or disable device address matching using device address 2 */
9095 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
9120 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
9200 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
9245 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
9289 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
9329 /* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
9374 /* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
9497 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
9503 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
9551 /* Bit 2 : Enable or disable interrupt for DONE event */
9552 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
9642 /* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
9649 /* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
9705 /* Bit 2 : Write '1' to Enable interrupt for DONE event */
9706 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
9799 /* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
9806 /* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
9862 /* Bit 2 : Write '1' to Disable interrupt for DONE event */
9863 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
9909 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
9926 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
9942 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE nu…
9955 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
9971 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
9973 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
9975 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
9983 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
9984 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
9991 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
9992 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
10008 /* Bits 2..0 : Set the resolution */
10013 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
10023 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
10024 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
10073 /* Bit 2 : Write '1' to Enable interrupt for READY event */
10074 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
10083 /* Bit 2 : Write '1' to Disable interrupt for READY event */
10084 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
10146 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
10147 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
10148 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
10149 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
10154 /* Bit 2 : Serial clock (SCK) polarity */
10155 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
10318 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
10319 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
10320 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
10321 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
10347 /* Bits 2..0 : List type */
10377 /* Bits 2..0 : List type */
10386 /* Bit 2 : Serial clock (SCK) polarity */
10387 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
10418 /* Bit 2 : Shortcut between END event and ACQUIRE task */
10419 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
10480 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
10507 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
10606 /* Bit 2 : Serial clock (SCK) polarity */
10607 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
10677 /* Description: Slope of 2nd piece wise linear function */
10679 /* Bits 11..0 : Slope of 2nd piece wise linear function */
10719 /* Description: y-intercept of 2nd piece wise linear function */
10721 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
10761 /* Description: End point of 2nd piece wise linear function */
10763 /* Bits 7..0 : End point of 2nd piece wise linear function */
10813 /* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
10849 /* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
10850 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
10891 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
10936 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
10965 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
10975 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
11042 /* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
11043 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
11087 /* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
11088 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
11104 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
11105 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
11370 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
11371 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
11457 /* Bits 2..0 : List type */
11487 /* Bits 2..0 : List type */
11657 /* Bit 2 : NACK sent after receiving a data byte */
11658 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
11825 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
11826 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
11870 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
11871 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
11900 /* Bit 2 : Framing error occurred */
11901 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
12083 /* Bit 2 : Enable or disable interrupt for RXDRDY event */
12084 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
12160 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
12161 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
12240 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
12241 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
12270 /* Bit 2 : Framing error occurred */
12271 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
12553 /* Bit 2 : Request status for RR[2] register */
12554 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
12556 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are alre…
12557 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not y…
12611 /* Bit 2 : Enable or disable RR[2] register */
12612 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
12614 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
12615 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */