lsqueue - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/mem/lsqueue

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
9398e65a	14-Apr-2024	Anzooooo <[email protected]>	LsqEnqCtrl: fix width of offset when allocate lqptr/sqptr /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
55178b77	12-Apr-2024	weiding liu <[email protected]>	VLSU: support of vector store/load exception /XiangShan/difftest /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala LSQWrapper.scala LoadExceptionBuffer.scala LoadQueue.scala LoadQueueReplay.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
9ae95eda	02-Apr-2024	Anzooooo <[email protected]>	Difftest: add new VLSU difftest support /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala LSQWrapper.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
32977e5d	02-Apr-2024	Anzooooo <[email protected]>	Dispatch2Iq, package: make the encoding and decoding more standardized /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala LSQWrapper.scala StoreQueue.scala VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala
d8be2368	10-Apr-2024	weiding liu <[email protected]>	VLSU, lsq: fix calcualte of enqptr when redirect StoreQueue.scala VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
b2d6d8e7	09-Apr-2024	good-circle <[email protected]>	VLSU: Add performance counters and parameters /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala StoreQueue.scala VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
243bee57	09-Apr-2024	weiding liu <[email protected]>	VLSU,LSQ: fix lqIdx/sqIdx calcualte when allocate entries StoreQueue.scala VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
83605159	07-Apr-2024	weiding liu <[email protected]>	VLSU: fix bug for transmit vector data and vector mask to StoreQueue StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
66d3a3c0	06-Apr-2024	weiding liu <[email protected]>	VLSU, StoreQueue: init vecMbCommit when allocate new entries /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
315e1323	05-Apr-2024	good-circle <[email protected]>	VLSU, sbuffer: Fix vector store write to sbuffer logic /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
c4b35e9b	05-Apr-2024	good-circle <[email protected]>	VLSU, storequeue: Should not judge exception when tlb miss StoreQueue.scala
21e4bcfb	05-Apr-2024	good-circle <[email protected]>	VLSU, loadqueue: Fix bug of exceptionbuffer enq logic /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
5da48be8	03-Apr-2024	good-circle <[email protected]>	VLSU: Fix bug of storequeue commit logic * more bugs need to be further tested /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
f7eafebe	01-Apr-2024	weiding liu <[email protected]>	VLSU,StoreQueue: fix bug of enq /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
157da8c8	01-Apr-2024	weiding liu <[email protected]>	VLSU,StoreQueue: add initialization for vector store flags /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
375ed6a9	30-Mar-2024	weiding liu <[email protected]>	VLSU: add support that replay vector load mask /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala LoadQueue.scala LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
b7618691	29-Mar-2024	weiding liu <[email protected]>	VLSU: fix bugs of build and connect /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala LoadQueue.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
3ea758f9	31-Mar-2024	Anzo <[email protected]>	VLSU: fix allocated LSQ entries (#2829) /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala StoreQueue.scala VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/package.scala
26af847e	25-Mar-2024	good-circle <[email protected]>	rv64v: implement lsu & lsq vector datapath /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala LSQWrapper.scala LoadExceptionBuffer.scala LoadQueue.scala LoadQueueRAR.scala LoadQueueRAW.scala LoadQueueReplay.scala StoreQueue.scala UncacheBuffer.scala VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
f3a9fb05	27-Mar-2024	Anzo <[email protected]>	rv64v: add support for vlsu continuous 'uop' (#2816) add LSQ backpressure logic and 'uop' continuous application LSQ entries logic /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala LSQWrapper.scala StoreQueue.scala VirtualLoadQueue.scala
3952421b	24-Mar-2024	weiding liu <[email protected]>	rv64v: rewrite VLSU uop split in VSplitImp, flow merge in VMergeBufferImp, uop issued out of order /XiangShan/huancun /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/ClockGate.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/AgeDetector.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/NewAgeDetector.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/utility /XiangShan/yunsuan
aebc38d1	12-Apr-2024	sfencevma <[email protected]>	delay paddr/mask check one more cycle /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/build.sc /XiangShan/ready-to-run /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Generator.scala /XiangShan/src/main/scala/utils/ClockGate.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/LsInfo.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/Og2ForVector.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobEnqPtrWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
e25e4d90	11-Apr-2024	Xuan Hu <[email protected]>	Merge remote-tracking branch 'upstream/master' into tmp-master TODO: add gpaddr data path from frontend to backend /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/ready-to-run /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala LSQWrapper.scala LoadExceptionBuffer.scala LoadQueue.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/utility
c3d5cfb3	16-Sep-2023	peixiaokun <[email protected]>	RVH: compile emu successfully /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala LoadExceptionBuffer.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
cca17e78	11-Sep-2023	peixiaokun <[email protected]>	RVH: fix some bugs about compilation /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
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