1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.ctrlblock.{DebugLsInfoBundle, LsTopdownInfo} 30import xiangshan.backend.rob.RobPtr 31import xiangshan.backend.fu._ 32import xiangshan.backend.fu.util.SdtrigExt 33import xiangshan.cache._ 34import xiangshan.cache.wpu.ReplayCarry 35import xiangshan.cache.mmu.{TlbCmd, TlbHintReq, TlbReq, TlbRequestIO, TlbResp} 36import xiangshan.mem.mdp._ 37 38class HybridUnit(implicit p: Parameters) extends XSModule 39 with HasLoadHelper 40 with HasPerfEvents 41 with HasDCacheParameters 42 with HasCircularQueuePtrHelper 43 with HasVLSUParameters 44 with SdtrigExt 45{ 46 val io = IO(new Bundle() { 47 // control 48 val redirect = Flipped(ValidIO(new Redirect)) 49 val csrCtrl = Flipped(new CustomCSRCtrlIO) 50 51 // flow in 52 val lsin = Flipped(Decoupled(new MemExuInput)) 53 54 // flow out 55 val ldout = DecoupledIO(new MemExuOutput) 56 val stout = DecoupledIO(new MemExuOutput) 57 58 val ldu_io = new Bundle() { 59 // dcache 60 val dcache = new DCacheLoadIO 61 62 // data path 63 val sbuffer = new LoadForwardQueryIO 64 val vec_forward = new LoadForwardQueryIO 65 val lsq = new LoadToLsqIO 66 val tl_d_channel = Input(new DcacheToLduForwardIO) 67 val forward_mshr = Flipped(new LduToMissqueueForwardIO) 68 val refill = Flipped(ValidIO(new Refill)) 69 val tlb_hint = Flipped(new TlbHintReq) 70 val l2_hint = Input(Valid(new L2ToL1Hint)) 71 72 // fast wakeup 73 val fast_uop = ValidIO(new DynInst) // early wakeup signal generated in load_s1, send to RS in load_s2 74 75 // trigger 76 val trigger = Vec(TriggerNum, new LoadUnitTriggerIO) 77 78 // load to load fast path 79 val l2l_fwd_in = Input(new LoadToLoadIO) 80 val l2l_fwd_out = Output(new LoadToLoadIO) 81 82 val ld_fast_match = Input(Bool()) 83 val ld_fast_fuOpType = Input(UInt()) 84 val ld_fast_imm = Input(UInt(12.W)) 85 86 // hardware prefetch to l1 cache req 87 val prefetch_req = Flipped(ValidIO(new L1PrefetchReq)) 88 89 // iq cancel 90 val ldCancel = Output(new LoadCancelIO()) // use to cancel the uops waked by this load, and cancel load 91 92 // iq wakeup, use to wakeup consumer uop at load s2 93 val wakeup = ValidIO(new DynInst) 94 95 // load ecc error 96 val s3_dly_ld_err = Output(Bool()) // Note that io.s3_dly_ld_err and io.lsq.s3_dly_ld_err is different 97 98 // schedule error query 99 val stld_nuke_query = Flipped(Vec(StorePipelineWidth, Valid(new StoreNukeQueryIO))) 100 101 // queue-based replay 102 val replay = Flipped(Decoupled(new LsPipelineBundle)) 103 val lq_rep_full = Input(Bool()) 104 105 // misc 106 val s2_ptr_chasing = Output(Bool()) // provide right pc for hw prefetch 107 108 // Load fast replay path 109 val fast_rep_in = Flipped(Decoupled(new LqWriteBundle)) 110 val fast_rep_out = Decoupled(new LqWriteBundle) 111 112 // Load RAR rollback 113 val rollback = Valid(new Redirect) 114 115 // perf 116 val debug_ls = Output(new DebugLsInfoBundle) 117 val lsTopdownInfo = Output(new LsTopdownInfo) 118 } 119 120 val stu_io = new Bundle() { 121 val dcache = new DCacheStoreIO 122 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 123 val issue = Valid(new MemExuInput) 124 val lsq = ValidIO(new LsPipelineBundle) 125 val lsq_replenish = Output(new LsPipelineBundle()) 126 val stld_nuke_query = Valid(new StoreNukeQueryIO) 127 val st_mask_out = Valid(new StoreMaskBundle) 128 val debug_ls = Output(new DebugLsInfoBundle) 129 } 130 131 val vec_stu_io = new Bundle() { 132 val in = Flipped(DecoupledIO(new VecPipeBundle())) 133 val isFirstIssue = Input(Bool()) 134 val lsq = ValidIO(new LsPipelineBundle()) 135 val feedbackSlow = ValidIO(new VSFQFeedback) 136 } 137 138 // prefetch 139 val prefetch_train = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info to sms 140 val prefetch_train_l1 = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info to stream & stride 141 val canAcceptLowConfPrefetch = Output(Bool()) 142 val canAcceptHighConfPrefetch = Output(Bool()) 143 val correctMissTrain = Input(Bool()) 144 145 // data path 146 val tlb = new TlbRequestIO(2) 147 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 148 149 // rs feedback 150 val feedback_fast = ValidIO(new RSFeedback) // stage 2 151 val feedback_slow = ValidIO(new RSFeedback) // stage 3 152 }) 153 154 val StorePrefetchL1Enabled = EnableStorePrefetchAtCommit || EnableStorePrefetchAtIssue || EnableStorePrefetchSPB 155 val s1_ready, s2_ready, s3_ready, sx_can_go = WireInit(false.B) 156 157 // Pipeline 158 // -------------------------------------------------------------------------------- 159 // stage 0 160 // -------------------------------------------------------------------------------- 161 // generate addr, use addr to query DCache and DTLB 162 val s0_valid = Wire(Bool()) 163 val s0_dcache_ready = Wire(Bool()) 164 val s0_kill = Wire(Bool()) 165 val s0_vaddr = Wire(UInt(VAddrBits.W)) 166 val s0_mask = Wire(UInt((VLEN/8).W)) 167 val s0_uop = Wire(new DynInst) 168 val s0_has_rob_entry = Wire(Bool()) 169 val s0_rsIdx = Wire(UInt(log2Up(MemIQSizeMax).W)) 170 val s0_mshrid = Wire(UInt()) 171 val s0_try_l2l = Wire(Bool()) 172 val s0_rep_carry = Wire(new ReplayCarry(nWays)) 173 val s0_isFirstIssue = Wire(Bool()) 174 val s0_fast_rep = Wire(Bool()) 175 val s0_ld_rep = Wire(Bool()) 176 val s0_l2l_fwd = Wire(Bool()) 177 val s0_sched_idx = Wire(UInt()) 178 val s0_can_go = s1_ready 179 val s0_fire = s0_valid && s0_dcache_ready && s0_can_go 180 val s0_out = Wire(new LqWriteBundle) 181 // vector 182 val s0_isvec = WireInit(false.B) 183 val s0_vecActive = WireInit(true.B) 184 // val s0_flowPtr = WireInit(0.U.asTypeOf(new VsFlowPtr)) 185 val s0_isLastElem = WireInit(false.B) 186 187 // load flow select/gen 188 // src0: super load replayed by LSQ (cache miss replay) (io.ldu_io.replay) 189 // src1: fast load replay (io.ldu_io.fast_rep_in) 190 // src2: load replayed by LSQ (io.ldu_io.replay) 191 // src3: hardware prefetch from prefetchor (high confidence) (io.prefetch) 192 // src4: int read / software prefetch first issue from RS (io.in) 193 // src5: vec read first issue from RS (TODO) 194 // src6: load try pointchaising when no issued or replayed load (io.fastpath) 195 // src7: hardware prefetch from prefetchor (high confidence) (io.prefetch) 196 // priority: high to low 197 val s0_ld_flow = FuType.isLoad(s0_uop.fuType) || FuType.isVLoad(s0_uop.fuType) 198 val s0_rep_stall = io.lsin.valid && isAfter(io.ldu_io.replay.bits.uop.robIdx, io.lsin.bits.uop.robIdx) 199 val s0_super_ld_rep_valid = io.ldu_io.replay.valid && io.ldu_io.replay.bits.forward_tlDchannel 200 val s0_ld_fast_rep_valid = io.ldu_io.fast_rep_in.valid 201 val s0_ld_rep_valid = io.ldu_io.replay.valid && !io.ldu_io.replay.bits.forward_tlDchannel && !s0_rep_stall 202 val s0_high_conf_prf_valid = io.ldu_io.prefetch_req.valid && io.ldu_io.prefetch_req.bits.confidence > 0.U 203 val s0_int_iss_valid = io.lsin.valid // int flow first issue or software prefetch 204 val s0_vec_iss_valid = io.vec_stu_io.in.valid 205 val s0_l2l_fwd_valid = io.ldu_io.l2l_fwd_in.valid && io.ldu_io.ld_fast_match 206 val s0_low_conf_prf_valid = io.ldu_io.prefetch_req.valid && io.ldu_io.prefetch_req.bits.confidence === 0.U 207 dontTouch(s0_super_ld_rep_valid) 208 dontTouch(s0_ld_fast_rep_valid) 209 dontTouch(s0_ld_rep_valid) 210 dontTouch(s0_high_conf_prf_valid) 211 dontTouch(s0_int_iss_valid) 212 dontTouch(s0_vec_iss_valid) 213 dontTouch(s0_l2l_fwd_valid) 214 dontTouch(s0_low_conf_prf_valid) 215 216 // load flow source ready 217 val s0_super_ld_rep_ready = WireInit(true.B) 218 val s0_ld_fast_rep_ready = !s0_super_ld_rep_valid 219 val s0_ld_rep_ready = !s0_super_ld_rep_valid && 220 !s0_ld_fast_rep_valid 221 val s0_high_conf_prf_ready = !s0_super_ld_rep_valid && 222 !s0_ld_fast_rep_valid && 223 !s0_ld_rep_valid 224 225 val s0_int_iss_ready = !s0_super_ld_rep_valid && 226 !s0_ld_fast_rep_valid && 227 !s0_ld_rep_valid && 228 !s0_high_conf_prf_valid 229 230 val s0_vec_iss_ready = !s0_super_ld_rep_valid && 231 !s0_ld_fast_rep_valid && 232 !s0_ld_rep_valid && 233 !s0_high_conf_prf_valid && 234 !s0_int_iss_valid 235 236 val s0_l2l_fwd_ready = !s0_super_ld_rep_valid && 237 !s0_ld_fast_rep_valid && 238 !s0_ld_rep_valid && 239 !s0_high_conf_prf_valid && 240 !s0_int_iss_valid && 241 !s0_vec_iss_valid 242 243 val s0_low_conf_prf_ready = !s0_super_ld_rep_valid && 244 !s0_ld_fast_rep_valid && 245 !s0_ld_rep_valid && 246 !s0_high_conf_prf_valid && 247 !s0_int_iss_valid && 248 !s0_vec_iss_valid && 249 !s0_l2l_fwd_valid 250 dontTouch(s0_super_ld_rep_ready) 251 dontTouch(s0_ld_fast_rep_ready) 252 dontTouch(s0_ld_rep_ready) 253 dontTouch(s0_high_conf_prf_ready) 254 dontTouch(s0_int_iss_ready) 255 dontTouch(s0_vec_iss_ready) 256 dontTouch(s0_l2l_fwd_ready) 257 dontTouch(s0_low_conf_prf_ready) 258 259 // load flow source select (OH) 260 val s0_super_ld_rep_select = s0_super_ld_rep_valid && s0_super_ld_rep_ready 261 val s0_ld_fast_rep_select = s0_ld_fast_rep_valid && s0_ld_fast_rep_ready 262 val s0_ld_rep_select = s0_ld_rep_valid && s0_ld_rep_ready 263 val s0_hw_prf_select = s0_high_conf_prf_ready && s0_high_conf_prf_valid || 264 s0_low_conf_prf_ready && s0_low_conf_prf_valid 265 val s0_int_iss_select = s0_int_iss_ready && s0_int_iss_valid 266 val s0_vec_iss_select = s0_vec_iss_ready && s0_vec_iss_valid 267 val s0_l2l_fwd_select = s0_l2l_fwd_ready && s0_l2l_fwd_valid 268 dontTouch(s0_super_ld_rep_select) 269 dontTouch(s0_ld_fast_rep_select) 270 dontTouch(s0_ld_rep_select) 271 dontTouch(s0_hw_prf_select) 272 dontTouch(s0_int_iss_select) 273 dontTouch(s0_vec_iss_select) 274 dontTouch(s0_l2l_fwd_select) 275 276 s0_valid := (s0_super_ld_rep_valid || 277 s0_ld_fast_rep_valid || 278 s0_ld_rep_valid || 279 s0_high_conf_prf_valid || 280 s0_int_iss_valid || 281 s0_vec_iss_valid || 282 s0_l2l_fwd_valid || 283 s0_low_conf_prf_valid) && !s0_kill 284 285 // which is S0's out is ready and dcache is ready 286 val s0_try_ptr_chasing = s0_l2l_fwd_select 287 val s0_do_try_ptr_chasing = s0_try_ptr_chasing && s0_can_go && io.ldu_io.dcache.req.ready 288 val s0_ptr_chasing_vaddr = io.ldu_io.l2l_fwd_in.data(5, 0) +& io.ldu_io.ld_fast_imm(5, 0) 289 val s0_ptr_chasing_canceled = WireInit(false.B) 290 s0_kill := s0_ptr_chasing_canceled || (s0_out.uop.robIdx.needFlush(io.redirect) && !s0_try_ptr_chasing) 291 292 // prefetch related ctrl signal 293 val s0_prf = Wire(Bool()) 294 val s0_prf_rd = Wire(Bool()) 295 val s0_prf_wr = Wire(Bool()) 296 val s0_hw_prf = s0_hw_prf_select 297 298 io.canAcceptLowConfPrefetch := s0_low_conf_prf_ready 299 io.canAcceptHighConfPrefetch := s0_high_conf_prf_ready 300 301 if (StorePrefetchL1Enabled) { 302 s0_dcache_ready := Mux(s0_ld_flow, io.ldu_io.dcache.req.ready, io.stu_io.dcache.req.ready) 303 } else { 304 s0_dcache_ready := Mux(s0_ld_flow, io.ldu_io.dcache.req.ready, true.B) 305 } 306 307 // query DTLB 308 io.tlb.req.valid := s0_valid && s0_dcache_ready 309 io.tlb.req.bits.cmd := Mux(s0_prf, 310 Mux(s0_prf_wr, TlbCmd.write, TlbCmd.read), 311 Mux(s0_ld_flow, TlbCmd.read, TlbCmd.write) 312 ) 313 io.tlb.req.bits.vaddr := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.paddr, s0_vaddr) 314 io.tlb.req.bits.size := Mux(s0_isvec, io.vec_stu_io.in.bits.alignedType(1, 0), LSUOpType.size(s0_uop.fuOpType)) // may broken if use it in feature 315 io.tlb.req.bits.kill := s0_kill 316 io.tlb.req.bits.memidx.is_ld := s0_ld_flow 317 io.tlb.req.bits.memidx.is_st := !s0_ld_flow 318 io.tlb.req.bits.memidx.idx := s0_uop.lqIdx.value 319 io.tlb.req.bits.debug.robIdx := s0_uop.robIdx 320 io.tlb.req.bits.no_translate := s0_hw_prf_select // hw b.reqetch addr does not need to be translated 321 io.tlb.req.bits.debug.pc := s0_uop.pc 322 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 323 324 // query DCache 325 // for load 326 io.ldu_io.dcache.req.valid := s0_valid && s0_dcache_ready && s0_ld_flow 327 io.ldu_io.dcache.req.bits.cmd := Mux(s0_prf_rd, MemoryOpConstants.M_PFR, 328 Mux(s0_prf_wr, MemoryOpConstants.M_PFW, MemoryOpConstants.M_XRD)) 329 io.ldu_io.dcache.req.bits.vaddr := s0_vaddr 330 io.ldu_io.dcache.req.bits.mask := s0_mask 331 io.ldu_io.dcache.req.bits.data := DontCare 332 io.ldu_io.dcache.req.bits.isFirstIssue := s0_isFirstIssue 333 io.ldu_io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, LOAD_SOURCE.U) 334 io.ldu_io.dcache.req.bits.debug_robIdx := s0_uop.robIdx.value 335 io.ldu_io.dcache.req.bits.replayCarry := s0_rep_carry 336 io.ldu_io.dcache.req.bits.id := DontCare // TODO: update cache meta 337 io.ldu_io.dcache.pf_source := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.pf_source.value, L1_HW_PREFETCH_NULL) 338 io.ldu_io.dcache.is128Req := is128Bit(io.vec_stu_io.in.bits.alignedType) && io.vec_stu_io.in.valid && s0_vec_iss_select 339 340 // for store 341 io.stu_io.dcache.req.valid := s0_valid && s0_dcache_ready && !s0_ld_flow && !s0_prf 342 io.stu_io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 343 io.stu_io.dcache.req.bits.vaddr := s0_vaddr 344 io.stu_io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, STORE_SOURCE.U) 345 346 // load flow priority mux 347 def fromNullSource() = { 348 s0_vaddr := 0.U 349 s0_mask := 0.U 350 s0_uop := 0.U.asTypeOf(new DynInst) 351 s0_try_l2l := false.B 352 s0_has_rob_entry := false.B 353 s0_rsIdx := 0.U 354 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 355 s0_mshrid := 0.U 356 s0_isFirstIssue := false.B 357 s0_fast_rep := false.B 358 s0_ld_rep := false.B 359 s0_l2l_fwd := false.B 360 s0_prf := false.B 361 s0_prf_rd := false.B 362 s0_prf_wr := false.B 363 s0_sched_idx := 0.U 364 } 365 366 def fromFastReplaySource(src: LqWriteBundle) = { 367 s0_vaddr := src.vaddr 368 s0_mask := src.mask 369 s0_uop := src.uop 370 s0_try_l2l := false.B 371 s0_has_rob_entry := src.hasROBEntry 372 s0_rep_carry := src.rep_info.rep_carry 373 s0_mshrid := src.rep_info.mshr_id 374 s0_rsIdx := src.rsIdx 375 s0_isFirstIssue := false.B 376 s0_fast_rep := true.B 377 s0_ld_rep := src.isLoadReplay 378 s0_l2l_fwd := false.B 379 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 380 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 381 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 382 s0_sched_idx := src.schedIndex 383 } 384 385 def fromNormalReplaySource(src: LsPipelineBundle) = { 386 s0_vaddr := src.vaddr 387 s0_mask := genVWmask(src.vaddr, src.uop.fuOpType(1, 0)) 388 s0_uop := src.uop 389 s0_try_l2l := false.B 390 s0_has_rob_entry := true.B 391 s0_rsIdx := src.rsIdx 392 s0_rep_carry := src.replayCarry 393 s0_mshrid := src.mshrid 394 s0_isFirstIssue := false.B 395 s0_fast_rep := false.B 396 s0_ld_rep := true.B 397 s0_l2l_fwd := false.B 398 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 399 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 400 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 401 s0_sched_idx := src.schedIndex 402 } 403 404 def fromPrefetchSource(src: L1PrefetchReq) = { 405 s0_vaddr := src.getVaddr() 406 s0_mask := 0.U 407 s0_uop := DontCare 408 s0_try_l2l := false.B 409 s0_has_rob_entry := false.B 410 s0_rsIdx := 0.U 411 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 412 s0_mshrid := 0.U 413 s0_isFirstIssue := false.B 414 s0_fast_rep := false.B 415 s0_ld_rep := false.B 416 s0_l2l_fwd := false.B 417 s0_prf := true.B 418 s0_prf_rd := !src.is_store 419 s0_prf_wr := src.is_store 420 s0_sched_idx := 0.U 421 } 422 423 def fromIntIssueSource(src: MemExuInput) = { 424 s0_vaddr := src.src(0) + SignExt(src.uop.imm(11, 0), VAddrBits) 425 s0_mask := genVWmask(s0_vaddr, src.uop.fuOpType(1,0)) 426 s0_uop := src.uop 427 s0_try_l2l := false.B 428 s0_has_rob_entry := true.B 429 s0_rsIdx := src.iqIdx 430 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 431 s0_mshrid := 0.U 432 s0_isFirstIssue := true.B 433 s0_fast_rep := false.B 434 s0_ld_rep := false.B 435 s0_l2l_fwd := false.B 436 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 437 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 438 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 439 s0_sched_idx := 0.U 440 } 441 442 def fromVecIssueSource(src: VecPipeBundle) = { 443 // For now, vector port handles only vector store flows 444 s0_vaddr := src.vaddr 445 s0_mask := src.mask 446 s0_uop := src.uop 447 s0_try_l2l := false.B 448 s0_has_rob_entry := true.B 449 s0_rsIdx := 0.U 450 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 451 s0_mshrid := 0.U 452 // s0_isFirstIssue := src.isFirstIssue 453 s0_fast_rep := false.B 454 s0_ld_rep := false.B 455 s0_l2l_fwd := false.B 456 s0_prf := false.B 457 s0_prf_rd := false.B 458 s0_prf_wr := false.B 459 s0_sched_idx := 0.U 460 461 s0_isvec := true.B 462 s0_vecActive := io.vec_stu_io.in.bits.vecActive 463 // s0_flowPtr := io.vec_stu_io.in.bits.flowPtr 464 // s0_isLastElem := io.vec_stu_io.in.bits.isLastElem 465 } 466 467 def fromLoadToLoadSource(src: LoadToLoadIO) = { 468 s0_vaddr := Cat(src.data(XLEN-1, 6), s0_ptr_chasing_vaddr(5,0)) 469 s0_mask := genVWmask(s0_vaddr, io.ldu_io.ld_fast_fuOpType(1, 0)) 470 // When there's no valid instruction from RS and LSQ, we try the load-to-load forwarding. 471 // Assume the pointer chasing is always ld. 472 s0_uop.fuOpType := io.ldu_io.ld_fast_fuOpType 473 s0_try_l2l := true.B 474 // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx in S0 when trying pointchasing 475 // because these signals will be updated in S1 476 s0_has_rob_entry := false.B 477 s0_rsIdx := 0.U 478 s0_mshrid := 0.U 479 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 480 s0_isFirstIssue := true.B 481 s0_fast_rep := false.B 482 s0_ld_rep := false.B 483 s0_l2l_fwd := true.B 484 s0_prf := false.B 485 s0_prf_rd := false.B 486 s0_prf_wr := false.B 487 s0_sched_idx := 0.U 488 } 489 490 // set default 491 s0_uop := DontCare 492 when (s0_super_ld_rep_select) { fromNormalReplaySource(io.ldu_io.replay.bits) } 493 .elsewhen (s0_ld_fast_rep_select) { fromFastReplaySource(io.ldu_io.fast_rep_in.bits) } 494 .elsewhen (s0_ld_rep_select) { fromNormalReplaySource(io.ldu_io.replay.bits) } 495 .elsewhen (s0_hw_prf_select) { fromPrefetchSource(io.ldu_io.prefetch_req.bits) } 496 .elsewhen (s0_int_iss_select) { fromIntIssueSource(io.lsin.bits) } 497 .elsewhen (s0_vec_iss_select) { fromVecIssueSource(io.vec_stu_io.in.bits) } 498 .otherwise { 499 if (EnableLoadToLoadForward) { 500 fromLoadToLoadSource(io.ldu_io.l2l_fwd_in) 501 } else { 502 fromNullSource() 503 } 504 } 505 506 // address align check 507 val s0_addr_aligned = LookupTree(Mux(s0_isvec, io.vec_stu_io.in.bits.alignedType(1,0), s0_uop.fuOpType(1, 0)), List( 508 "b00".U -> true.B, //b 509 "b01".U -> (s0_vaddr(0) === 0.U), //h 510 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 511 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 512 ))// may broken if use it in feature 513 514 // accept load flow if dcache ready (tlb is always ready) 515 // TODO: prefetch need writeback to loadQueueFlag 516 s0_out := DontCare 517 s0_out.rsIdx := s0_rsIdx 518 s0_out.vaddr := s0_vaddr 519 s0_out.mask := s0_mask 520 s0_out.uop := s0_uop 521 s0_out.isFirstIssue := s0_isFirstIssue 522 s0_out.hasROBEntry := s0_has_rob_entry 523 s0_out.isPrefetch := s0_prf 524 s0_out.isHWPrefetch := s0_hw_prf 525 s0_out.isFastReplay := s0_fast_rep 526 s0_out.isLoadReplay := s0_ld_rep 527 s0_out.isFastPath := s0_l2l_fwd 528 s0_out.mshrid := s0_mshrid 529 s0_out.isvec := s0_isvec 530 s0_out.isLastElem := s0_isLastElem 531 s0_out.vecActive := s0_vecActive 532 // s0_out.sflowPtr := s0_flowPtr 533 s0_out.uop.exceptionVec(loadAddrMisaligned) := !s0_addr_aligned && s0_ld_flow 534 s0_out.uop.exceptionVec(storeAddrMisaligned) := !s0_addr_aligned && !s0_ld_flow 535 s0_out.forward_tlDchannel := s0_super_ld_rep_select 536 when(io.tlb.req.valid && s0_isFirstIssue) { 537 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 538 }.otherwise{ 539 s0_out.uop.debugInfo.tlbFirstReqTime := s0_uop.debugInfo.tlbFirstReqTime 540 } 541 s0_out.schedIndex := s0_sched_idx 542 543 // load fast replay 544 io.ldu_io.fast_rep_in.ready := (s0_can_go && io.ldu_io.dcache.req.ready && s0_ld_fast_rep_ready) 545 546 // load flow source ready 547 // cache missed load has highest priority 548 // always accept cache missed load flow from load replay queue 549 io.ldu_io.replay.ready := (s0_can_go && io.ldu_io.dcache.req.ready && (s0_ld_rep_ready && !s0_rep_stall || s0_super_ld_rep_select)) 550 551 // accept load flow from rs when: 552 // 1) there is no lsq-replayed load 553 // 2) there is no fast replayed load 554 // 3) there is no high confidence prefetch request 555 io.lsin.ready := (s0_can_go && 556 Mux(FuType.isLoad(io.lsin.bits.uop.fuType), io.ldu_io.dcache.req.ready, 557 (if (StorePrefetchL1Enabled) io.stu_io.dcache.req.ready else true.B)) && s0_int_iss_ready) 558 io.vec_stu_io.in.ready := s0_can_go && io.ldu_io.dcache.req.ready && s0_vec_iss_ready 559 560 561 // for hw prefetch load flow feedback, to be added later 562 // io.prefetch_in.ready := s0_hw_prf_select 563 564 // dcache replacement extra info 565 // TODO: should prefetch load update replacement? 566 io.ldu_io.dcache.replacementUpdated := Mux(s0_ld_rep_select || s0_super_ld_rep_select, io.ldu_io.replay.bits.replacementUpdated, false.B) 567 568 io.stu_io.prefetch_req.ready := s1_ready && io.stu_io.dcache.req.ready && !io.lsin.valid 569 570 // load debug 571 XSDebug(io.ldu_io.dcache.req.fire && s0_ld_flow, 572 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 573 ) 574 XSDebug(s0_valid && s0_ld_flow, 575 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, lqIdx ${Hexadecimal(s0_out.uop.lqIdx.asUInt)}, " + 576 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 577 578 // store debug 579 XSDebug(io.stu_io.dcache.req.fire && !s0_ld_flow, 580 p"[DCACHE STORE REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 581 ) 582 XSDebug(s0_valid && !s0_ld_flow, 583 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, sqIdx ${Hexadecimal(s0_out.uop.sqIdx.asUInt)}, " + 584 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 585 586 587 // Pipeline 588 // -------------------------------------------------------------------------------- 589 // stage 1 590 // -------------------------------------------------------------------------------- 591 // TLB resp (send paddr to dcache) 592 val s1_valid = RegInit(false.B) 593 val s1_in = Wire(new LqWriteBundle) 594 val s1_out = Wire(new LqWriteBundle) 595 val s1_kill = Wire(Bool()) 596 val s1_can_go = s2_ready 597 val s1_fire = s1_valid && !s1_kill && s1_can_go 598 val s1_ld_flow = RegNext(s0_ld_flow) 599 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 600 val s1_isLastElem = RegEnable(s0_out.isLastElem, false.B, s0_fire) 601 602 s1_ready := !s1_valid || s1_kill || s2_ready 603 when (s0_fire) { s1_valid := true.B } 604 .elsewhen (s1_fire) { s1_valid := false.B } 605 .elsewhen (s1_kill) { s1_valid := false.B } 606 s1_in := RegEnable(s0_out, s0_fire) 607 608 val s1_fast_rep_dly_err = RegNext(io.ldu_io.fast_rep_in.bits.delayedLoadError) 609 val s1_fast_rep_kill = s1_fast_rep_dly_err && s1_in.isFastReplay 610 val s1_l2l_fwd_dly_err = RegNext(io.ldu_io.l2l_fwd_in.dly_ld_err) 611 val s1_l2l_fwd_kill = s1_l2l_fwd_dly_err && s1_in.isFastPath 612 val s1_late_kill = s1_fast_rep_kill || s1_l2l_fwd_kill 613 val s1_vaddr_hi = Wire(UInt()) 614 val s1_vaddr_lo = Wire(UInt()) 615 val s1_vaddr = Wire(UInt()) 616 val s1_paddr_dup_lsu = Wire(UInt()) 617 val s1_paddr_dup_dcache = Wire(UInt()) 618 val s1_ld_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, LduCfg).asUInt.orR // af & pf exception were modified below. 619 val s1_st_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR // af & pf exception were modified below. 620 val s1_exception = (s1_ld_flow && s1_ld_exception) || (!s1_ld_flow && s1_st_exception) 621 val s1_tlb_miss = io.tlb.resp.bits.miss 622 val s1_prf = s1_in.isPrefetch 623 val s1_hw_prf = s1_in.isHWPrefetch 624 val s1_sw_prf = s1_prf && !s1_hw_prf 625 val s1_tlb_memidx = io.tlb.resp.bits.memidx 626 627 // mmio cbo decoder 628 val s1_mmio_cbo = (s1_in.uop.fuOpType === LSUOpType.cbo_clean || 629 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 630 s1_in.uop.fuOpType === LSUOpType.cbo_inval) && !s1_ld_flow && !s1_prf 631 val s1_mmio = s1_mmio_cbo 632 633 s1_vaddr_hi := s1_in.vaddr(VAddrBits - 1, 6) 634 s1_vaddr_lo := s1_in.vaddr(5, 0) 635 s1_vaddr := Cat(s1_vaddr_hi, s1_vaddr_lo) 636 s1_paddr_dup_lsu := io.tlb.resp.bits.paddr(0) 637 s1_paddr_dup_dcache := io.tlb.resp.bits.paddr(1) 638 639 when (s1_tlb_memidx.is_ld && io.tlb.resp.valid && !s1_tlb_miss && 640 s1_tlb_memidx.idx === s1_in.uop.lqIdx.value && s1_ld_flow) { 641 // printf("Load idx = %d\n", s1_tlb_memidx.idx) 642 s1_out.uop.debugInfo.tlbRespTime := GTimer() 643 } .elsewhen(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && 644 s1_tlb_memidx.idx === s1_out.uop.sqIdx.value && !s1_ld_flow) { 645 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 646 s1_out.uop.debugInfo.tlbRespTime := GTimer() 647 } 648 649 io.tlb.req_kill := s1_kill 650 io.tlb.resp.ready := true.B 651 652 io.ldu_io.dcache.s1_paddr_dup_lsu <> s1_paddr_dup_lsu 653 io.ldu_io.dcache.s1_paddr_dup_dcache <> s1_paddr_dup_dcache 654 io.ldu_io.dcache.s1_kill := s1_kill || s1_tlb_miss || s1_exception 655 656 // store to load forwarding 657 io.ldu_io.sbuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 658 io.ldu_io.sbuffer.vaddr := s1_vaddr 659 io.ldu_io.sbuffer.paddr := s1_paddr_dup_lsu 660 io.ldu_io.sbuffer.uop := s1_in.uop 661 io.ldu_io.sbuffer.sqIdx := s1_in.uop.sqIdx 662 io.ldu_io.sbuffer.mask := s1_in.mask 663 io.ldu_io.sbuffer.pc := s1_in.uop.pc // FIXME: remove it 664 665 io.ldu_io.vec_forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 666 io.ldu_io.vec_forward.vaddr := s1_vaddr 667 io.ldu_io.vec_forward.paddr := s1_paddr_dup_lsu 668 io.ldu_io.vec_forward.uop := s1_in.uop 669 io.ldu_io.vec_forward.sqIdx := s1_in.uop.sqIdx 670 io.ldu_io.vec_forward.mask := s1_in.mask 671 io.ldu_io.vec_forward.pc := s1_in.uop.pc // FIXME: remove it 672 673 io.ldu_io.lsq.forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 674 io.ldu_io.lsq.forward.vaddr := s1_vaddr 675 io.ldu_io.lsq.forward.paddr := s1_paddr_dup_lsu 676 io.ldu_io.lsq.forward.uop := s1_in.uop 677 io.ldu_io.lsq.forward.sqIdx := s1_in.uop.sqIdx 678 io.ldu_io.lsq.forward.sqIdxMask := 0.U 679 io.ldu_io.lsq.forward.mask := s1_in.mask 680 io.ldu_io.lsq.forward.pc := s1_in.uop.pc // FIXME: remove it 681 682 // st-ld violation query 683 val s1_nuke = VecInit((0 until StorePipelineWidth).map(w => { 684 io.ldu_io.stld_nuke_query(w).valid && // query valid 685 isAfter(s1_in.uop.robIdx, io.ldu_io.stld_nuke_query(w).bits.robIdx) && // older store 686 // TODO: Fix me when vector instruction 687 (s1_paddr_dup_lsu(PAddrBits-1, 3) === io.ldu_io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 688 (s1_in.mask & io.ldu_io.stld_nuke_query(w).bits.mask).orR // data mask contain 689 })).asUInt.orR && !s1_tlb_miss && s1_ld_flow 690 691 s1_out := s1_in 692 s1_out.vaddr := s1_vaddr 693 s1_out.paddr := s1_paddr_dup_lsu 694 s1_out.tlbMiss := s1_tlb_miss 695 s1_out.ptwBack := io.tlb.resp.bits.ptwBack 696 s1_out.rsIdx := s1_in.rsIdx 697 s1_out.rep_info.debug := s1_in.uop.debugInfo 698 s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf 699 s1_out.lateKill := s1_late_kill 700 701 when (s1_ld_flow) { 702 when (!s1_late_kill) { 703 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 704 // af & pf exception were modified 705 s1_out.uop.exceptionVec(loadPageFault) := io.tlb.resp.bits.excp(0).pf.ld 706 s1_out.uop.exceptionVec(loadAccessFault) := io.tlb.resp.bits.excp(0).af.ld 707 } .otherwise { 708 s1_out.uop.exceptionVec(loadAddrMisaligned) := false.B 709 s1_out.uop.exceptionVec(loadAccessFault) := s1_late_kill 710 } 711 } .otherwise { 712 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st 713 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st 714 } 715 716 // pointer chasing 717 val s1_try_ptr_chasing = RegNext(s0_do_try_ptr_chasing, false.B) 718 val s1_ptr_chasing_vaddr = RegEnable(s0_ptr_chasing_vaddr, s0_do_try_ptr_chasing) 719 val s1_fu_op_type_not_ld = WireInit(false.B) 720 val s1_not_fast_match = WireInit(false.B) 721 val s1_addr_mismatch = WireInit(false.B) 722 val s1_addr_misaligned = WireInit(false.B) 723 val s1_ptr_chasing_canceled = WireInit(false.B) 724 val s1_cancel_ptr_chasing = WireInit(false.B) 725 726 s1_kill := s1_late_kill || 727 s1_cancel_ptr_chasing || 728 s1_in.uop.robIdx.needFlush(io.redirect) || 729 RegEnable(s0_kill, false.B, io.lsin.valid || io.ldu_io.replay.valid || io.ldu_io.l2l_fwd_in.valid || io.ldu_io.fast_rep_in.valid || io.vec_stu_io.in.valid) 730 731 if (EnableLoadToLoadForward) { 732 // Sometimes, we need to cancel the load-load forwarding. 733 // These can be put at S0 if timing is bad at S1. 734 // Case 0: CACHE_SET(base + offset) != CACHE_SET(base) (lowest 6-bit addition has an overflow) 735 s1_addr_mismatch := s1_ptr_chasing_vaddr(6) || RegEnable(io.ldu_io.ld_fast_imm(11, 6).orR, s0_do_try_ptr_chasing) 736 // Case 1: the address is misaligned, kill s1 737 s1_addr_misaligned := LookupTree(s1_in.uop.fuOpType(1, 0), List( 738 "b00".U -> false.B, //b 739 "b01".U -> (s1_vaddr(0) =/= 0.U), //h 740 "b10".U -> (s1_vaddr(1, 0) =/= 0.U), //w 741 "b11".U -> (s1_vaddr(2, 0) =/= 0.U) //d 742 )) 743 // Case 2: this load-load uop is cancelled 744 s1_ptr_chasing_canceled := !io.lsin.valid || FuType.isStore(io.lsin.bits.uop.fuType) 745 746 when (s1_try_ptr_chasing) { 747 s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_ptr_chasing_canceled 748 749 s1_in.uop := io.lsin.bits.uop 750 s1_in.rsIdx := io.lsin.bits.iqIdx 751 s1_in.isFirstIssue := io.lsin.bits.isFirstIssue 752 s1_vaddr_lo := s1_ptr_chasing_vaddr(5, 0) 753 s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 754 s1_paddr_dup_dcache := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 755 756 // recored tlb time when get the data to ensure the correctness of the latency calculation (although it should not record in here, because it does not use tlb) 757 s1_in.uop.debugInfo.tlbFirstReqTime := GTimer() 758 s1_in.uop.debugInfo.tlbRespTime := GTimer() 759 } 760 when (!s1_cancel_ptr_chasing) { 761 s0_ptr_chasing_canceled := s1_try_ptr_chasing && !io.ldu_io.replay.fire && !io.ldu_io.fast_rep_in.fire 762 when (s1_try_ptr_chasing) { 763 io.lsin.ready := true.B 764 } 765 } 766 } 767 768 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 769 val s1_sqIdx_mask = RegNext(UIntToMask(s0_out.uop.sqIdx.value, StoreQueueSize)) 770 // to enable load-load, sqIdxMask must be calculated based on lsin.uop 771 // If the timing here is not OK, load-load forwarding has to be disabled. 772 // Or we calculate sqIdxMask at RS?? 773 io.ldu_io.lsq.forward.sqIdxMask := s1_sqIdx_mask 774 if (EnableLoadToLoadForward) { 775 when (s1_try_ptr_chasing) { 776 io.ldu_io.lsq.forward.sqIdxMask := UIntToMask(io.lsin.bits.uop.sqIdx.value, StoreQueueSize) 777 } 778 } 779 780 io.ldu_io.forward_mshr.valid := s1_valid && s1_out.forward_tlDchannel && s1_ld_flow 781 io.ldu_io.forward_mshr.mshrid := s1_out.mshrid 782 io.ldu_io.forward_mshr.paddr := s1_out.paddr 783 784 io.ldu_io.wakeup.valid := s0_fire && s0_ld_flow && (s0_super_ld_rep_select || s0_ld_fast_rep_select || s0_ld_rep_select || s0_int_iss_select) 785 io.ldu_io.wakeup.bits := s0_uop 786 787 io.stu_io.dcache.s1_kill := s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect) 788 io.stu_io.dcache.s1_paddr := s1_paddr_dup_dcache 789 790 791 // load debug 792 XSDebug(s1_valid && s1_ld_flow, 793 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 794 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 795 796 // store debug 797 XSDebug(s1_valid && !s1_ld_flow, 798 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.sqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 799 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 800 801 // store out 802 io.stu_io.lsq.valid := s1_valid && !s1_ld_flow && !s1_prf && !s1_isvec 803 io.stu_io.lsq.bits := s1_out 804 io.stu_io.lsq.bits.miss := s1_tlb_miss 805 806 io.vec_stu_io.lsq.valid := s1_valid && !s1_ld_flow && !s1_prf && s1_isvec 807 io.vec_stu_io.lsq.bits := s1_out 808 io.vec_stu_io.lsq.bits.miss := s1_tlb_miss 809 io.vec_stu_io.lsq.bits.isLastElem := s1_isLastElem 810 811 io.stu_io.st_mask_out.valid := s1_valid && !s1_ld_flow && !s1_prf 812 io.stu_io.st_mask_out.bits.mask := s1_out.mask 813 io.stu_io.st_mask_out.bits.sqIdx := s1_out.uop.sqIdx 814 815 io.stu_io.issue.valid := s1_valid && !s1_tlb_miss && !s1_ld_flow && !s1_prf && !s1_isvec 816 io.stu_io.issue.bits := RegEnable(io.lsin.bits, io.lsin.fire) 817 818 // st-ld violation dectect request 819 io.stu_io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_ld_flow && !s1_prf 820 io.stu_io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 821 io.stu_io.stld_nuke_query.bits.paddr := s1_paddr_dup_lsu 822 io.stu_io.stld_nuke_query.bits.mask := s1_in.mask 823 824 // Pipeline 825 // -------------------------------------------------------------------------------- 826 // stage 2 827 // -------------------------------------------------------------------------------- 828 // s2: DCache resp 829 val s2_valid = RegInit(false.B) 830 val s2_in = Wire(new LqWriteBundle) 831 val s2_out = Wire(new LqWriteBundle) 832 val s2_kill = Wire(Bool()) 833 val s2_can_go = s3_ready 834 val s2_fire = s2_valid && !s2_kill && s2_can_go 835 val s2_isvec = RegEnable(s1_isvec, false.B, s1_fire) 836 val s2_vecActive = RegEnable(s1_out.vecActive, true.B, s1_fire) 837 val s2_paddr = RegEnable(s1_paddr_dup_lsu, s1_fire) 838 839 s2_kill := s2_in.uop.robIdx.needFlush(io.redirect) 840 s2_ready := !s2_valid || s2_kill || s3_ready 841 when (s1_fire) { s2_valid := true.B } 842 .elsewhen (s2_fire) { s2_valid := false.B } 843 .elsewhen (s2_kill) { s2_valid := false.B } 844 s2_in := RegEnable(s1_out, s1_fire) 845 846 val s2_pmp = WireInit(io.pmp) 847 848 val s2_prf = s2_in.isPrefetch 849 val s2_hw_prf = s2_in.isHWPrefetch 850 val s2_ld_flow = RegEnable(s1_ld_flow, s1_fire) 851 852 // exception that may cause load addr to be invalid / illegal 853 // if such exception happen, that inst and its exception info 854 // will be force writebacked to rob 855 val s2_exception_vec = WireInit(s2_in.uop.exceptionVec) 856 when (s2_ld_flow) { 857 when (!s2_in.lateKill) { 858 s2_exception_vec(loadAccessFault) := (s2_in.uop.exceptionVec(loadAccessFault) || s2_pmp.ld) && s2_vecActive 859 // soft prefetch will not trigger any exception (but ecc error interrupt may be triggered) 860 when (s2_prf || s2_in.tlbMiss) { 861 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 862 } 863 } 864 } .otherwise { 865 s2_exception_vec(storeAccessFault) := s2_in.uop.exceptionVec(storeAccessFault) || s2_pmp.st 866 when (s2_prf || s2_in.tlbMiss) { 867 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 868 } 869 } 870 val s2_ld_exception = ExceptionNO.selectByFu(s2_exception_vec, LduCfg).asUInt.orR && s2_ld_flow 871 val s2_st_exception = ExceptionNO.selectByFu(s2_exception_vec, StaCfg).asUInt.orR && !s2_ld_flow 872 val s2_exception = s2_ld_exception || s2_st_exception 873 874 val (s2_fwd_frm_d_chan, s2_fwd_data_frm_d_chan) = io.ldu_io.tl_d_channel.forward(s1_valid && s1_out.forward_tlDchannel, s1_out.mshrid, s1_out.paddr) 875 val (s2_fwd_data_valid, s2_fwd_frm_mshr, s2_fwd_data_frm_mshr) = io.ldu_io.forward_mshr.forward() 876 val s2_fwd_frm_d_chan_or_mshr = s2_fwd_data_valid && (s2_fwd_frm_d_chan || s2_fwd_frm_mshr) 877 878 // writeback access fault caused by ecc error / bus error 879 // * ecc data error is slow to generate, so we will not use it until load stage 3 880 // * in load stage 3, an extra signal io.load_error will be used to 881 val s2_actually_mmio = s2_pmp.mmio 882 val s2_ld_mmio = !s2_prf && 883 s2_actually_mmio && 884 !s2_exception && 885 !s2_in.tlbMiss && 886 s2_ld_flow 887 val s2_st_mmio = !s2_prf && 888 (RegNext(s1_mmio) || s2_pmp.mmio) && 889 !s2_exception && 890 !s2_in.tlbMiss && 891 !s2_ld_flow 892 val s2_st_atomic = !s2_prf && 893 (RegNext(s1_mmio) || s2_pmp.atomic) && 894 !s2_exception && 895 !s2_in.tlbMiss && 896 !s2_ld_flow 897 val s2_full_fwd = Wire(Bool()) 898 val s2_mem_amb = s2_in.uop.storeSetHit && 899 io.ldu_io.lsq.forward.addrInvalid 900 901 val s2_tlb_miss = s2_in.tlbMiss 902 val s2_fwd_fail = io.ldu_io.lsq.forward.dataInvalid || io.ldu_io.vec_forward.dataInvalid 903 val s2_dcache_miss = io.ldu_io.dcache.resp.bits.miss && 904 !s2_fwd_frm_d_chan_or_mshr && 905 !s2_full_fwd 906 907 val s2_mq_nack = io.ldu_io.dcache.s2_mq_nack && 908 !s2_fwd_frm_d_chan_or_mshr && 909 !s2_full_fwd 910 911 val s2_bank_conflict = io.ldu_io.dcache.s2_bank_conflict && 912 !s2_fwd_frm_d_chan_or_mshr && 913 !s2_full_fwd 914 915 val s2_wpu_pred_fail = io.ldu_io.dcache.s2_wpu_pred_fail && 916 !s2_fwd_frm_d_chan_or_mshr && 917 !s2_full_fwd 918 919 val s2_rar_nack = io.ldu_io.lsq.ldld_nuke_query.req.valid && 920 !io.ldu_io.lsq.ldld_nuke_query.req.ready 921 922 val s2_raw_nack = io.ldu_io.lsq.stld_nuke_query.req.valid && 923 !io.ldu_io.lsq.stld_nuke_query.req.ready 924 925 // st-ld violation query 926 // NeedFastRecovery Valid when 927 // 1. Fast recovery query request Valid. 928 // 2. Load instruction is younger than requestors(store instructions). 929 // 3. Physical address match. 930 // 4. Data contains. 931 val s2_nuke = VecInit((0 until StorePipelineWidth).map(w => { 932 io.ldu_io.stld_nuke_query(w).valid && // query valid 933 isAfter(s2_in.uop.robIdx, io.ldu_io.stld_nuke_query(w).bits.robIdx) && // older store 934 // TODO: Fix me when vector instruction 935 (s2_in.paddr(PAddrBits-1, 3) === io.ldu_io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 936 (s2_in.mask & io.ldu_io.stld_nuke_query(w).bits.mask).orR // data mask contain 937 })).asUInt.orR && s2_ld_flow || s2_in.rep_info.nuke 938 939 val s2_cache_handled = io.ldu_io.dcache.resp.bits.handled 940 val s2_cache_tag_error = RegNext(io.csrCtrl.cache_error_enable) && 941 io.ldu_io.dcache.resp.bits.tag_error 942 943 val s2_troublem = !s2_exception && 944 !s2_ld_mmio && 945 !s2_prf && 946 !s2_in.lateKill && 947 s2_ld_flow 948 949 io.ldu_io.dcache.resp.ready := true.B 950 io.stu_io.dcache.resp.ready := true.B 951 val s2_dcache_should_resp = !(s2_in.tlbMiss || s2_exception || s2_ld_mmio || s2_prf || s2_in.lateKill) && s2_ld_flow 952 assert(!(s2_valid && (s2_dcache_should_resp && !io.ldu_io.dcache.resp.valid)), "DCache response got lost") 953 954 // fast replay require 955 val s2_dcache_fast_rep = (s2_mq_nack || !s2_dcache_miss && (s2_bank_conflict || s2_wpu_pred_fail)) 956 val s2_nuke_fast_rep = !s2_mq_nack && 957 !s2_dcache_miss && 958 !s2_bank_conflict && 959 !s2_wpu_pred_fail && 960 !s2_rar_nack && 961 !s2_raw_nack && 962 s2_nuke 963 964 val s2_fast_rep = !s2_mem_amb && 965 !s2_tlb_miss && 966 !s2_fwd_fail && 967 (s2_dcache_fast_rep || s2_nuke_fast_rep) && 968 s2_troublem 969 970 // need allocate new entry 971 val s2_can_query = !s2_mem_amb && 972 !s2_tlb_miss && 973 !s2_fwd_fail && 974 !s2_dcache_fast_rep && 975 s2_troublem 976 977 val s2_data_fwded = s2_dcache_miss && (s2_full_fwd || s2_cache_tag_error) 978 979 // ld-ld violation require 980 io.ldu_io.lsq.ldld_nuke_query.req.valid := s2_valid && s2_can_query 981 io.ldu_io.lsq.ldld_nuke_query.req.bits.uop := s2_in.uop 982 io.ldu_io.lsq.ldld_nuke_query.req.bits.mask := s2_in.mask 983 io.ldu_io.lsq.ldld_nuke_query.req.bits.paddr := s2_in.paddr 984 io.ldu_io.lsq.ldld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 985 986 // st-ld violation require 987 io.ldu_io.lsq.stld_nuke_query.req.valid := s2_valid && s2_can_query 988 io.ldu_io.lsq.stld_nuke_query.req.bits.uop := s2_in.uop 989 io.ldu_io.lsq.stld_nuke_query.req.bits.mask := s2_in.mask 990 io.ldu_io.lsq.stld_nuke_query.req.bits.paddr := s2_in.paddr 991 io.ldu_io.lsq.stld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 992 993 // merge forward result 994 // lsq has higher priority than sbuffer 995 val s2_fwd_mask = Wire(Vec((VLEN/8), Bool())) 996 val s2_fwd_data = Wire(Vec((VLEN/8), UInt(8.W))) 997 s2_full_fwd := ((~s2_fwd_mask.asUInt).asUInt & s2_in.mask) === 0.U && !io.ldu_io.lsq.forward.dataInvalid && !io.ldu_io.vec_forward.dataInvalid 998 // generate XLEN/8 Muxs 999 for (i <- 0 until VLEN / 8) { 1000 s2_fwd_mask(i) := io.ldu_io.lsq.forward.forwardMask(i) || io.ldu_io.sbuffer.forwardMask(i) || io.ldu_io.vec_forward.forwardMask(i) 1001 s2_fwd_data(i) := Mux( 1002 io.ldu_io.lsq.forward.forwardMask(i), 1003 io.ldu_io.lsq.forward.forwardData(i), 1004 Mux( 1005 io.ldu_io.vec_forward.forwardMask(i), 1006 io.ldu_io.vec_forward.forwardData(i), 1007 io.ldu_io.sbuffer.forwardData(i) 1008 ) 1009 ) 1010 } 1011 1012 XSDebug(s2_fire && s2_ld_flow, "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 1013 s2_in.uop.pc, 1014 io.ldu_io.lsq.forward.forwardData.asUInt, io.ldu_io.lsq.forward.forwardMask.asUInt, 1015 s2_in.forwardData.asUInt, s2_in.forwardMask.asUInt 1016 ) 1017 1018 // 1019 s2_out := s2_in 1020 s2_out.data := 0.U // data will be generated in load s3 1021 s2_out.uop.fpWen := s2_in.uop.fpWen && !s2_exception && s2_ld_flow 1022 s2_out.mmio := s2_ld_mmio || s2_st_mmio 1023 s2_out.atomic := s2_st_atomic 1024 s2_out.uop.flushPipe := false.B 1025 s2_out.uop.exceptionVec := s2_exception_vec 1026 s2_out.forwardMask := s2_fwd_mask 1027 s2_out.forwardData := s2_fwd_data 1028 s2_out.handledByMSHR := s2_cache_handled 1029 s2_out.miss := s2_dcache_miss && s2_troublem 1030 s2_out.feedbacked := io.feedback_fast.valid && !io.feedback_fast.bits.hit 1031 1032 // Generate replay signal caused by: 1033 // * st-ld violation check 1034 // * tlb miss 1035 // * dcache replay 1036 // * forward data invalid 1037 // * dcache miss 1038 s2_out.rep_info.mem_amb := s2_mem_amb && s2_troublem 1039 s2_out.rep_info.tlb_miss := s2_tlb_miss && s2_troublem 1040 s2_out.rep_info.fwd_fail := s2_fwd_fail && s2_troublem 1041 s2_out.rep_info.dcache_rep := s2_mq_nack && s2_troublem 1042 s2_out.rep_info.dcache_miss := s2_dcache_miss && s2_troublem 1043 s2_out.rep_info.bank_conflict := s2_bank_conflict && s2_troublem 1044 s2_out.rep_info.wpu_fail := s2_wpu_pred_fail && s2_troublem 1045 s2_out.rep_info.rar_nack := s2_rar_nack && s2_troublem 1046 s2_out.rep_info.raw_nack := s2_raw_nack && s2_troublem 1047 s2_out.rep_info.nuke := s2_nuke && s2_troublem 1048 s2_out.rep_info.full_fwd := s2_data_fwded 1049 s2_out.rep_info.data_inv_sq_idx := Mux(io.ldu_io.vec_forward.dataInvalid, s2_out.uop.sqIdx, io.ldu_io.lsq.forward.dataInvalidSqIdx) 1050 s2_out.rep_info.addr_inv_sq_idx := Mux(io.ldu_io.vec_forward.addrInvalid, s2_out.uop.sqIdx, io.ldu_io.lsq.forward.addrInvalidSqIdx) 1051 s2_out.rep_info.rep_carry := io.ldu_io.dcache.resp.bits.replayCarry 1052 s2_out.rep_info.mshr_id := io.ldu_io.dcache.resp.bits.mshr_id 1053 s2_out.rep_info.last_beat := s2_in.paddr(log2Up(refillBytes)) 1054 s2_out.rep_info.debug := s2_in.uop.debugInfo 1055 s2_out.rep_info.tlb_id := io.ldu_io.tlb_hint.id 1056 s2_out.rep_info.tlb_full := io.ldu_io.tlb_hint.full 1057 1058 // if forward fail, replay this inst from fetch 1059 val debug_fwd_fail_rep = s2_fwd_fail && !s2_troublem && !s2_in.tlbMiss 1060 // if ld-ld violation is detected, replay from this inst from fetch 1061 val debug_ldld_nuke_rep = false.B // s2_ldld_violation && !s2_ld_mmio && !s2_is_prefetch && !s2_in.tlbMiss 1062 // io.out.bits.uop.replayInst := false.B 1063 1064 // to be removed 1065 val s2_ld_need_fb = !s2_in.isLoadReplay && // already feedbacked 1066 io.ldu_io.lq_rep_full && // LoadQueueReplay is full 1067 s2_out.rep_info.need_rep && // need replay 1068 !s2_exception && // no exception is triggered 1069 !s2_hw_prf && // not hardware prefetch 1070 !s2_isvec 1071 val s2_st_need_fb = !s2_ld_flow && !s2_hw_prf && !s2_isvec 1072 io.feedback_fast.valid := s2_valid && (s2_ld_need_fb || s2_st_need_fb) 1073 io.feedback_fast.bits.hit := Mux(s2_ld_flow, false.B, !s2_tlb_miss) 1074 io.feedback_fast.bits.flushState := s2_in.ptwBack 1075 io.feedback_fast.bits.robIdx := s2_in.uop.robIdx 1076 io.feedback_fast.bits.sourceType := Mux(s2_ld_flow, RSFeedbackType.lrqFull, RSFeedbackType.tlbMiss) 1077 io.feedback_fast.bits.dataInvalidSqIdx := DontCare 1078 1079 val s2_vec_feedback = Wire(Valid(new VSFQFeedback)) 1080 s2_vec_feedback.valid := s2_valid && !s2_ld_flow && !s2_hw_prf && s2_isvec 1081 // s2_vec_feedback.bits.flowPtr := s2_out.sflowPtr 1082 s2_vec_feedback.bits.hit := !s2_tlb_miss 1083 s2_vec_feedback.bits.sourceType := RSFeedbackType.tlbMiss 1084 s2_vec_feedback.bits.paddr := s2_paddr 1085 s2_vec_feedback.bits.mmio := s2_st_mmio 1086 s2_vec_feedback.bits.atomic := s2_st_mmio 1087 s2_vec_feedback.bits.exceptionVec := s2_exception_vec 1088 1089 io.stu_io.lsq_replenish := s2_out 1090 io.stu_io.lsq_replenish.miss := io.ldu_io.dcache.resp.fire && io.ldu_io.dcache.resp.bits.miss 1091 1092 io.ldu_io.ldCancel.ld1Cancel := false.B 1093 1094 // fast wakeup 1095 io.ldu_io.fast_uop.valid := RegNext( 1096 !io.ldu_io.dcache.s1_disable_fast_wakeup && 1097 s1_valid && 1098 !s1_kill && 1099 !io.tlb.resp.bits.miss && 1100 !io.ldu_io.lsq.forward.dataInvalidFast 1101 ) && (s2_valid && !s2_out.rep_info.need_rep && !s2_ld_mmio && s2_ld_flow) && !s2_isvec 1102 io.ldu_io.fast_uop.bits := RegNext(s1_out.uop) 1103 1104 // 1105 io.ldu_io.s2_ptr_chasing := RegEnable(s1_try_ptr_chasing && !s1_cancel_ptr_chasing, false.B, s1_fire) 1106 1107 // prefetch train 1108 io.prefetch_train.valid := s2_valid && !s2_actually_mmio && !s2_in.tlbMiss 1109 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 1110 io.prefetch_train.bits.miss := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.miss, io.stu_io.dcache.resp.bits.miss) // TODO: use trace with bank conflict? 1111 io.prefetch_train.bits.meta_prefetch := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.meta_prefetch, false.B) 1112 io.prefetch_train.bits.meta_access := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.meta_access, false.B) 1113 1114 io.prefetch_train_l1.valid := s2_valid && !s2_actually_mmio && s2_ld_flow 1115 io.prefetch_train_l1.bits.fromLsPipelineBundle(s2_in) 1116 io.prefetch_train_l1.bits.miss := io.ldu_io.dcache.resp.bits.miss 1117 io.prefetch_train_l1.bits.meta_prefetch := io.ldu_io.dcache.resp.bits.meta_prefetch 1118 io.prefetch_train_l1.bits.meta_access := io.ldu_io.dcache.resp.bits.meta_access 1119 if (env.FPGAPlatform){ 1120 io.ldu_io.dcache.s0_pc := DontCare 1121 io.ldu_io.dcache.s1_pc := DontCare 1122 io.ldu_io.dcache.s2_pc := DontCare 1123 }else{ 1124 io.ldu_io.dcache.s0_pc := s0_out.uop.pc 1125 io.ldu_io.dcache.s1_pc := s1_out.uop.pc 1126 io.ldu_io.dcache.s2_pc := s2_out.uop.pc 1127 } 1128 io.ldu_io.dcache.s2_kill := s2_pmp.ld || s2_actually_mmio || s2_kill 1129 io.stu_io.dcache.s2_kill := s2_pmp.st || s2_actually_mmio || s2_kill 1130 io.stu_io.dcache.s2_pc := s2_out.uop.pc 1131 1132 val s1_ld_left_fire = s1_valid && !s1_kill && s2_ready && s1_ld_flow 1133 val s2_ld_valid_dup = RegInit(0.U(6.W)) 1134 s2_ld_valid_dup := 0x0.U(6.W) 1135 when (s1_ld_left_fire && !s1_out.isHWPrefetch && s1_ld_flow) { s2_ld_valid_dup := 0x3f.U(6.W) } 1136 when (s1_kill || s1_out.isHWPrefetch || !s1_ld_flow) { s2_ld_valid_dup := 0x0.U(6.W) } 1137 assert(RegNext((s2_valid === s2_ld_valid_dup(0)) || RegNext(s1_out.isHWPrefetch) || RegNext(!s1_ld_flow))) 1138 1139 // Pipeline 1140 // -------------------------------------------------------------------------------- 1141 // stage 3 1142 // -------------------------------------------------------------------------------- 1143 // writeback and update load queue 1144 val s3_valid = RegNext(s2_valid && !s2_out.isHWPrefetch && !s2_out.uop.robIdx.needFlush(io.redirect)) 1145 val s3_in = RegEnable(s2_out, s2_fire) 1146 val s3_out = Wire(Valid(new MemExuOutput)) 1147 val s3_dcache_rep = RegEnable(s2_dcache_fast_rep && s2_troublem, false.B, s2_fire) 1148 val s3_ld_valid_dup = RegEnable(s2_ld_valid_dup, s2_fire) 1149 val s3_fast_rep = Wire(Bool()) 1150 val s3_ld_flow = RegNext(s2_ld_flow) 1151 val s3_troublem = RegNext(s2_troublem) 1152 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 1153 val s3_isvec = RegNext(s2_isvec) 1154 s3_ready := !s3_valid || s3_kill || sx_can_go 1155 1156 // forwrad last beat 1157 val (s3_fwd_frm_d_chan, s3_fwd_data_frm_d_chan) = io.ldu_io.tl_d_channel.forward(s2_valid && s2_out.forward_tlDchannel, s2_out.mshrid, s2_out.paddr) 1158 val s3_fwd_data_valid = RegEnable(s2_fwd_data_valid, false.B, s2_valid) 1159 val s3_fwd_frm_d_chan_valid = (s3_fwd_frm_d_chan && s3_fwd_data_valid) && s3_ld_flow 1160 1161 1162 // s3 load fast replay 1163 io.ldu_io.fast_rep_out.valid := s3_valid && 1164 s3_fast_rep && 1165 !s3_in.uop.robIdx.needFlush(io.redirect) && 1166 s3_ld_flow && 1167 !s3_isvec 1168 io.ldu_io.fast_rep_out.bits := s3_in 1169 1170 io.ldu_io.lsq.ldin.valid := s3_valid && 1171 (!s3_fast_rep || !io.ldu_io.fast_rep_out.ready) && 1172 !s3_in.feedbacked && 1173 !s3_in.lateKill && 1174 s3_ld_flow 1175 io.ldu_io.lsq.ldin.bits := s3_in 1176 io.ldu_io.lsq.ldin.bits.miss := s3_in.miss && !s3_fwd_frm_d_chan_valid 1177 1178 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1179 io.ldu_io.lsq.ldin.bits.data_wen_dup := s3_ld_valid_dup.asBools 1180 io.ldu_io.lsq.ldin.bits.replacementUpdated := io.ldu_io.dcache.resp.bits.replacementUpdated 1181 io.ldu_io.lsq.ldin.bits.missDbUpdated := RegNext(s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated) 1182 1183 val s3_dly_ld_err = 1184 if (EnableAccurateLoadError) { 1185 (s3_in.lateKill || io.ldu_io.dcache.resp.bits.error_delayed) && RegNext(io.csrCtrl.cache_error_enable) 1186 } else { 1187 WireInit(false.B) 1188 } 1189 io.ldu_io.s3_dly_ld_err := false.B // s3_dly_ld_err && s3_valid 1190 io.ldu_io.fast_rep_out.bits.delayedLoadError := s3_dly_ld_err 1191 io.ldu_io.lsq.ldin.bits.dcacheRequireReplay := s3_dcache_rep 1192 1193 val s3_vp_match_fail = RegNext(io.ldu_io.lsq.forward.matchInvalid || io.ldu_io.sbuffer.matchInvalid) && s3_troublem 1194 val s3_ldld_rep_inst = 1195 io.ldu_io.lsq.ldld_nuke_query.resp.valid && 1196 io.ldu_io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch && 1197 RegNext(io.csrCtrl.ldld_vio_check_enable) 1198 1199 val s3_rep_info = WireInit(s3_in.rep_info) 1200 s3_rep_info.dcache_miss := s3_in.rep_info.dcache_miss && !s3_fwd_frm_d_chan_valid && s3_troublem 1201 val s3_rep_frm_fetch = s3_vp_match_fail 1202 val s3_flushPipe = s3_ldld_rep_inst 1203 val s3_sel_rep_cause = PriorityEncoderOH(s3_rep_info.cause.asUInt) 1204 val s3_force_rep = s3_sel_rep_cause(LoadReplayCauses.C_TM) && 1205 !s3_in.uop.exceptionVec(loadAddrMisaligned) && 1206 s3_troublem 1207 1208 val s3_ld_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, LduCfg).asUInt.orR && s3_ld_flow 1209 val s3_st_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, StaCfg).asUInt.orR && !s3_ld_flow 1210 val s3_exception = s3_ld_exception || s3_st_exception 1211 when ((s3_ld_exception || s3_dly_ld_err || s3_rep_frm_fetch) && !s3_force_rep) { 1212 io.ldu_io.lsq.ldin.bits.rep_info.cause := 0.U.asTypeOf(s3_rep_info.cause.cloneType) 1213 } .otherwise { 1214 io.ldu_io.lsq.ldin.bits.rep_info.cause := VecInit(s3_sel_rep_cause.asBools) 1215 } 1216 1217 // Int flow, if hit, will be writebacked at s3 1218 s3_out.valid := s3_valid && 1219 (!s3_ld_flow && !s3_in.feedbacked || !io.ldu_io.lsq.ldin.bits.rep_info.need_rep) && !s3_in.mmio 1220 s3_out.bits.uop := s3_in.uop 1221 s3_out.bits.uop.exceptionVec(loadAccessFault) := (s3_dly_ld_err || s3_in.uop.exceptionVec(loadAccessFault)) && s3_ld_flow 1222 s3_out.bits.uop.replayInst := s3_rep_frm_fetch 1223 s3_out.bits.data := s3_in.data 1224 s3_out.bits.debug.isMMIO := s3_in.mmio 1225 s3_out.bits.debug.isPerfCnt := false.B 1226 s3_out.bits.debug.paddr := s3_in.paddr 1227 s3_out.bits.debug.vaddr := s3_in.vaddr 1228 1229 when (s3_force_rep) { 1230 s3_out.bits.uop.exceptionVec := 0.U.asTypeOf(s3_in.uop.exceptionVec.cloneType) 1231 } 1232 1233 io.ldu_io.rollback.valid := s3_valid && (s3_rep_frm_fetch || s3_flushPipe) && !s3_exception && s3_ld_flow 1234 io.ldu_io.rollback.bits := DontCare 1235 io.ldu_io.rollback.bits.isRVC := s3_out.bits.uop.preDecodeInfo.isRVC 1236 io.ldu_io.rollback.bits.robIdx := s3_out.bits.uop.robIdx 1237 io.ldu_io.rollback.bits.ftqIdx := s3_out.bits.uop.ftqPtr 1238 io.ldu_io.rollback.bits.ftqOffset := s3_out.bits.uop.ftqOffset 1239 io.ldu_io.rollback.bits.level := Mux(s3_rep_frm_fetch, RedirectLevel.flush, RedirectLevel.flushAfter) 1240 io.ldu_io.rollback.bits.cfiUpdate.target := s3_out.bits.uop.pc 1241 io.ldu_io.rollback.bits.debug_runahead_checkpoint_id := s3_out.bits.uop.debugInfo.runahead_checkpoint_id 1242 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1243 io.ldu_io.lsq.ldin.bits.uop := s3_out.bits.uop 1244 1245 val s3_revoke = s3_exception || io.ldu_io.lsq.ldin.bits.rep_info.need_rep 1246 io.ldu_io.lsq.ldld_nuke_query.revoke := s3_revoke 1247 io.ldu_io.lsq.stld_nuke_query.revoke := s3_revoke 1248 1249 // feedback slow 1250 s3_fast_rep := RegNext(s2_fast_rep) && 1251 !s3_in.feedbacked && 1252 !s3_in.lateKill && 1253 !s3_rep_frm_fetch && 1254 !s3_exception 1255 1256 val s3_fb_no_waiting = !s3_in.isLoadReplay && !(s3_fast_rep && io.ldu_io.fast_rep_out.ready) && !s3_in.feedbacked 1257 1258 // 1259 io.feedback_slow.valid := s3_valid && !s3_in.uop.robIdx.needFlush(io.redirect) && s3_fb_no_waiting && s3_ld_flow 1260 io.feedback_slow.bits.hit := !io.ldu_io.lsq.ldin.bits.rep_info.need_rep || io.ldu_io.lsq.ldin.ready 1261 io.feedback_slow.bits.flushState := s3_in.ptwBack 1262 io.feedback_slow.bits.robIdx := s3_in.uop.robIdx 1263 io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull 1264 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 1265 1266 io.vec_stu_io.feedbackSlow.valid := RegNext(s2_vec_feedback.valid && !s2_out.uop.robIdx.needFlush(io.redirect)) 1267 io.vec_stu_io.feedbackSlow.bits := RegNext(s2_vec_feedback.bits) 1268 1269 io.ldu_io.ldCancel.ld2Cancel := s3_valid && s3_ld_flow && ( // is load 1270 io.ldu_io.lsq.ldin.bits.rep_info.need_rep || s3_in.mmio // exe fail or is mmio 1271 ) 1272 1273 // data from dcache hit 1274 val s3_ld_raw_data_frm_cache = Wire(new LoadDataFromDcacheBundle) 1275 s3_ld_raw_data_frm_cache.respDcacheData := io.ldu_io.dcache.resp.bits.data_delayed 1276 s3_ld_raw_data_frm_cache.forwardMask := RegEnable(s2_fwd_mask, s2_valid) 1277 s3_ld_raw_data_frm_cache.forwardData := RegEnable(s2_fwd_data, s2_valid) 1278 s3_ld_raw_data_frm_cache.uop := RegEnable(s2_out.uop, s2_valid) 1279 s3_ld_raw_data_frm_cache.addrOffset := RegEnable(s2_out.paddr(3, 0), s2_valid) 1280 s3_ld_raw_data_frm_cache.forward_D := RegEnable(s2_fwd_frm_d_chan, false.B, s2_valid) || s3_fwd_frm_d_chan_valid 1281 s3_ld_raw_data_frm_cache.forwardData_D := Mux(s3_fwd_frm_d_chan_valid, s3_fwd_data_frm_d_chan, RegEnable(s2_fwd_data_frm_d_chan, s2_valid)) 1282 s3_ld_raw_data_frm_cache.forward_mshr := RegEnable(s2_fwd_frm_mshr, false.B, s2_valid) 1283 s3_ld_raw_data_frm_cache.forwardData_mshr := RegEnable(s2_fwd_data_frm_mshr, s2_valid) 1284 s3_ld_raw_data_frm_cache.forward_result_valid := RegEnable(s2_fwd_data_valid, false.B, s2_valid) 1285 1286 val s3_merged_data_frm_cache = s3_ld_raw_data_frm_cache.mergedData() 1287 val s3_picked_data_frm_cache = LookupTree(s3_ld_raw_data_frm_cache.addrOffset, List( 1288 "b0000".U -> s3_merged_data_frm_cache(63, 0), 1289 "b0001".U -> s3_merged_data_frm_cache(63, 8), 1290 "b0010".U -> s3_merged_data_frm_cache(63, 16), 1291 "b0011".U -> s3_merged_data_frm_cache(63, 24), 1292 "b0100".U -> s3_merged_data_frm_cache(63, 32), 1293 "b0101".U -> s3_merged_data_frm_cache(63, 40), 1294 "b0110".U -> s3_merged_data_frm_cache(63, 48), 1295 "b0111".U -> s3_merged_data_frm_cache(63, 56), 1296 "b1000".U -> s3_merged_data_frm_cache(127, 64), 1297 "b1001".U -> s3_merged_data_frm_cache(127, 72), 1298 "b1010".U -> s3_merged_data_frm_cache(127, 80), 1299 "b1011".U -> s3_merged_data_frm_cache(127, 88), 1300 "b1100".U -> s3_merged_data_frm_cache(127, 96), 1301 "b1101".U -> s3_merged_data_frm_cache(127, 104), 1302 "b1110".U -> s3_merged_data_frm_cache(127, 112), 1303 "b1111".U -> s3_merged_data_frm_cache(127, 120) 1304 )) 1305 val s3_ld_data_frm_cache = rdataHelper(s3_ld_raw_data_frm_cache.uop, s3_picked_data_frm_cache) 1306 1307 // FIXME: add 1 cycle delay ? 1308 io.ldout.bits := s3_out.bits 1309 io.ldout.bits.data := s3_ld_data_frm_cache 1310 io.ldout.valid := s3_out.valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) && s3_ld_flow && !s3_isvec 1311 1312 // for uncache 1313 io.ldu_io.lsq.uncache.ready := true.B 1314 1315 // fast load to load forward 1316 if (EnableLoadToLoadForward) { 1317 io.ldu_io.l2l_fwd_out.valid := s3_out.valid && !s3_in.lateKill && s3_ld_flow 1318 io.ldu_io.l2l_fwd_out.data := s3_ld_data_frm_cache 1319 io.ldu_io.l2l_fwd_out.dly_ld_err := s3_dly_ld_err // ecc delayed error 1320 } else { 1321 io.ldu_io.l2l_fwd_out.valid := false.B 1322 io.ldu_io.l2l_fwd_out.data := DontCare 1323 io.ldu_io.l2l_fwd_out.dly_ld_err := DontCare 1324 } 1325 1326 // hybrid unit writeback to rob 1327 // delay params 1328 val SelectGroupSize = RollbackGroupSize 1329 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 1330 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 1331 val TotalDelayCycles = TotalSelectCycles - 2 1332 1333 // writeback 1334 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 1335 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 1336 val sx_in = Wire(Vec(TotalDelayCycles + 1, new MemExuOutput)) 1337 1338 sx_can_go := sx_ready.head 1339 for (i <- 0 until TotalDelayCycles + 1) { 1340 if (i == 0) { 1341 sx_valid(i) := s3_valid && 1342 !s3_ld_flow && 1343 !s3_in.feedbacked && 1344 !s3_in.mmio 1345 sx_in(i) := s3_out.bits 1346 sx_ready(i) := !s3_valid(i) || sx_in(i).uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 1347 } else { 1348 val cur_kill = sx_in(i).uop.robIdx.needFlush(io.redirect) 1349 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 1350 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 1351 val prev_fire = sx_valid(i-1) && !sx_in(i-1).uop.robIdx.needFlush(io.redirect) && sx_ready(i) 1352 1353 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 1354 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 1355 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), sx_valid_can_go) 1356 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 1357 } 1358 } 1359 1360 val sx_last_valid = sx_valid.takeRight(1).head 1361 val sx_last_ready = sx_ready.takeRight(1).head 1362 val sx_last_in = sx_in.takeRight(1).head 1363 1364 sx_last_ready := !sx_last_valid || sx_last_in.uop.robIdx.needFlush(io.redirect) || io.stout.ready 1365 io.stout.valid := sx_last_valid && !sx_last_in.uop.robIdx.needFlush(io.redirect) && FuType.isStore(sx_last_in.uop.fuType) 1366 io.stout.bits := sx_last_in 1367 1368 // trigger 1369 val ld_trigger = FuType.isLoad(io.ldout.bits.uop.fuType) 1370 val last_valid_data = RegEnable(io.ldout.bits.data, io.stout.fire) 1371 val hit_ld_addr_trig_hit_vec = Wire(Vec(TriggerNum, Bool())) 1372 val lq_ld_addr_trig_hit_vec = RegNext(io.ldu_io.lsq.trigger.lqLoadAddrTriggerHitVec) 1373 (0 until TriggerNum).map{i => { 1374 val tdata2 = RegNext(RegNext(io.ldu_io.trigger(i).tdata2)) 1375 val matchType = RegNext(RegNext(io.ldu_io.trigger(i).matchType)) 1376 val tEnable = RegNext(RegNext(io.ldu_io.trigger(i).tEnable)) 1377 1378 hit_ld_addr_trig_hit_vec(i) := TriggerCmp(RegNext(s3_in.vaddr), tdata2, matchType, tEnable) 1379 io.ldu_io.trigger(i).addrHit := Mux(io.ldout.valid && ld_trigger, hit_ld_addr_trig_hit_vec(i), lq_ld_addr_trig_hit_vec(i)) 1380 }} 1381 io.ldu_io.lsq.trigger.hitLoadAddrTriggerHitVec := hit_ld_addr_trig_hit_vec 1382 1383 // FIXME: please move this part to LoadQueueReplay 1384 io.ldu_io.debug_ls := DontCare 1385 io.stu_io.debug_ls := DontCare 1386 io.stu_io.debug_ls.s1.isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch && !s1_ld_flow 1387 io.stu_io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 1388 1389 // Topdown 1390 io.ldu_io.lsTopdownInfo.s1.robIdx := s1_in.uop.robIdx.value 1391 io.ldu_io.lsTopdownInfo.s1.vaddr_valid := s1_valid && s1_in.hasROBEntry 1392 io.ldu_io.lsTopdownInfo.s1.vaddr_bits := s1_vaddr 1393 io.ldu_io.lsTopdownInfo.s2.robIdx := s2_in.uop.robIdx.value 1394 io.ldu_io.lsTopdownInfo.s2.paddr_valid := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss 1395 io.ldu_io.lsTopdownInfo.s2.paddr_bits := s2_in.paddr 1396 io.ldu_io.lsTopdownInfo.s2.first_real_miss := io.ldu_io.dcache.resp.bits.real_miss 1397 io.ldu_io.lsTopdownInfo.s2.cache_miss_en := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated 1398 1399 // perf cnt 1400 XSPerfAccumulate("s0_in_valid", io.lsin.valid) 1401 XSPerfAccumulate("s0_in_block", io.lsin.valid && !io.lsin.fire) 1402 XSPerfAccumulate("s0_in_fire_first_issue", s0_valid && s0_isFirstIssue) 1403 XSPerfAccumulate("s0_lsq_fire_first_issue", io.ldu_io.replay.fire) 1404 XSPerfAccumulate("s0_ldu_fire_first_issue", io.lsin.fire && s0_isFirstIssue) 1405 XSPerfAccumulate("s0_fast_replay_issue", io.ldu_io.fast_rep_in.fire) 1406 XSPerfAccumulate("s0_stall_out", s0_valid && !s0_can_go) 1407 XSPerfAccumulate("s0_stall_ld_dcache", s0_valid && !io.ldu_io.dcache.req.ready) 1408 XSPerfAccumulate("s0_stall_st_dcache", s0_valid && !io.stu_io.dcache.req.ready) 1409 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.lsin.bits.src(0)(VAddrBits-1, 12)) 1410 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.lsin.bits.src(0)(VAddrBits-1, 12)) 1411 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.lsin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1412 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.lsin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1413 XSPerfAccumulate("s0_forward_tl_d_channel", s0_out.forward_tlDchannel) 1414 XSPerfAccumulate("s0_hardware_prefetch_fire", s0_fire && s0_hw_prf_select) 1415 XSPerfAccumulate("s0_software_prefetch_fire", s0_fire && s0_prf && s0_int_iss_select) 1416 XSPerfAccumulate("s0_hardware_prefetch_blocked", io.ldu_io.prefetch_req.valid && !s0_hw_prf_select) 1417 XSPerfAccumulate("s0_hardware_prefetch_total", io.ldu_io.prefetch_req.valid) 1418 1419 XSPerfAccumulate("s1_in_valid", s1_valid) 1420 XSPerfAccumulate("s1_in_fire", s1_fire) 1421 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 1422 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 1423 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 1424 XSPerfAccumulate("s1_stall_out", s1_valid && !s1_can_go) 1425 XSPerfAccumulate("s1_late_kill", s1_valid && s1_fast_rep_kill) 1426 1427 XSPerfAccumulate("s2_in_valid", s2_valid) 1428 XSPerfAccumulate("s2_in_fire", s2_fire) 1429 XSPerfAccumulate("s2_in_fire_first_issue", s2_fire && s2_in.isFirstIssue) 1430 XSPerfAccumulate("s2_dcache_miss", s2_fire && io.ldu_io.dcache.resp.bits.miss) 1431 XSPerfAccumulate("s2_dcache_miss_first_issue", s2_fire && io.ldu_io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1432 XSPerfAccumulate("s2_dcache_real_miss_first_issue", s2_fire && io.ldu_io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1433 XSPerfAccumulate("s2_full_forward", s2_fire && s2_full_fwd) 1434 XSPerfAccumulate("s2_dcache_miss_full_forward", s2_fire && s2_dcache_miss) 1435 XSPerfAccumulate("s2_fwd_frm_d_can", s2_valid && s2_fwd_frm_d_chan) 1436 XSPerfAccumulate("s2_fwd_frm_d_chan_or_mshr", s2_valid && s2_fwd_frm_d_chan_or_mshr) 1437 XSPerfAccumulate("s2_stall_out", s2_fire && !s2_can_go) 1438 XSPerfAccumulate("s2_prefetch", s2_fire && s2_prf) 1439 XSPerfAccumulate("s2_prefetch_ignored", s2_fire && s2_prf && s2_mq_nack) // ignore prefetch for mshr full / miss req port conflict 1440 XSPerfAccumulate("s2_prefetch_miss", s2_fire && s2_prf && io.ldu_io.dcache.resp.bits.miss) // prefetch req miss in l1 1441 XSPerfAccumulate("s2_prefetch_hit", s2_fire && s2_prf && !io.ldu_io.dcache.resp.bits.miss) // prefetch req hit in l1 1442 XSPerfAccumulate("s2_prefetch_accept", s2_fire && s2_prf && io.ldu_io.dcache.resp.bits.miss && !s2_mq_nack) // prefetch a missed line in l1, and l1 accepted it 1443 XSPerfAccumulate("s2_forward_req", s2_fire && s2_in.forward_tlDchannel) 1444 XSPerfAccumulate("s2_successfully_forward_channel_D", s2_fire && s2_fwd_frm_d_chan && s2_fwd_data_valid) 1445 XSPerfAccumulate("s2_successfully_forward_mshr", s2_fire && s2_fwd_frm_mshr && s2_fwd_data_valid) 1446 1447 XSPerfAccumulate("s3_fwd_frm_d_chan", s3_valid && s3_fwd_frm_d_chan_valid) 1448 1449 XSPerfAccumulate("load_to_load_forward", s1_try_ptr_chasing && !s1_ptr_chasing_canceled) 1450 XSPerfAccumulate("load_to_load_forward_try", s1_try_ptr_chasing) 1451 XSPerfAccumulate("load_to_load_forward_fail", s1_cancel_ptr_chasing) 1452 XSPerfAccumulate("load_to_load_forward_fail_cancelled", s1_cancel_ptr_chasing && s1_ptr_chasing_canceled) 1453 XSPerfAccumulate("load_to_load_forward_fail_wakeup_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && s1_not_fast_match) 1454 XSPerfAccumulate("load_to_load_forward_fail_op_not_ld", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && s1_fu_op_type_not_ld) 1455 XSPerfAccumulate("load_to_load_forward_fail_addr_align", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && s1_addr_misaligned) 1456 XSPerfAccumulate("load_to_load_forward_fail_set_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && !s1_addr_misaligned && s1_addr_mismatch) 1457 1458 // bug lyq: some signals in perfEvents are no longer suitable for the current MemBlock design 1459 // hardware performance counter 1460 val perfEvents = Seq( 1461 ("load_s0_in_fire ", s0_fire ), 1462 ("load_to_load_forward ", s1_fire && s1_try_ptr_chasing && !s1_ptr_chasing_canceled ), 1463 ("stall_dcache ", s0_valid && s0_can_go && !io.ldu_io.dcache.req.ready ), 1464 ("load_s1_in_fire ", s0_fire ), 1465 ("load_s1_tlb_miss ", s1_fire && io.tlb.resp.bits.miss ), 1466 ("load_s2_in_fire ", s1_fire ), 1467 ("load_s2_dcache_miss ", s2_fire && io.ldu_io.dcache.resp.bits.miss ), 1468 ) 1469 generatePerfEvent() 1470}