1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.rob.RobPtr 26import xiangshan.backend.Bundles._ 27import xiangshan.mem._ 28import xiangshan.backend.fu.vector.Bundles._ 29 30 31class VSplitPipeline(isVStore: Boolean = false)(implicit p: Parameters) extends VLSUModule{ 32 val io = IO(new VSplitPipelineIO(isVStore)) 33 // will be override later 34 def us_whole_reg(fuOpType: UInt): Bool = false.B 35 def us_mask(fuOpType: UInt): Bool = false.B 36 def us_fof(fuOpType: UInt): Bool = false.B 37 38 val vdIdxReg = RegInit(0.U(3.W)) 39 40 val s1_ready = WireInit(false.B) 41 io.in.ready := s1_ready 42 43 /**----------------------------------------------------------- 44 * s0 stage 45 * decode and generate AlignedType, uop mask, preIsSplit 46 * ---------------------------------------------------------- 47 */ 48 val s0_vtype = io.in.bits.uop.vpu.vtype 49 val s0_sew = s0_vtype.vsew 50 val s0_eew = io.in.bits.uop.vpu.veew 51 val s0_lmul = s0_vtype.vlmul 52 // when load whole register or unit-stride masked , emul should be 1 53 val s0_fuOpType = io.in.bits.uop.fuOpType 54 val s0_mop = s0_fuOpType(6, 5) 55 val s0_nf = Mux(us_whole_reg(s0_fuOpType), 0.U, io.in.bits.uop.vpu.nf) 56 val s0_vm = io.in.bits.uop.vpu.vm 57 val s0_emul = Mux(us_whole_reg(s0_fuOpType) ,GenUSWholeEmul(io.in.bits.uop.vpu.nf), Mux(us_mask(s0_fuOpType), 0.U(mulBits.W), EewLog2(s0_eew) - s0_sew + s0_lmul)) 58 val s0_preIsSplit = !(isUnitStride(s0_mop) && !us_fof(s0_fuOpType)) 59 val s0_nfield = s0_nf +& 1.U 60 61 val s0_valid = Wire(Bool()) 62 val s0_kill = io.in.bits.uop.robIdx.needFlush(io.redirect) 63 val s0_can_go = s1_ready 64 val s0_fire = s0_valid && s0_can_go 65 val s0_out = Wire(new VLSBundle(isVStore)) 66 67 val isUsWholeReg = isUnitStride(s0_mop) && us_whole_reg(s0_fuOpType) 68 val isMaskReg = isUnitStride(s0_mop) && us_mask(s0_fuOpType) 69 val isSegment = s0_nf =/= 0.U && !us_whole_reg(s0_fuOpType) 70 val instType = Cat(isSegment, s0_mop) 71 val uopIdx = io.in.bits.uop.vpu.vuopIdx 72 val uopIdxInField = GenUopIdxInField(instType, s0_emul, s0_lmul, uopIdx) 73 val vdIdxInField = GenVdIdxInField(instType, s0_emul, s0_lmul, uopIdxInField) 74 val lmulLog2 = Mux(s0_lmul.asSInt >= 0.S, 0.U, s0_lmul) 75 val emulLog2 = Mux(s0_emul.asSInt >= 0.S, 0.U, s0_emul) 76 val numEewLog2 = emulLog2 - EewLog2(s0_eew) 77 val numSewLog2 = lmulLog2 - s0_sew 78 val numFlowsSameVdLog2 = Mux( 79 isIndexed(instType), 80 log2Up(VLENB).U - s0_sew(1,0), 81 log2Up(VLENB).U - s0_eew(1,0) 82 ) 83 // numUops = nf * max(lmul, emul) 84 val lmulLog2Pos = Mux(s0_lmul.asSInt < 0.S, 0.U, s0_lmul) 85 val emulLog2Pos = Mux(s0_emul.asSInt < 0.S, 0.U, s0_emul) 86 val numUops = Mux( 87 isIndexed(s0_mop) && s0_lmul.asSInt > s0_emul.asSInt, 88 (s0_nf +& 1.U) << lmulLog2Pos, 89 (s0_nf +& 1.U) << emulLog2Pos 90 ) 91 92 val vvl = io.in.bits.src_vl.asTypeOf(VConfig()).vl 93 val evl = Mux(isUsWholeReg, 94 GenUSWholeRegVL(io.in.bits.uop.vpu.nf +& 1.U, s0_eew), 95 Mux(isMaskReg, 96 GenUSMaskRegVL(vvl), 97 vvl)) 98 val vvstart = io.in.bits.uop.vpu.vstart 99 val alignedType = Mux(isIndexed(instType), s0_sew(1, 0), s0_eew(1, 0)) 100 val broadenAligendType = Mux(s0_preIsSplit, Cat("b0".U, alignedType), "b100".U) // if is unit-stride, use 128-bits memory access 101 val flowsLog2 = GenRealFlowLog2(instType, s0_emul, s0_lmul, s0_eew, s0_sew) 102 val flowsPrevThisUop = uopIdxInField << flowsLog2 // # of flows before this uop in a field 103 val flowsPrevThisVd = vdIdxInField << numFlowsSameVdLog2 // # of flows before this vd in a field 104 val flowsIncludeThisUop = (uopIdxInField +& 1.U) << flowsLog2 // # of flows before this uop besides this uop 105 val flowNum = io.in.bits.flowNum.get 106 val srcMask = GenFlowMask(Mux(s0_vm, Fill(VLEN, 1.U(1.W)), io.in.bits.src_mask), vvstart, evl, true) 107 108 val flowMask = ((srcMask & 109 UIntToMask(flowsIncludeThisUop.asUInt, VLEN + 1) & 110 (~UIntToMask(flowsPrevThisUop.asUInt, VLEN)).asUInt 111 ) >> flowsPrevThisVd)(VLENB - 1, 0) 112 val vlmax = GenVLMAX(s0_lmul, s0_sew) 113 114 // connect 115 s0_out := DontCare 116 s0_out match {case x => 117 x.uop := io.in.bits.uop 118 x.uop.vpu.vl := evl 119 x.uop.uopIdx := uopIdx 120 x.uop.numUops := numUops 121 x.uop.lastUop := (uopIdx +& 1.U) === numUops 122 x.uop.vpu.nf := s0_nf 123 x.flowMask := flowMask 124 x.byteMask := GenUopByteMask(flowMask, Cat("b0".U, alignedType))(VLENB - 1, 0) 125 x.fof := isUnitStride(s0_mop) && us_fof(s0_fuOpType) 126 x.baseAddr := io.in.bits.src_rs1 127 x.stride := io.in.bits.src_stride 128 x.flowNum := flowNum 129 x.nfields := s0_nfield 130 x.vm := s0_vm 131 x.usWholeReg := isUsWholeReg 132 x.usMaskReg := isMaskReg 133 x.eew := s0_eew 134 x.sew := s0_sew 135 x.emul := s0_emul 136 x.lmul := s0_lmul 137 x.vlmax := Mux(isUsWholeReg, evl, vlmax) 138 x.instType := instType 139 x.data := io.in.bits.src_vs3 140 x.vdIdxInField := vdIdxInField 141 x.preIsSplit := s0_preIsSplit 142 x.alignedType := broadenAligendType 143 } 144 s0_valid := io.in.valid && !s0_kill 145 /**------------------------------------- 146 * s1 stage 147 * ------------------------------------ 148 * generate UopOffset 149 */ 150 val s1_valid = RegInit(false.B) 151 val s1_kill = Wire(Bool()) 152 val s1_in = Wire(new VLSBundle(isVStore)) 153 val s1_can_go = io.out.ready && io.toMergeBuffer.resp.valid 154 val s1_fire = s1_valid && !s1_kill && s1_can_go 155 156 s1_ready := s1_kill || !s1_valid || io.out.ready && io.toMergeBuffer.resp.valid 157 158 when(s0_fire){ 159 s1_valid := true.B 160 }.elsewhen(s1_fire){ 161 s1_valid := false.B 162 }.elsewhen(s1_kill){ 163 s1_valid := false.B 164 } 165 s1_in := RegEnable(s0_out, s0_fire) 166 167 val s1_uopidx = s1_in.uop.vpu.vuopIdx 168 val s1_nf = s1_in.uop.vpu.nf 169 val s1_nfields = s1_in.nfields 170 val s1_eew = s1_in.eew 171 val s1_instType = s1_in.instType 172 val s1_stride = s1_in.stride 173 val s1_vmask = FillInterleaved(8, s1_in.byteMask)(VLEN-1, 0) 174 val s1_alignedType = s1_in.alignedType 175 val s1_notIndexedStride = Mux( // stride for strided/unit-stride instruction 176 isStrided(s1_instType), 177 s1_stride(XLEN - 1, 0), // for strided load, stride = x[rs2] 178 s1_nfields << s1_eew(1, 0) // for unit-stride load, stride = eew * NFIELDS 179 ) 180 val uopOffset = (s1_uopidx >> s1_nf) << s1_alignedType 181 val stride = Mux(isIndexed(s1_instType), s1_stride, s1_notIndexedStride) // if is index instructions, get index when split 182 183 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) 184 185 // query mergeBuffer 186 io.toMergeBuffer.req.valid := s1_fire // only can_go will get MergeBuffer entry 187 io.toMergeBuffer.req.bits.flowNum := Mux(s1_in.preIsSplit, PopCount(s1_in.flowMask), flowNum) 188 io.toMergeBuffer.req.bits.data := s1_in.data 189 io.toMergeBuffer.req.bits.uop := s1_in.uop 190 io.toMergeBuffer.req.bits.mask := s1_in.flowMask 191 io.toMergeBuffer.req.bits.vaddr := DontCare 192 io.toMergeBuffer.req.bits.vdIdx := vdIdxReg 193// io.toMergeBuffer.req.bits.vdOffset := 194 195 when (s1_in.uop.lastUop && s1_valid || s1_kill) { 196 vdIdxReg := 0.U 197 }.elsewhen(s1_valid) { 198 vdIdxReg := vdIdxReg + 1.U 199 XSError(vdIdxReg + 1.U === 0.U, s"Overflow! The number of vd should be less than 8\n") 200 } 201 // out connect 202 io.out.valid := s1_valid && io.toMergeBuffer.resp.valid 203 io.out.bits := s1_in 204 io.out.bits.uopOffset := uopOffset 205 io.out.bits.stride := stride 206 io.out.bits.mBIndex := io.toMergeBuffer.resp.bits.mBIndex 207 208 XSPerfAccumulate("split_out", io.out.fire) 209 XSPerfAccumulate("pipe_block", io.out.valid && !io.out.ready) 210 XSPerfAccumulate("mbuffer_block", s1_valid && io.out.ready && !io.toMergeBuffer.resp.valid) 211} 212 213abstract class VSplitBuffer(isVStore: Boolean = false)(implicit p: Parameters) extends VLSUModule{ 214 val io = IO(new VSplitBufferIO(isVStore)) 215 216 val bufferSize: Int 217 218 class VSplitPtr(implicit p: Parameters) extends CircularQueuePtr[VSplitPtr](bufferSize){ 219 } 220 221 object VSplitPtr { 222 def apply(f: Bool, v: UInt)(implicit p: Parameters): VSplitPtr = { 223 val ptr = Wire(new VSplitPtr) 224 ptr.flag := f 225 ptr.value := v 226 ptr 227 } 228 } 229 230 val uopq = Reg(Vec(bufferSize, new VLSBundle(isVStore))) 231 val valid = RegInit(VecInit(Seq.fill(bufferSize)(false.B))) 232 val vstart = RegInit(VecInit(Seq.fill(bufferSize)(0.U(elemIdxBits.W)))) // index of the exception element 233 val vl = RegInit(VecInit(Seq.fill(bufferSize)(0.U.asTypeOf(Valid(UInt(elemIdxBits.W)))))) // only for fof instructions that modify vl 234 val srcMaskVec = Reg(Vec(bufferSize, UInt(VLEN.W))) 235 // ptr 236 val enqPtr = RegInit(0.U.asTypeOf(new VSplitPtr)) 237 val deqPtr = RegInit(0.U.asTypeOf(new VSplitPtr)) 238 // for split 239 val splitIdx = RegInit(0.U(flowIdxBits.W)) 240 val strideOffsetReg = RegInit(0.U(VLEN.W)) 241 242 /** 243 * Redirect 244 */ 245 val flushed = WireInit(VecInit(Seq.fill(bufferSize)(false.B))) // entry has been flushed by the redirect arrived in the pre 1 cycle 246 val flushVec = (valid zip flushed).zip(uopq).map { case ((v, f), entry) => v && entry.uop.robIdx.needFlush(io.redirect) && !f } 247 val flushEnq = io.in.fire && io.in.bits.uop.robIdx.needFlush(io.redirect) 248 val flushNumReg = RegNext(PopCount(flushEnq +: flushVec)) 249 val redirectReg = RegNext(io.redirect) 250 val flushVecReg = RegNext(WireInit(VecInit(flushVec))) 251 252 // enqueue 253 when (io.in.fire && !flushEnq) { 254 val id = enqPtr.value 255 uopq(id) := io.in.bits 256 valid(id) := true.B 257 } 258 io.in.ready := isNotBefore(enqPtr, deqPtr) 259 260 //split uops 261 val issueValid = valid(deqPtr.value) 262 val issueEntry = uopq(deqPtr.value) 263 val issueMbIndex = issueEntry.mBIndex 264 val issueFlowNum = issueEntry.flowNum 265 val issueBaseAddr = issueEntry.baseAddr 266 val issueUop = issueEntry.uop 267 val issueUopIdx = issueUop.vpu.vuopIdx 268 val issueInstType = issueEntry.instType 269 val issueUopOffset = issueEntry.uopOffset 270 val issueEew = issueEntry.eew 271 val issueSew = issueEntry.sew 272 val issueLmul = issueEntry.emul 273 val issueEmul = issueEntry.lmul 274 val issueAlignedType = issueEntry.alignedType 275 val issuePreIsSplit = issueEntry.preIsSplit 276 val issueByteMask = issueEntry.byteMask 277 val elemIdx = GenElemIdx( 278 instType = issueInstType, 279 emul = issueEmul, 280 lmul = issueLmul, 281 eew = issueEew, 282 sew = issueSew, 283 uopIdx = issueUopIdx, 284 flowIdx = splitIdx 285 ) // elemIdx inside an inst, for exception 286 val indexedStride = IndexAddr( // index for indexed instruction 287 index = issueEntry.stride, 288 flow_inner_idx = ((splitIdx << issueEew(1, 0))(vOffsetBits - 1, 0) >> issueEew(1, 0)).asUInt, 289 eew = issueEew 290 ) 291 val issueStride = Mux(isIndexed(issueInstType), indexedStride, strideOffsetReg) 292 val vaddr = issueBaseAddr + issueUopOffset + issueStride 293 val mask = genVWmask128(vaddr ,issueAlignedType) // scala maske for flow 294 val flowMask = issueEntry.flowMask 295 val vecActive = (flowMask & UIntToOH(splitIdx)).orR 296 /* 297 * Unit-Stride split to one flow or two flow. 298 * for Unit-Stride, if uop's addr is aligned with 128-bits, split it to one flow, otherwise split two 299 */ 300 301 val usAligned128 = (vaddr(3,0) === 0.U)// addr 128-bit aligned 302 val usSplitMask = genUSSplitMask(issueByteMask, splitIdx, vaddr(3,0)) 303 val usNoSplit = (usAligned128 || !(vaddr(3,0) +& PopCount(usSplitMask))(4)) && !issuePreIsSplit && (splitIdx === 0.U)// unit-stride uop don't need to split into two flow 304 val usSplitVaddr = genUSSplitAddr(vaddr, splitIdx) 305 val regOffset = vaddr(3,0) // offset in 256-bits vd 306 XSError((splitIdx > 1.U && usNoSplit) || (splitIdx > 1.U && !issuePreIsSplit) , "Unit-Stride addr split error!\n") 307 308 // data 309 io.out.bits match { case x => 310 x.uop := issueUop 311 x.vaddr := Mux(!issuePreIsSplit, usSplitVaddr, vaddr) 312 x.alignedType := issueAlignedType 313 x.isvec := true.B 314 x.mask := Mux(!issuePreIsSplit, usSplitMask, mask) 315 x.reg_offset := regOffset //for merge unit-stride data 316 x.vecActive := vecActive 317 x.is_first_ele := DontCare 318 x.usSecondInv := usNoSplit 319 x.elemIdx := Mux(!issuePreIsSplit, splitIdx, elemIdx) // if is Unit-Stride, elemIdx is the index of 2 splited mem request (for merge data) 320 x.uop_unit_stride_fof := DontCare 321 x.isFirstIssue := DontCare 322 x.mBIndex := issueMbIndex 323 } 324 325 //update enqptr 326 when (redirectReg.valid && flushNumReg =/= 0.U) { 327 enqPtr := enqPtr - flushNumReg 328 }.otherwise { 329 when (io.in.fire) { 330 enqPtr := enqPtr + 1.U 331 } 332 } 333 334 // flush queue 335 for (i <- 0 until bufferSize) { 336 when(flushVecReg(i) && redirectReg.valid && flushNumReg =/= 0.U) { 337 valid(i) := false.B 338 flushed(i) := true.B 339 } 340 } 341 342 /* Execute logic */ 343 /** Issue to scala pipeline**/ 344 val canIssue = Wire(Bool()) 345 val allowIssue = io.out.ready 346 val doIssue = Wire(Bool()) 347 val issueCount = Mux(usNoSplit, 2.U,PopCount(doIssue)) // for dont need split unit-stride, issue two flow 348 349 // handshake 350 val thisPtr = deqPtr.value 351 canIssue := !issueUop.robIdx.needFlush(io.redirect) && deqPtr < enqPtr 352 doIssue := canIssue && allowIssue 353 when (!RegNext(io.redirect.valid) || distanceBetween(enqPtr, deqPtr) > flushNumReg) { 354 when ((splitIdx < (issueFlowNum - issueCount)) && doIssue) { 355 // The uop has not been entirly splited yet 356 splitIdx := splitIdx + issueCount 357 strideOffsetReg := strideOffsetReg + issueStride 358 }.otherwise { 359 when (doIssue) { 360 // The uop is done spliting 361 splitIdx := 0.U(flowIdxBits.W) // initialize flowIdx 362 valid(deqPtr.value) := false.B 363 strideOffsetReg := 0.U 364 deqPtr := deqPtr + 1.U 365 } 366 } 367 }.otherwise { 368 splitIdx := 0.U(flowIdxBits.W) // initialize flowIdx 369 strideOffsetReg := 0.U 370 } 371 372 // out connect 373 io.out.valid := canIssue && (vecActive || !issuePreIsSplit) // TODO: inactive uop do not send to pipeline 374 375 XSPerfAccumulate("out_valid", io.out.valid) 376 XSPerfAccumulate("out_fire", io.out.fire) 377 XSPerfAccumulate("out_fire_unitstride", io.out.fire && !issuePreIsSplit) 378 XSPerfAccumulate("unitstride_vlenAlign", io.out.fire && !issuePreIsSplit && io.out.bits.vaddr(3, 0) === 0.U) 379 XSPerfAccumulate("unitstride_invalid", io.out.ready && canIssue && !issuePreIsSplit && PopCount(io.out.bits.mask).orR) 380 381 QueuePerf(bufferSize, distanceBetween(enqPtr, deqPtr), !io.in.ready) 382} 383 384class VSSplitBufferImp(implicit p: Parameters) extends VSplitBuffer(isVStore = true){ 385 override lazy val bufferSize = SplitBufferSize 386 // split data 387 val flowData = GenVSData( 388 data = issueEntry.data.asUInt, 389 elemIdx = splitIdx, 390 alignedType = issueAlignedType 391 ) 392 val usSplitData = genUSSplitData(issueEntry.data.asUInt, splitIdx, vaddr(3,0)) 393 394 val sqIdx = issueUop.sqIdx + splitIdx 395 io.out.bits.uop.sqIdx := sqIdx 396 397 // send data to sq 398 val vstd = io.vstd.get 399 vstd.valid := canIssue 400 vstd.bits.uop := issueUop 401 vstd.bits.uop.sqIdx := sqIdx 402 vstd.bits.data := Mux(!issuePreIsSplit, usSplitData, flowData) 403 vstd.bits.debug := DontCare 404 vstd.bits.vdIdx.get := DontCare 405 vstd.bits.vdIdxInField.get := DontCare 406 vstd.bits.mask.get := Mux(!issuePreIsSplit, usSplitMask, mask) 407 408} 409 410class VLSplitBufferImp(implicit p: Parameters) extends VSplitBuffer(isVStore = false){ 411 override lazy val bufferSize = SplitBufferSize 412 io.out.bits.uop.lqIdx := issueUop.lqIdx + splitIdx 413} 414 415class VSSplitPipelineImp(implicit p: Parameters) extends VSplitPipeline(isVStore = true){ 416 override def us_whole_reg(fuOpType: UInt): Bool = fuOpType === VstuType.vsr 417 override def us_mask(fuOpType: UInt): Bool = fuOpType === VstuType.vsm 418 override def us_fof(fuOpType: UInt): Bool = false.B // dont have vector fof store 419} 420 421class VLSplitPipelineImp(implicit p: Parameters) extends VSplitPipeline(isVStore = false){ 422 423 override def us_whole_reg(fuOpType: UInt): Bool = fuOpType === VlduType.vlr 424 override def us_mask(fuOpType: UInt): Bool = fuOpType === VlduType.vlm 425 override def us_fof(fuOpType: UInt): Bool = fuOpType === VlduType.vleff 426} 427 428class VLSplitImp(implicit p: Parameters) extends VLSUModule{ 429 val io = IO(new VSplitIO(isVStore=false)) 430 val splitPipeline = Module(new VLSplitPipelineImp()) 431 val splitBuffer = Module(new VLSplitBufferImp()) 432 // Split Pipeline 433 splitPipeline.io.in <> io.in 434 splitPipeline.io.redirect <> io.redirect 435 io.toMergeBuffer <> splitPipeline.io.toMergeBuffer 436 437 // Split Buffer 438 splitBuffer.io.in <> splitPipeline.io.out 439 splitBuffer.io.redirect <> io.redirect 440 io.out <> splitBuffer.io.out 441} 442 443class VSSplitImp(implicit p: Parameters) extends VLSUModule{ 444 val io = IO(new VSplitIO(isVStore=true)) 445 val splitPipeline = Module(new VSSplitPipelineImp()) 446 val splitBuffer = Module(new VSSplitBufferImp()) 447 // Split Pipeline 448 splitPipeline.io.in <> io.in 449 splitPipeline.io.redirect <> io.redirect 450 io.toMergeBuffer <> splitPipeline.io.toMergeBuffer 451 452 // Split Buffer 453 splitBuffer.io.in <> splitPipeline.io.out 454 splitBuffer.io.redirect <> io.redirect 455 io.out <> splitBuffer.io.out 456 io.vstd.get <> splitBuffer.io.vstd.get 457} 458 459