1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import utility._ 24import utils._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput} 27import xiangshan.backend.rob.RobPtr 28import xiangshan.cache._ 29import xiangshan.backend.fu.FenceToSbuffer 30import xiangshan.cache.wpu.ReplayCarry 31import xiangshan.mem.prefetch.PrefetchReqBundle 32import math._ 33 34object genWmask { 35 def apply(addr: UInt, sizeEncode: UInt): UInt = { 36 (LookupTree(sizeEncode, List( 37 "b00".U -> 0x1.U, //0001 << addr(2:0) 38 "b01".U -> 0x3.U, //0011 39 "b10".U -> 0xf.U, //1111 40 "b11".U -> 0xff.U //11111111 41 )) << addr(2, 0)).asUInt 42 } 43} 44 45object genVWmask { 46 def apply(addr: UInt, sizeEncode: UInt): UInt = { 47 (LookupTree(sizeEncode, List( 48 "b00".U -> 0x1.U, //0001 << addr(2:0) 49 "b01".U -> 0x3.U, //0011 50 "b10".U -> 0xf.U, //1111 51 "b11".U -> 0xff.U //11111111 52 )) << addr(3, 0)).asUInt 53 } 54} 55 56object genWdata { 57 def apply(data: UInt, sizeEncode: UInt): UInt = { 58 LookupTree(sizeEncode, List( 59 "b00".U -> Fill(16, data(7, 0)), 60 "b01".U -> Fill(8, data(15, 0)), 61 "b10".U -> Fill(4, data(31, 0)), 62 "b11".U -> Fill(2, data(63,0)) 63 )) 64 } 65} 66 67object shiftDataToLow { 68 def apply(addr: UInt,data : UInt): UInt = { 69 Mux(addr(3), (data >> 64).asUInt,data) 70 } 71} 72object shiftMaskToLow { 73 def apply(addr: UInt,mask: UInt): UInt = { 74 Mux(addr(3),(mask >> 8).asUInt,mask) 75 } 76} 77 78class LsPipelineBundle(implicit p: Parameters) extends XSBundle 79 with HasDCacheParameters 80 with HasVLSUParameters { 81 val uop = new DynInst 82 val vaddr = UInt(VAddrBits.W) 83 val paddr = UInt(PAddrBits.W) 84 // val func = UInt(6.W) 85 val mask = UInt((VLEN/8).W) 86 val data = UInt((VLEN+1).W) 87 val wlineflag = Bool() // store write the whole cache line 88 89 val miss = Bool() 90 val tlbMiss = Bool() 91 val ptwBack = Bool() 92 val mmio = Bool() 93 val atomic = Bool() 94 val rsIdx = UInt(log2Up(MemIQSizeMax).W) 95 96 val forwardMask = Vec(VLEN/8, Bool()) 97 val forwardData = Vec(VLEN/8, UInt(8.W)) 98 99 // prefetch 100 val isPrefetch = Bool() 101 val isHWPrefetch = Bool() 102 def isSWPrefetch = isPrefetch && !isHWPrefetch 103 104 // vector 105 val isvec = Bool() 106 val isLastElem = Bool() 107 val is128bit = Bool() 108 val uop_unit_stride_fof = Bool() 109 val usSecondInv = Bool() 110 val elemIdx = UInt(elemIdxBits.W) 111 val alignedType = UInt(alignTypeBits.W) 112 val mbIndex = UInt(max(vlmBindexBits, vsmBindexBits).W) 113 // val rob_idx_valid = Vec(2,Bool()) 114 // val inner_idx = Vec(2,UInt(3.W)) 115 // val rob_idx = Vec(2,new RobPtr) 116 val reg_offset = UInt(vOffsetBits.W) 117 // val offset = Vec(2,UInt(4.W)) 118 val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element 119 val is_first_ele = Bool() 120 // val flowPtr = new VlflowPtr() // VLFlowQueue ptr 121 // val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 122 123 // For debug usage 124 val isFirstIssue = Bool() 125 val hasROBEntry = Bool() 126 127 // For load replay 128 val isLoadReplay = Bool() 129 val isFastPath = Bool() 130 val isFastReplay = Bool() 131 val replayCarry = new ReplayCarry(nWays) 132 133 // For dcache miss load 134 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 135 val handledByMSHR = Bool() 136 val replacementUpdated = Bool() 137 val missDbUpdated = Bool() 138 139 val forward_tlDchannel = Bool() 140 val dcacheRequireReplay = Bool() 141 val delayedLoadError = Bool() 142 val lateKill = Bool() 143 val feedbacked = Bool() 144 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 145 // loadQueueReplay index. 146 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 147} 148 149class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 150 val meta_prefetch = UInt(L1PfSourceBits.W) 151 val meta_access = Bool() 152 153 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false) = { 154 if (latch) vaddr := RegNext(input.vaddr) else vaddr := input.vaddr 155 if (latch) paddr := RegNext(input.paddr) else paddr := input.paddr 156 if (latch) mask := RegNext(input.mask) else mask := input.mask 157 if (latch) data := RegNext(input.data) else data := input.data 158 if (latch) uop := RegNext(input.uop) else uop := input.uop 159 if (latch) wlineflag := RegNext(input.wlineflag) else wlineflag := input.wlineflag 160 if (latch) miss := RegNext(input.miss) else miss := input.miss 161 if (latch) tlbMiss := RegNext(input.tlbMiss) else tlbMiss := input.tlbMiss 162 if (latch) ptwBack := RegNext(input.ptwBack) else ptwBack := input.ptwBack 163 if (latch) mmio := RegNext(input.mmio) else mmio := input.mmio 164 if (latch) rsIdx := RegNext(input.rsIdx) else rsIdx := input.rsIdx 165 if (latch) forwardMask := RegNext(input.forwardMask) else forwardMask := input.forwardMask 166 if (latch) forwardData := RegNext(input.forwardData) else forwardData := input.forwardData 167 if (latch) isPrefetch := RegNext(input.isPrefetch) else isPrefetch := input.isPrefetch 168 if (latch) isHWPrefetch := RegNext(input.isHWPrefetch) else isHWPrefetch := input.isHWPrefetch 169 if (latch) isFirstIssue := RegNext(input.isFirstIssue) else isFirstIssue := input.isFirstIssue 170 if (latch) hasROBEntry := RegNext(input.hasROBEntry) else hasROBEntry := input.hasROBEntry 171 if (latch) dcacheRequireReplay := RegNext(input.dcacheRequireReplay) else dcacheRequireReplay := input.dcacheRequireReplay 172 if (latch) schedIndex := RegNext(input.schedIndex) else schedIndex := input.schedIndex 173 if (latch) isvec := RegNext(input.isvec) else isvec := input.isvec 174 if (latch) isLastElem := RegNext(input.isLastElem) else isLastElem := input.isLastElem 175 if (latch) is128bit := RegNext(input.is128bit) else is128bit := input.is128bit 176 if (latch) vecActive := RegNext(input.vecActive) else vecActive := input.vecActive 177 if (latch) is_first_ele := RegNext(input.is_first_ele) else is_first_ele := input.is_first_ele 178 if (latch) uop_unit_stride_fof := RegNext(input.uop_unit_stride_fof) else uop_unit_stride_fof := input.uop_unit_stride_fof 179 if (latch) usSecondInv := RegNext(input.usSecondInv) else usSecondInv := input.usSecondInv 180 if (latch) reg_offset := RegNext(input.reg_offset) else reg_offset := input.reg_offset 181 if (latch) elemIdx := RegNext(input.elemIdx) else elemIdx := input.elemIdx 182 if (latch) alignedType := RegNext(input.alignedType) else alignedType := input.alignedType 183 if (latch) mbIndex := RegNext(input.mbIndex) else mbIndex := input.mbIndex 184 // if (latch) flowPtr := RegNext(input.flowPtr) else flowPtr := input.flowPtr 185 // if (latch) sflowPtr := RegNext(input.sflowPtr) else sflowPtr := input.sflowPtr 186 187 meta_prefetch := DontCare 188 meta_access := DontCare 189 forward_tlDchannel := DontCare 190 mshrid := DontCare 191 replayCarry := DontCare 192 atomic := DontCare 193 isLoadReplay := DontCare 194 isFastPath := DontCare 195 isFastReplay := DontCare 196 handledByMSHR := DontCare 197 replacementUpdated := DontCare 198 missDbUpdated := DontCare 199 delayedLoadError := DontCare 200 lateKill := DontCare 201 feedbacked := DontCare 202 ldCancel := DontCare 203 } 204 205 def asPrefetchReqBundle(): PrefetchReqBundle = { 206 val res = Wire(new PrefetchReqBundle) 207 res.vaddr := this.vaddr 208 res.paddr := this.paddr 209 res.pc := this.uop.pc 210 211 res 212 } 213} 214 215class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 216 217class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 218 // load inst replay informations 219 val rep_info = new LoadToLsqReplayIO 220 // queue entry data, except flag bits, will be updated if writeQueue is true, 221 // valid bit in LqWriteBundle will be ignored 222 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 223 224 225 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false) = { 226 if(latch) vaddr := RegNext(input.vaddr) else vaddr := input.vaddr 227 if(latch) paddr := RegNext(input.paddr) else paddr := input.paddr 228 if(latch) mask := RegNext(input.mask) else mask := input.mask 229 if(latch) data := RegNext(input.data) else data := input.data 230 if(latch) uop := RegNext(input.uop) else uop := input.uop 231 if(latch) wlineflag := RegNext(input.wlineflag) else wlineflag := input.wlineflag 232 if(latch) miss := RegNext(input.miss) else miss := input.miss 233 if(latch) tlbMiss := RegNext(input.tlbMiss) else tlbMiss := input.tlbMiss 234 if(latch) ptwBack := RegNext(input.ptwBack) else ptwBack := input.ptwBack 235 if(latch) mmio := RegNext(input.mmio) else mmio := input.mmio 236 if(latch) atomic := RegNext(input.atomic) else atomic := input.atomic 237 if(latch) rsIdx := RegNext(input.rsIdx) else rsIdx := input.rsIdx 238 if(latch) forwardMask := RegNext(input.forwardMask) else forwardMask := input.forwardMask 239 if(latch) forwardData := RegNext(input.forwardData) else forwardData := input.forwardData 240 if(latch) isPrefetch := RegNext(input.isPrefetch) else isPrefetch := input.isPrefetch 241 if(latch) isHWPrefetch := RegNext(input.isHWPrefetch) else isHWPrefetch := input.isHWPrefetch 242 if(latch) isFirstIssue := RegNext(input.isFirstIssue) else isFirstIssue := input.isFirstIssue 243 if(latch) hasROBEntry := RegNext(input.hasROBEntry) else hasROBEntry := input.hasROBEntry 244 if(latch) isLoadReplay := RegNext(input.isLoadReplay) else isLoadReplay := input.isLoadReplay 245 if(latch) isFastPath := RegNext(input.isFastPath) else isFastPath := input.isFastPath 246 if(latch) isFastReplay := RegNext(input.isFastReplay) else isFastReplay := input.isFastReplay 247 if(latch) mshrid := RegNext(input.mshrid) else mshrid := input.mshrid 248 if(latch) forward_tlDchannel := RegNext(input.forward_tlDchannel) else forward_tlDchannel := input.forward_tlDchannel 249 if(latch) replayCarry := RegNext(input.replayCarry) else replayCarry := input.replayCarry 250 if(latch) dcacheRequireReplay := RegNext(input.dcacheRequireReplay) else dcacheRequireReplay := input.dcacheRequireReplay 251 if(latch) schedIndex := RegNext(input.schedIndex) else schedIndex := input.schedIndex 252 if(latch) handledByMSHR := RegNext(input.handledByMSHR) else handledByMSHR := input.handledByMSHR 253 if(latch) replacementUpdated := RegNext(input.replacementUpdated) else replacementUpdated := input.replacementUpdated 254 if(latch) missDbUpdated := RegNext(input.missDbUpdated) else missDbUpdated := input.missDbUpdated 255 if(latch) delayedLoadError := RegNext(input.delayedLoadError) else delayedLoadError := input.delayedLoadError 256 if(latch) lateKill := RegNext(input.lateKill) else lateKill := input.lateKill 257 if(latch) feedbacked := RegNext(input.feedbacked) else feedbacked := input.feedbacked 258 if(latch) isvec := RegNext(input.isvec) else isvec := input.isvec 259 if(latch) is128bit := RegNext(input.is128bit) else is128bit := input.is128bit 260 if(latch) vecActive := RegNext(input.vecActive) else vecActive := input.vecActive 261 if(latch) uop_unit_stride_fof := RegNext(input.uop_unit_stride_fof) else uop_unit_stride_fof := input.uop_unit_stride_fof 262 if(latch) reg_offset := RegNext(input.reg_offset) else reg_offset := input.reg_offset 263 if(latch) mbIndex := RegNext(input.mbIndex) else mbIndex := input.mbIndex 264 265 rep_info := DontCare 266 data_wen_dup := DontCare 267 } 268} 269 270class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 271 val vaddr = Output(UInt(VAddrBits.W)) 272 val paddr = Output(UInt(PAddrBits.W)) 273 val mask = Output(UInt((VLEN/8).W)) 274 val uop = Output(new DynInst) // for replay 275 val pc = Output(UInt(VAddrBits.W)) //for debug 276 val valid = Output(Bool()) 277 278 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 279 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 280 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 281 282 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 283 val sqIdx = Output(new SqPtr) 284 285 // dataInvalid suggests store to load forward found forward should happen, 286 // but data is not available for now. If dataInvalid, load inst should 287 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 288 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 289 290 // matchInvalid suggests in store to load forward logic, paddr cam result does 291 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 292 // should be raised to flush SQ and committed sbuffer. 293 val matchInvalid = Input(Bool()) // resp to load_s2 294 295 // addrInvalid suggests store to load forward found forward should happen, 296 // but address (SSID) is not available for now. If addrInvalid, load inst should 297 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 298 val addrInvalid = Input(Bool()) 299} 300 301// LoadForwardQueryIO used in load pipeline 302// 303// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 304// PipeIO use predecoded sqIdxMask for better forward timing 305class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 306 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 307 // sqIdxMask is calcuated in earlier stage for better timing 308 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 309 310 // dataInvalid: addr match, but data is not valid for now 311 val dataInvalidFast = Input(Bool()) // resp to load_s1 312 // val dataInvalid = Input(Bool()) // resp to load_s2 313 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 314 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 315} 316 317// Query load queue for ld-ld violation 318// 319// Req should be send in load_s1 320// Resp will be generated 1 cycle later 321// 322// Note that query req may be !ready, as dcache is releasing a block 323// If it happens, a replay from rs is needed. 324class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 325 val uop = new DynInst 326 // mask: load's data mask. 327 val mask = UInt((VLEN/8).W) 328 329 // paddr: load's paddr. 330 val paddr = UInt(PAddrBits.W) 331 // dataInvalid: load data is invalid. 332 val data_valid = Bool() 333} 334 335class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 336 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 337 val rep_frm_fetch = Bool() 338} 339 340class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 341 val req = Decoupled(new LoadNukeQueryReq) 342 val resp = Flipped(Valid(new LoadNukeQueryResp)) 343 val revoke = Output(Bool()) 344} 345 346class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 347 // robIdx: Requestor's (a store instruction) rob index for match logic. 348 val robIdx = new RobPtr 349 350 // paddr: requestor's (a store instruction) physical address for match logic. 351 val paddr = UInt(PAddrBits.W) 352 353 // mask: requestor's (a store instruction) data width mask for match logic. 354 val mask = UInt((VLEN/8).W) 355} 356 357// Store byte valid mask write bundle 358// 359// Store byte valid mask write to SQ takes 2 cycles 360class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 361 val sqIdx = new SqPtr 362 val mask = UInt((VLEN/8).W) 363} 364 365class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 366 // old dcache: optimize data sram read fanout 367 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 368 // val bank_oh = UInt(DCacheBanks.W) 369 370 // new dcache 371 val respDcacheData = UInt(VLEN.W) 372 val forwardMask = Vec(VLEN/8, Bool()) 373 val forwardData = Vec(VLEN/8, UInt(8.W)) 374 val uop = new DynInst // for data selection, only fwen and fuOpType are used 375 val addrOffset = UInt(4.W) // for data selection 376 377 // forward tilelink D channel 378 val forward_D = Bool() 379 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 380 381 // forward mshr data 382 val forward_mshr = Bool() 383 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 384 385 val forward_result_valid = Bool() 386 387 def dcacheData(): UInt = { 388 // old dcache 389 // val dcache_data = Mux1H(bank_oh, bankedDcacheData) 390 // new dcache 391 val dcache_data = respDcacheData 392 val use_D = forward_D && forward_result_valid 393 val use_mshr = forward_mshr && forward_result_valid 394 Mux(use_D, forwardData_D.asUInt, Mux(use_mshr, forwardData_mshr.asUInt, dcache_data)) 395 } 396 397 def mergedData(): UInt = { 398 val rdataVec = VecInit((0 until VLEN / 8).map(j => 399 Mux(forwardMask(j), forwardData(j), dcacheData()(8*(j+1)-1, 8*j)) 400 )) 401 rdataVec.asUInt 402 } 403} 404 405// Load writeback data from load queue (refill) 406class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 407 val lqData = UInt(64.W) // load queue has merged data 408 val uop = new DynInst // for data selection, only fwen and fuOpType are used 409 val addrOffset = UInt(3.W) // for data selection 410 411 def mergedData(): UInt = { 412 lqData 413 } 414} 415 416// Bundle for load / store wait waking up 417class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 418 val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr)) 419 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 420} 421 422object AddPipelineReg { 423 class PipelineRegModule[T <: Data](gen: T) extends Module { 424 val io = IO(new Bundle() { 425 val in = Flipped(DecoupledIO(gen.cloneType)) 426 val out = DecoupledIO(gen.cloneType) 427 val isFlush = Input(Bool()) 428 }) 429 430 val valid = RegInit(false.B) 431 valid.suggestName("pipeline_reg_valid") 432 when (io.out.fire) { valid := false.B } 433 when (io.in.fire) { valid := true.B } 434 when (io.isFlush) { valid := false.B } 435 436 io.in.ready := !valid || io.out.ready 437 io.out.bits := RegEnable(io.in.bits, io.in.fire) 438 io.out.valid := valid //&& !isFlush 439 } 440 441 def apply[T <: Data] 442 (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool, 443 moduleName: Option[String] = None 444 ){ 445 val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType)) 446 if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get) 447 pipelineReg.io.in <> left 448 right <> pipelineReg.io.out 449 pipelineReg.io.isFlush := isFlush 450 } 451} 452