icache - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/frontend/icache

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
a0c65233	20-Sep-2023	Yinan Xu <[email protected]>	Bump difftst, huancun, and utility (#2316) * add `VERILATOR_5` macro to indicate v5.0 * update the clock gating primitive for Verilator v5.0 * remove the clock IOs for DifftestModules * add dontC Bump difftst, huancun, and utility (#2316) * add `VERILATOR_5` macro to indicate v5.0 * update the clock gating primitive for Verilator v5.0 * remove the clock IOs for DifftestModules * add dontCare for RefillEvent show more ... /XiangShan/difftest /XiangShan/huancun /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala ICacheMainPipe.scala ICacheMissUnit.scala IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/utility
95e60e55	18-Sep-2023	Tang Haojin <[email protected]>	LazyModule: do not inline lazy modules in XS (#2311) /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala ICache.scala InstrUncache.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
7d45a146	10-Sep-2023	Yinan Xu <[email protected]>	Bump difftest for Chisel-generated interfaces (#2284) We also add support for difftest with RISC-V Vector extension and nFused. L2 TLB check is disabled unexpectedly and will be fixed soon. /XiangShan/Makefile /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala ICacheMainPipe.scala ICacheMissUnit.scala IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/test/scala/top/SimTop.scala
cb6e5d3c	06-Sep-2023	ssszwic <[email protected]>	icache: change itlb port to no-blocked and new fdip (#2277) /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala ICache.scala ICacheBundle.scala ICacheMainPipe.scala ICacheMissUnit.scala IPrefetch.scala
76b0dfef	06-Sep-2023	Guokai Chen <[email protected]>	ICache: shrink to 64K (#2282) /XiangShan/Makefile /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/xiangshan/DbEntry.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala ICache.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/StorePrefetchBursts.scala /XiangShan/utility
0e8170d2	23-Aug-2023	ssszwic <[email protected]>	icache: balance the pipeline to optimize timing (#2255) /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
4b2a95e0	19-Aug-2023	Xiaokun-Pei <[email protected]>	icache: fix bug that loses tlb access fault (#2251) /XiangShan/.github/workflows/check_verilog.py /XiangShan/coupledL2 /XiangShan/huancun /XiangShan/scripts/cache/parseAddr.py /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala ICacheMainPipe.scala
b92c5693	16-Aug-2023	Tang Haojin <[email protected]>	utility: use unified `MemReqSource` (#2243) /XiangShan/Makefile /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/scripts/cache/convert_dir.sh /XiangShan/scripts/cache/convert_mp.sh /XiangShan/scripts/cache/convert_tllog.sh /XiangShan/scripts/cache/l2DB_helper.py /XiangShan/scripts/rollingplot.py /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/BusPerfMonitor.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/utility
9bba777e	11-Aug-2023	ssszwic <[email protected]>	ICache: fix timing (#2233) /XiangShan/.mill-version /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/rocket-chip /XiangShan/scripts/rollingplot.py /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/DbEntry.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/VictimList.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/WPU.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/WPUWrapper.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala ICache.scala ICacheMainPipe.scala IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/test/scala/cache/WpuTest.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
d2b20d1a	02-Jun-2023	Tang Haojin <[email protected]>	top-down: align top-down with Gem5 (#2085) * topdown: add defines of topdown counters enum * redirect: add redirect type for perf * top-down: add stallReason IOs frontend -> ctrlBlock -> de top-down: align top-down with Gem5 (#2085) * topdown: add defines of topdown counters enum * redirect: add redirect type for perf * top-down: add stallReason IOs frontend -> ctrlBlock -> decode -> rename -> dispatch * top-down: add dummy connections * top-down: update TopdownCounters * top-down: imp backend analysis and counter dump * top-down: add HartId in `addSource` * top-down: broadcast lqIdx of ROB head * top-down: frontend signal done * top-down: add memblock topdown interface * Bump HuanCun: add TopDownMonitor * top-down: receive and handle reasons in dispatch * top-down: remove previous top-down code * TopDown: add MemReqSource enum * TopDown: extend mshr_latency range * TopDown: add basic Req Source TODO: distinguish prefetch * dcache: distinguish L1DataPrefetch and CPUData * top-down: comment out debugging perf counters in ibuffer * TopDown: add path to pass MemReqSource to HuanCun * TopDown: use simpler logic to count reqSource and update Probe count * frontend: update topdown counters * Update HuanCun Topdown for MemReqSource * top-down: fix load stalls * top-down: Change the priority of different stall reasons * top-down: breakdown OtherCoreStall * sbuffer: fix eviction * when valid count reaches StoreBufferSize, do eviction * sbuffer: fix replaceIdx * If the way selected by the replacement algorithm cannot be written into dcache, its result is not used. * dcache, ldu: fix vaddr in missqueue This commit prevents the high bits of the virtual address from being truncated * fix-ldst_pri-230506 * mainpipe: fix loadsAreComing * top-down: disable dedup * top-down: remove old top-down config * top-down: split lq addr from ls_debug * top-down: purge previous top-down code * top-down: add debug_vaddr in LoadQueueReplay * add source rob_head_other_repay * remove load_l1_cache_stall_with/wihtou_bank_conflict * dcache: split CPUData & refill latency * split CPUData to CPUStoreData & CPULoadData & CPUAtomicData * monitor refill latency for all type of req * dcache: fix perfcounter in mq * io.req.bits.cancel should be applied when counting req.fire * TopDown: add TopDown for CPL2 in XiangShan * top-down: add hartid params to L2Cache * top-down: fix dispatch queue bound * top-down: no DqStall when robFull * topdown: buspmu support latency statistic (#2106) * perf: add buspmu between L2 and L3, support name argument * bump difftest * perf: busmonitor supports latency stat * config: fix cpl2 compatible problem * bump utility * bump coupledL2 * bump huancun * misc: adapt to utility key&field * config: fix key&field source, remove deprecated argument * buspmu: remove debug print * bump coupledl2&huancun * top-down: fix sq full condition * top-down: classify "lq full" load bound * top-down: bump submodules * bump coupledL2: fix reqSource in data path * bump coupledL2 --------- Co-authored-by: tastynoob <[email protected]> Co-authored-by: Guokai Chen <[email protected]> Co-authored-by: lixin <[email protected]> Co-authored-by: XiChen <[email protected]> Co-authored-by: Zhou Yaoyang <[email protected]> Co-authored-by: Lyn <[email protected]> Co-authored-by: wakafa <[email protected]> show more ... /XiangShan/Makefile /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/BusPerfMonitor.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala ICache.scala ICacheMainPipe.scala ICacheMissUnit.scala IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/utility
15ee59e4	25-May-2023	wakafa <[email protected]>	Merge coupledL2 into master (#2064) * icache: Acquire -> Get to L2 * gitmodules: add coupledL2 as submodule * cpl2: merge coupledL2 into master * Changes includes: * coupledL2 integratio Merge coupledL2 into master (#2064) * icache: Acquire -> Get to L2 * gitmodules: add coupledL2 as submodule * cpl2: merge coupledL2 into master * Changes includes: * coupledL2 integration * modify user&echo fields in i$/d$/ptw * set d$ never always-releasedata * remove hw perfcnt connection for L2 * bump utility * icache: remove unused releaseUnit * config: minimalconfig includes l2 * Otherwise, dirty bits maintainence may be broken * Known issue: L2 should have more than 1 bank to avoid compiling problem * bump Utility * bump coupledL2: fix bugs in dual-core * bump coupledL2 * icache: set icache as non-coherent node * bump coupledL2: fix dirty problem in L2 ProbeAckData --------- Co-authored-by: guohongyu <[email protected]> Co-authored-by: XiChen <[email protected]> show more ... /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala ICache.scala ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
40a95436	05-May-2023	guohongyu <[email protected]>	ICache: remove useless code ICache.scala ICacheMainPipe.scala ICacheMissUnit.scala IPrefetch.scala
5727817b	27-Apr-2023	guohongyu <[email protected]>	ICacfix mainPipe prefetch check condition ICacheMainPipe.scala
c2ba7c80	27-Apr-2023	guohongyu <[email protected]>	ICache: add hartId for difftest & disable mainPipe block check ICache.scala ICacheMainPipe.scala IPrefetch.scala
f304ee97	26-Apr-2023	guohongyu <[email protected]>	ICache: disable bankedMetaDiff & enable assert multi-hit in mainPipe ICache.scala ICacheMainPipe.scala
ece5f794	26-Apr-2023	guohongyu <[email protected]>	ICache: fix bankedMetaArray ready logic ICacheBankedArray.scala
1d4724e4	25-Apr-2023	guohongyu <[email protected]>	ICache: fix compile error IPrefetch.scala
7e9b92d0	25-Apr-2023	guohongyu <[email protected]>	ICache: merge master /XiangShan/.github/workflows/emu.yml /XiangShan/.github/workflows/nightly.yml /XiangShan/Makefile /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala ICacheBundle.scala /XiangShan/utility
71bba061	20-Apr-2023	HongYu Guo <[email protected]>	ICache：remove coherence & add fencei support (#2043) * ICache:send Get instead of Acquire to L2 * ICache:add vaild_array in metaArray * [WIP]ICache:annotate invalid coherence modules for icach ICache：remove coherence & add fencei support (#2043) * ICache:send Get instead of Acquire to L2 * ICache:add vaild_array in metaArray * [WIP]ICache:annotate invalid coherence modules for icache * ICache:delete invalid coherence modules for icache * ICache : add fencei logic * ICache : fix check multi-hit logic show more ... /XiangShan/.github/workflows/emu.yml /XiangShan/.github/workflows/nightly.yml /XiangShan/Makefile /XiangShan/debug/local_ci.py /XiangShan/difftest /XiangShan/huancun /XiangShan/scripts/constantHelper.py /XiangShan/scripts/gen_sep_mem.sh /XiangShan/scripts/top-down/README.md /XiangShan/scripts/top-down/top-down.sh /XiangShan/scripts/top-down/top_down.py /XiangShan/scripts/utils/convert.sh /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Generator.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/ArbiterHelper.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/DbEntry.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala ICache.scala ICacheBundle.scala ICacheMainPipe.scala ICacheMissUnit.scala IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/utility
2a6078bf	17-Apr-2023	guohongyu <[email protected]>	ICache : finish fencei support /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala ICache.scala ICacheBankedArray.scala ICacheMissUnit.scala IPrefetch.scala
34f9624d	17-Apr-2023	guohongyu <[email protected]>	ICache : fix compile error & make itlb and pmp port num more configurable /XiangShan/.github/workflows/emu.yml /XiangShan/.github/workflows/nightly.yml /XiangShan/Makefile /XiangShan/difftest /XiangShan/scripts/gen_sep_mem.sh /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Generator.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala ICache.scala ICacheBankedArray.scala IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/utility
0c26d810	06-Apr-2023	guohongyu <[email protected]>	[WIP] ICache: implement new bankedMetaArray & make prefetchPipe num Configurable /XiangShan/.github/workflows/emu.yml /XiangShan/.github/workflows/nightly.yml /XiangShan/difftest /XiangShan/huancun /XiangShan/scripts/top-down/README.md /XiangShan/scripts/top-down/top-down.sh /XiangShan/scripts/top-down/top_down.py /XiangShan/scripts/utils/convert.sh /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/constantin.txt /XiangShan/src/main/scala/xiangshan/DbEntry.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala ICache.scala ICacheBankedArray.scala IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/utility
64d7d412	23-Mar-2023	guohongyu <[email protected]>	ICache: IPFBuffer: use ptr queue to improve IPF entry utilization IPrefetch.scala
ebfdba16	23-Mar-2023	guohongyu <[email protected]>	ICache:generate diff module only when env.EnableDifftest=true ICacheMainPipe.scala
cb9c9c0f	23-Mar-2023	guohongyu <[email protected]>	ICache:improve IPrefetch filter logic & use Mux1H to get PIQ data in MainPipe /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala ICacheMainPipe.scala IPrefetch.scala
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