1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.fu.PMPRespBundle 27import xiangshan.backend.rob.{DebugLsInfoBundle, LsTopdownInfo, RobPtr} 28import xiangshan.cache._ 29import xiangshan.cache.wpu.ReplayCarry 30import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 31import xiangshan.mem.mdp._ 32 33class LoadToLsqReplayIO(implicit p: Parameters) extends XSBundle with HasDCacheParameters { 34 // mshr refill index 35 val mshr_id = UInt(log2Up(cfg.nMissEntries).W) 36 // get full data from store queue and sbuffer 37 val full_fwd = Bool() 38 // wait for data from store inst's store queue index 39 val data_inv_sq_idx = new SqPtr 40 // wait for address from store queue index 41 val addr_inv_sq_idx = new SqPtr 42 // replay carry 43 val rep_carry = new ReplayCarry(nWays) 44 // data in last beat 45 val last_beat = Bool() 46 // replay cause 47 val cause = Vec(LoadReplayCauses.allCauses, Bool()) 48 // performance debug information 49 val debug = new PerfDebugInfo 50 51 // alias 52 def mem_amb = cause(LoadReplayCauses.C_MA) 53 def tlb_miss = cause(LoadReplayCauses.C_TM) 54 def fwd_fail = cause(LoadReplayCauses.C_FF) 55 def dcache_rep = cause(LoadReplayCauses.C_DR) 56 def dcache_miss = cause(LoadReplayCauses.C_DM) 57 def wpu_fail = cause(LoadReplayCauses.C_WF) 58 def bank_conflict = cause(LoadReplayCauses.C_BC) 59 def rar_nack = cause(LoadReplayCauses.C_RAR) 60 def raw_nack = cause(LoadReplayCauses.C_RAW) 61 def nuke = cause(LoadReplayCauses.C_NK) 62 def need_rep = cause.asUInt.orR 63} 64 65 66class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 67 val ldin = DecoupledIO(new LqWriteBundle) 68 val uncache = Flipped(DecoupledIO(new ExuOutput)) 69 val ld_raw_data = Input(new LoadDataFromLQBundle) 70 val forward = new PipeLoadForwardQueryIO 71 val stld_nuke_query = new LoadNukeQueryIO 72 val ldld_nuke_query = new LoadNukeQueryIO 73 val trigger = Flipped(new LqTriggerIO) 74} 75 76class LoadToLoadIO(implicit p: Parameters) extends XSBundle { 77 val valid = Bool() 78 val data = UInt(XLEN.W) // load to load fast path is limited to ld (64 bit) used as vaddr src1 only 79 val dly_ld_err = Bool() 80} 81 82class LoadUnitTriggerIO(implicit p: Parameters) extends XSBundle { 83 val tdata2 = Input(UInt(64.W)) 84 val matchType = Input(UInt(2.W)) 85 val tEnable = Input(Bool()) // timing is calculated before this 86 val addrHit = Output(Bool()) 87 val lastDataHit = Output(Bool()) 88} 89 90class LoadUnit(implicit p: Parameters) extends XSModule 91 with HasLoadHelper 92 with HasPerfEvents 93 with HasDCacheParameters 94 with HasCircularQueuePtrHelper 95{ 96 val io = IO(new Bundle() { 97 // control 98 val redirect = Flipped(ValidIO(new Redirect)) 99 val csrCtrl = Flipped(new CustomCSRCtrlIO) 100 101 // int issue path 102 val ldin = Flipped(Decoupled(new ExuInput)) 103 val ldout = Decoupled(new ExuOutput) 104 val rsIdx = Input(UInt()) 105 val isFirstIssue = Input(Bool()) 106 107 // data path 108 val tlb = new TlbRequestIO(2) 109 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 110 val dcache = new DCacheLoadIO 111 val sbuffer = new LoadForwardQueryIO 112 val lsq = new LoadToLsqIO 113 val tl_d_channel = Input(new DcacheToLduForwardIO) 114 val forward_mshr = Flipped(new LduToMissqueueForwardIO) 115 val refill = Flipped(ValidIO(new Refill)) 116 val l2_hint = Input(Valid(new L2ToL1Hint)) 117 118 // fast wakeup 119 val fast_uop = ValidIO(new MicroOp) // early wakeup signal generated in load_s1, send to RS in load_s2 120 121 // trigger 122 val trigger = Vec(3, new LoadUnitTriggerIO) 123 124 // prefetch 125 val prefetch_train = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info 126 val prefetch_req = Flipped(ValidIO(new L1PrefetchReq)) // hardware prefetch to l1 cache req 127 128 // load to load fast path 129 val l2l_fwd_in = Input(new LoadToLoadIO) 130 val l2l_fwd_out = Output(new LoadToLoadIO) 131 val ld_fast_match = Input(Bool()) 132 val ld_fast_imm = Input(UInt(12.W)) 133 134 // rs feedback 135 val feedback_fast = ValidIO(new RSFeedback) // stage 2 136 val feedback_slow = ValidIO(new RSFeedback) // stage 3 137 138 // load ecc error 139 val s3_dly_ld_err = Output(Bool()) // Note that io.s3_dly_ld_err and io.lsq.s3_dly_ld_err is different 140 141 // schedule error query 142 val stld_nuke_query = Flipped(Vec(StorePipelineWidth, Valid(new StoreNukeQueryIO))) 143 144 // queue-based replay 145 val replay = Flipped(Decoupled(new LsPipelineBundle)) 146 val lq_rep_full = Input(Bool()) 147 148 // misc 149 val s2_ptr_chasing = Output(Bool()) // provide right pc for hw prefetch 150 151 // Load fast replay path 152 val fast_rep_in = Flipped(Decoupled(new LqWriteBundle)) 153 val fast_rep_out = Decoupled(new LqWriteBundle) 154 155 // perf 156 val debug_ls = Output(new DebugLsInfoBundle) 157 val lsTopdownInfo = Output(new LsTopdownInfo) 158 }) 159 160 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 161 162 // Pipeline 163 // -------------------------------------------------------------------------------- 164 // stage 0 165 // -------------------------------------------------------------------------------- 166 // generate addr, use addr to query DCache and DTLB 167 val s0_valid = Wire(Bool()) 168 val s0_kill = Wire(Bool()) 169 val s0_vaddr = Wire(UInt(VAddrBits.W)) 170 val s0_mask = Wire(UInt((VLEN/8).W)) 171 val s0_uop = Wire(new MicroOp) 172 val s0_has_rob_entry = Wire(Bool()) 173 val s0_rsIdx = Wire(UInt(log2Up(IssQueSize).W)) 174 val s0_mshrid = Wire(UInt()) 175 val s0_try_l2l = Wire(Bool()) 176 val s0_rep_carry = Wire(new ReplayCarry(nWays)) 177 val s0_isFirstIssue = Wire(Bool()) 178 val s0_fast_rep = Wire(Bool()) 179 val s0_ld_rep = Wire(Bool()) 180 val s0_l2l_fwd = Wire(Bool()) 181 val s0_sched_idx = Wire(UInt()) 182 val s0_can_go = s1_ready 183 val s0_fire = s0_valid && s0_can_go 184 val s0_out = Wire(new LqWriteBundle) 185 186 // load flow select/gen 187 // src0: super load replayed by LSQ (cache miss replay) (io.replay) 188 // src1: fast load replay (io.fast_rep_in) 189 // src2: load replayed by LSQ (io.replay) 190 // src3: hardware prefetch from prefetchor (high confidence) (io.prefetch) 191 // src4: int read / software prefetch first issue from RS (io.in) 192 // src5: vec read first issue from RS (TODO) 193 // src6: load try pointchaising when no issued or replayed load (io.fastpath) 194 // src7: hardware prefetch from prefetchor (high confidence) (io.prefetch) 195 // priority: high to low 196 val s0_rep_stall = io.ldin.valid && isAfter(io.replay.bits.uop.robIdx, io.ldin.bits.uop.robIdx) 197 val s0_super_ld_rep_valid = io.replay.valid && io.replay.bits.forward_tlDchannel 198 val s0_ld_fast_rep_valid = io.fast_rep_in.valid 199 val s0_ld_rep_valid = io.replay.valid && !io.replay.bits.forward_tlDchannel && !s0_rep_stall 200 val s0_high_conf_prf_valid = io.prefetch_req.valid && io.prefetch_req.bits.confidence > 0.U 201 val s0_int_iss_valid = io.ldin.valid // int flow first issue or software prefetch 202 val s0_vec_iss_valid = WireInit(false.B) // TODO 203 val s0_l2l_fwd_valid = io.l2l_fwd_in.valid 204 val s0_low_conf_prf_valid = io.prefetch_req.valid && io.prefetch_req.bits.confidence === 0.U 205 dontTouch(s0_super_ld_rep_valid) 206 dontTouch(s0_ld_fast_rep_valid) 207 dontTouch(s0_ld_rep_valid) 208 dontTouch(s0_high_conf_prf_valid) 209 dontTouch(s0_int_iss_valid) 210 dontTouch(s0_vec_iss_valid) 211 dontTouch(s0_l2l_fwd_valid) 212 dontTouch(s0_low_conf_prf_valid) 213 214 // load flow source ready 215 val s0_super_ld_rep_ready = WireInit(true.B) 216 val s0_ld_fast_rep_ready = !s0_super_ld_rep_valid 217 val s0_ld_rep_ready = !s0_super_ld_rep_valid && 218 !s0_ld_fast_rep_valid 219 val s0_high_conf_prf_ready = !s0_super_ld_rep_valid && 220 !s0_ld_fast_rep_valid && 221 !s0_ld_rep_valid 222 223 val s0_int_iss_ready = !s0_super_ld_rep_valid && 224 !s0_ld_fast_rep_valid && 225 !s0_ld_rep_valid && 226 !s0_high_conf_prf_valid 227 228 val s0_vec_iss_ready = !s0_super_ld_rep_valid && 229 !s0_ld_fast_rep_valid && 230 !s0_ld_rep_valid && 231 !s0_high_conf_prf_valid && 232 !s0_int_iss_valid 233 234 val s0_l2l_fwd_ready = !s0_super_ld_rep_valid && 235 !s0_ld_fast_rep_valid && 236 !s0_ld_rep_valid && 237 !s0_high_conf_prf_valid && 238 !s0_int_iss_valid && 239 !s0_vec_iss_valid 240 241 val s0_low_conf_prf_ready = !s0_super_ld_rep_valid && 242 !s0_ld_fast_rep_valid && 243 !s0_ld_rep_valid && 244 !s0_high_conf_prf_valid && 245 !s0_int_iss_valid && 246 !s0_vec_iss_valid && 247 !s0_l2l_fwd_valid 248 dontTouch(s0_super_ld_rep_ready) 249 dontTouch(s0_ld_fast_rep_ready) 250 dontTouch(s0_ld_rep_ready) 251 dontTouch(s0_high_conf_prf_ready) 252 dontTouch(s0_int_iss_ready) 253 dontTouch(s0_vec_iss_ready) 254 dontTouch(s0_l2l_fwd_ready) 255 dontTouch(s0_low_conf_prf_ready) 256 257 // load flow source select (OH) 258 val s0_super_ld_rep_select = s0_super_ld_rep_valid && s0_super_ld_rep_ready 259 val s0_ld_fast_rep_select = s0_ld_fast_rep_valid && s0_ld_fast_rep_ready 260 val s0_ld_rep_select = s0_ld_rep_valid && s0_ld_rep_ready 261 val s0_hw_prf_select = s0_high_conf_prf_ready && s0_high_conf_prf_valid || 262 s0_low_conf_prf_ready && s0_low_conf_prf_valid 263 val s0_int_iss_select = s0_int_iss_ready && s0_int_iss_valid 264 val s0_vec_iss_select = s0_vec_iss_ready && s0_vec_iss_valid 265 val s0_l2l_fwd_select = s0_l2l_fwd_ready && s0_l2l_fwd_valid 266 assert(!s0_vec_iss_select) // to be added 267 dontTouch(s0_super_ld_rep_select) 268 dontTouch(s0_ld_fast_rep_select) 269 dontTouch(s0_ld_rep_select) 270 dontTouch(s0_hw_prf_select) 271 dontTouch(s0_int_iss_select) 272 dontTouch(s0_vec_iss_select) 273 dontTouch(s0_l2l_fwd_select) 274 275 s0_valid := (s0_super_ld_rep_valid || 276 s0_ld_fast_rep_valid || 277 s0_ld_rep_valid || 278 s0_high_conf_prf_valid || 279 s0_int_iss_valid || 280 s0_vec_iss_valid || 281 s0_l2l_fwd_valid || 282 s0_low_conf_prf_valid) && io.dcache.req.ready && !s0_kill 283 284 // which is S0's out is ready and dcache is ready 285 val s0_try_ptr_chasing = s0_l2l_fwd_select 286 val s0_do_try_ptr_chasing = s0_try_ptr_chasing && s0_can_go && io.dcache.req.ready 287 val s0_ptr_chasing_vaddr = io.l2l_fwd_in.data(5, 0) +& io.ld_fast_imm(5, 0) 288 val s0_ptr_chasing_canceled = WireInit(false.B) 289 s0_kill := s0_ptr_chasing_canceled || (s0_out.uop.robIdx.needFlush(io.redirect) && !s0_try_ptr_chasing) 290 291 // prefetch related ctrl signal 292 val s0_prf = Wire(Bool()) 293 val s0_prf_rd = Wire(Bool()) 294 val s0_prf_wr = Wire(Bool()) 295 val s0_hw_prf = s0_hw_prf_select 296 297 // query DTLB 298 io.tlb.req.valid := s0_valid 299 io.tlb.req.bits.cmd := Mux(s0_prf, 300 Mux(s0_prf_wr, TlbCmd.write, TlbCmd.read), 301 TlbCmd.read 302 ) 303 io.tlb.req.bits.vaddr := Mux(s0_hw_prf_select, io.prefetch_req.bits.paddr, s0_vaddr) 304 io.tlb.req.bits.size := LSUOpType.size(s0_uop.ctrl.fuOpType) 305 io.tlb.req.bits.kill := s0_kill 306 io.tlb.req.bits.memidx.is_ld := true.B 307 io.tlb.req.bits.memidx.is_st := false.B 308 io.tlb.req.bits.memidx.idx := s0_uop.lqIdx.value 309 io.tlb.req.bits.debug.robIdx := s0_uop.robIdx 310 io.tlb.req.bits.no_translate := s0_hw_prf_select // hw b.reqetch addr does not need to be translated 311 io.tlb.req.bits.debug.pc := s0_uop.cf.pc 312 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 313 314 // query DCache 315 io.dcache.req.valid := s0_valid 316 io.dcache.req.bits.cmd := Mux(s0_prf_rd, 317 MemoryOpConstants.M_PFR, 318 Mux(s0_prf_wr, MemoryOpConstants.M_PFW, MemoryOpConstants.M_XRD) 319 ) 320 io.dcache.req.bits.vaddr := s0_vaddr 321 io.dcache.req.bits.mask := s0_mask 322 io.dcache.req.bits.data := DontCare 323 io.dcache.req.bits.isFirstIssue := s0_isFirstIssue 324 io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, LOAD_SOURCE.U) 325 io.dcache.req.bits.debug_robIdx := s0_uop.robIdx.value 326 io.dcache.req.bits.replayCarry := s0_rep_carry 327 io.dcache.req.bits.id := DontCare // TODO: update cache meta 328 329 // load flow priority mux 330 def fromNullSource() = { 331 s0_vaddr := 0.U 332 s0_mask := 0.U 333 s0_uop := 0.U.asTypeOf(new MicroOp) 334 s0_try_l2l := false.B 335 s0_has_rob_entry := false.B 336 s0_rsIdx := 0.U 337 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 338 s0_mshrid := 0.U 339 s0_isFirstIssue := false.B 340 s0_fast_rep := false.B 341 s0_ld_rep := false.B 342 s0_l2l_fwd := false.B 343 s0_prf := false.B 344 s0_prf_rd := false.B 345 s0_prf_wr := false.B 346 s0_sched_idx := 0.U 347 } 348 349 def fromFastReplaySource(src: LqWriteBundle) = { 350 s0_vaddr := src.vaddr 351 s0_mask := src.mask 352 s0_uop := src.uop 353 s0_try_l2l := false.B 354 s0_has_rob_entry := src.hasROBEntry 355 s0_rep_carry := src.rep_info.rep_carry 356 s0_mshrid := src.rep_info.mshr_id 357 s0_rsIdx := src.rsIdx 358 s0_isFirstIssue := false.B 359 s0_fast_rep := true.B 360 s0_ld_rep := src.isLoadReplay 361 s0_l2l_fwd := false.B 362 s0_prf := LSUOpType.isPrefetch(src.uop.ctrl.fuOpType) 363 s0_prf_rd := src.uop.ctrl.fuOpType === LSUOpType.prefetch_r 364 s0_prf_wr := src.uop.ctrl.fuOpType === LSUOpType.prefetch_w 365 s0_sched_idx := src.schedIndex 366 } 367 368 def fromNormalReplaySource(src: LsPipelineBundle) = { 369 s0_vaddr := src.vaddr 370 s0_mask := genVWmask(src.vaddr, src.uop.ctrl.fuOpType(1, 0)) 371 s0_uop := src.uop 372 s0_try_l2l := false.B 373 s0_has_rob_entry := true.B 374 s0_rsIdx := src.rsIdx 375 s0_rep_carry := src.replayCarry 376 s0_mshrid := src.mshrid 377 s0_isFirstIssue := false.B 378 s0_fast_rep := false.B 379 s0_ld_rep := true.B 380 s0_l2l_fwd := false.B 381 s0_prf := LSUOpType.isPrefetch(src.uop.ctrl.fuOpType) 382 s0_prf_rd := src.uop.ctrl.fuOpType === LSUOpType.prefetch_r 383 s0_prf_wr := src.uop.ctrl.fuOpType === LSUOpType.prefetch_w 384 s0_sched_idx := src.schedIndex 385 } 386 387 def fromPrefetchSource(src: L1PrefetchReq) = { 388 s0_vaddr := src.getVaddr() 389 s0_mask := 0.U 390 s0_uop := DontCare 391 s0_try_l2l := false.B 392 s0_has_rob_entry := false.B 393 s0_rsIdx := 0.U 394 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 395 s0_mshrid := 0.U 396 s0_isFirstIssue := false.B 397 s0_fast_rep := false.B 398 s0_ld_rep := false.B 399 s0_l2l_fwd := false.B 400 s0_prf := true.B 401 s0_prf_rd := !src.is_store 402 s0_prf_wr := src.is_store 403 s0_sched_idx := 0.U 404 } 405 406 def fromIntIssueSource(src: ExuInput) = { 407 s0_vaddr := src.src(0) + SignExt(src.uop.ctrl.imm(11, 0), VAddrBits) 408 s0_mask := genVWmask(s0_vaddr, src.uop.ctrl.fuOpType(1,0)) 409 s0_uop := src.uop 410 s0_try_l2l := false.B 411 s0_has_rob_entry := true.B 412 s0_rsIdx := io.rsIdx 413 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 414 s0_mshrid := 0.U 415 s0_isFirstIssue := true.B 416 s0_fast_rep := false.B 417 s0_ld_rep := false.B 418 s0_l2l_fwd := false.B 419 s0_prf := LSUOpType.isPrefetch(src.uop.ctrl.fuOpType) 420 s0_prf_rd := src.uop.ctrl.fuOpType === LSUOpType.prefetch_r 421 s0_prf_wr := src.uop.ctrl.fuOpType === LSUOpType.prefetch_w 422 s0_sched_idx := 0.U 423 } 424 425 def fromVecIssueSource() = { 426 s0_vaddr := 0.U 427 s0_mask := 0.U 428 s0_uop := 0.U.asTypeOf(new MicroOp) 429 s0_try_l2l := false.B 430 s0_has_rob_entry := false.B 431 s0_rsIdx := 0.U 432 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 433 s0_mshrid := 0.U 434 s0_isFirstIssue := false.B 435 s0_fast_rep := false.B 436 s0_ld_rep := false.B 437 s0_l2l_fwd := false.B 438 s0_prf := false.B 439 s0_prf_rd := false.B 440 s0_prf_wr := false.B 441 s0_sched_idx := 0.U 442 } 443 444 def fromLoadToLoadSource(src: LoadToLoadIO) = { 445 s0_vaddr := Cat(src.data(XLEN-1, 6), s0_ptr_chasing_vaddr(5,0)) 446 s0_mask := genVWmask(Cat(s0_ptr_chasing_vaddr(3), 0.U(3.W)), LSUOpType.ld) 447 // When there's no valid instruction from RS and LSQ, we try the load-to-load forwarding. 448 // Assume the pointer chasing is always ld. 449 s0_uop.ctrl.fuOpType := LSUOpType.ld 450 s0_try_l2l := true.B 451 // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx in S0 when trying pointchasing 452 // because these signals will be updated in S1 453 s0_has_rob_entry := false.B 454 s0_rsIdx := 0.U 455 s0_mshrid := 0.U 456 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 457 s0_isFirstIssue := true.B 458 s0_fast_rep := false.B 459 s0_ld_rep := false.B 460 s0_l2l_fwd := true.B 461 s0_prf := false.B 462 s0_prf_rd := false.B 463 s0_prf_wr := false.B 464 s0_sched_idx := 0.U 465 } 466 467 // set default 468 s0_uop := DontCare 469 when (s0_super_ld_rep_select) { fromNormalReplaySource(io.replay.bits) } 470 .elsewhen (s0_ld_fast_rep_select) { fromFastReplaySource(io.fast_rep_in.bits) } 471 .elsewhen (s0_ld_rep_select) { fromNormalReplaySource(io.replay.bits) } 472 .elsewhen (s0_hw_prf_select) { fromPrefetchSource(io.prefetch_req.bits) } 473 .elsewhen (s0_int_iss_select) { fromIntIssueSource(io.ldin.bits) } 474 .elsewhen (s0_vec_iss_select) { fromVecIssueSource() } 475 .otherwise { 476 if (EnableLoadToLoadForward) { 477 fromLoadToLoadSource(io.l2l_fwd_in) 478 } else { 479 fromNullSource() 480 } 481 } 482 483 // address align check 484 val s0_addr_aligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 485 "b00".U -> true.B, //b 486 "b01".U -> (s0_vaddr(0) === 0.U), //h 487 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 488 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 489 )) 490 491 // accept load flow if dcache ready (tlb is always ready) 492 // TODO: prefetch need writeback to loadQueueFlag 493 s0_out := DontCare 494 s0_out.rsIdx := s0_rsIdx 495 s0_out.vaddr := s0_vaddr 496 s0_out.mask := s0_mask 497 s0_out.uop := s0_uop 498 s0_out.isFirstIssue := s0_isFirstIssue 499 s0_out.hasROBEntry := s0_has_rob_entry 500 s0_out.isPrefetch := s0_prf 501 s0_out.isHWPrefetch := s0_hw_prf 502 s0_out.isFastReplay := s0_fast_rep 503 s0_out.isLoadReplay := s0_ld_rep 504 s0_out.isFastPath := s0_l2l_fwd 505 s0_out.mshrid := s0_mshrid 506 s0_out.uop.cf.exceptionVec(loadAddrMisaligned) := !s0_addr_aligned 507 s0_out.forward_tlDchannel := s0_super_ld_rep_select 508 when(io.tlb.req.valid && s0_isFirstIssue) { 509 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 510 }.otherwise{ 511 s0_out.uop.debugInfo.tlbFirstReqTime := s0_uop.debugInfo.tlbFirstReqTime 512 } 513 s0_out.schedIndex := s0_sched_idx 514 515 // load fast replay 516 io.fast_rep_in.ready := (s0_can_go && io.dcache.req.ready && s0_ld_fast_rep_ready) 517 518 // load flow source ready 519 // cache missed load has highest priority 520 // always accept cache missed load flow from load replay queue 521 io.replay.ready := (s0_can_go && io.dcache.req.ready && (s0_ld_rep_ready && !s0_rep_stall || s0_super_ld_rep_select)) 522 523 // accept load flow from rs when: 524 // 1) there is no lsq-replayed load 525 // 2) there is no fast replayed load 526 // 3) there is no high confidence prefetch request 527 io.ldin.ready := (s0_can_go && io.dcache.req.ready && s0_int_iss_ready) 528 529 // for hw prefetch load flow feedback, to be added later 530 // io.prefetch_in.ready := s0_hw_prf_select 531 532 // dcache replacement extra info 533 // TODO: should prefetch load update replacement? 534 io.dcache.replacementUpdated := Mux(s0_ld_rep_select || s0_super_ld_rep_select, io.replay.bits.replacementUpdated, false.B) 535 536 XSDebug(io.dcache.req.fire, 537 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 538 ) 539 XSDebug(s0_valid, 540 p"S0: pc ${Hexadecimal(s0_out.uop.cf.pc)}, lId ${Hexadecimal(s0_out.uop.lqIdx.asUInt)}, " + 541 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 542 543 // Pipeline 544 // -------------------------------------------------------------------------------- 545 // stage 1 546 // -------------------------------------------------------------------------------- 547 // TLB resp (send paddr to dcache) 548 val s1_valid = RegInit(false.B) 549 val s1_in = Wire(new LqWriteBundle) 550 val s1_out = Wire(new LqWriteBundle) 551 val s1_kill = Wire(Bool()) 552 val s1_can_go = s2_ready 553 val s1_fire = s1_valid && !s1_kill && s1_can_go 554 555 s1_ready := !s1_valid || s1_kill || s2_ready 556 when (s0_fire) { s1_valid := true.B } 557 .elsewhen (s1_fire) { s1_valid := false.B } 558 .elsewhen (s1_kill) { s1_valid := false.B } 559 s1_in := RegEnable(s0_out, s0_fire) 560 561 val s1_fast_rep_dly_err = RegNext(io.fast_rep_in.bits.delayedLoadError) 562 val s1_fast_rep_kill = s1_fast_rep_dly_err && s1_in.isFastReplay 563 val s1_l2l_fwd_dly_err = RegNext(io.l2l_fwd_in.dly_ld_err) 564 val s1_l2l_fwd_kill = s1_l2l_fwd_dly_err && s1_in.isFastPath 565 val s1_late_kill = s1_fast_rep_kill || s1_l2l_fwd_kill 566 val s1_vaddr_hi = Wire(UInt()) 567 val s1_vaddr_lo = Wire(UInt()) 568 val s1_vaddr = Wire(UInt()) 569 val s1_paddr_dup_lsu = Wire(UInt()) 570 val s1_paddr_dup_dcache = Wire(UInt()) 571 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.cf.exceptionVec, lduCfg).asUInt.orR // af & pf exception were modified below. 572 val s1_tlb_miss = io.tlb.resp.bits.miss 573 val s1_prf = s1_in.isPrefetch 574 val s1_hw_prf = s1_in.isHWPrefetch 575 val s1_sw_prf = s1_prf && !s1_hw_prf 576 val s1_tlb_memidx = io.tlb.resp.bits.memidx 577 578 s1_vaddr_hi := s1_in.vaddr(VAddrBits - 1, 6) 579 s1_vaddr_lo := s1_in.vaddr(5, 0) 580 s1_vaddr := Cat(s1_vaddr_hi, s1_vaddr_lo) 581 s1_paddr_dup_lsu := io.tlb.resp.bits.paddr(0) 582 s1_paddr_dup_dcache := io.tlb.resp.bits.paddr(1) 583 584 when (s1_tlb_memidx.is_ld && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_in.uop.lqIdx.value) { 585 // printf("load idx = %d\n", s1_tlb_memidx.idx) 586 s1_out.uop.debugInfo.tlbRespTime := GTimer() 587 } 588 589 io.tlb.req_kill := s1_kill 590 io.tlb.resp.ready := true.B 591 592 io.dcache.s1_paddr_dup_lsu <> s1_paddr_dup_lsu 593 io.dcache.s1_paddr_dup_dcache <> s1_paddr_dup_dcache 594 io.dcache.s1_kill := s1_kill || s1_tlb_miss || s1_exception 595 596 // store to load forwarding 597 io.sbuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_prf) 598 io.sbuffer.vaddr := s1_vaddr 599 io.sbuffer.paddr := s1_paddr_dup_lsu 600 io.sbuffer.uop := s1_in.uop 601 io.sbuffer.sqIdx := s1_in.uop.sqIdx 602 io.sbuffer.mask := s1_in.mask 603 io.sbuffer.pc := s1_in.uop.cf.pc // FIXME: remove it 604 605 io.lsq.forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_prf) 606 io.lsq.forward.vaddr := s1_vaddr 607 io.lsq.forward.paddr := s1_paddr_dup_lsu 608 io.lsq.forward.uop := s1_in.uop 609 io.lsq.forward.sqIdx := s1_in.uop.sqIdx 610 io.lsq.forward.sqIdxMask := 0.U 611 io.lsq.forward.mask := s1_in.mask 612 io.lsq.forward.pc := s1_in.uop.cf.pc // FIXME: remove it 613 614 // st-ld violation query 615 val s1_nuke = VecInit((0 until StorePipelineWidth).map(w => { 616 io.stld_nuke_query(w).valid && // query valid 617 isAfter(s1_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 618 // TODO: Fix me when vector instruction 619 (s1_paddr_dup_lsu(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 620 (s1_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 621 })).asUInt.orR && !s1_tlb_miss 622 623 s1_out := s1_in 624 s1_out.vaddr := s1_vaddr 625 s1_out.paddr := s1_paddr_dup_lsu 626 s1_out.tlbMiss := s1_tlb_miss 627 s1_out.ptwBack := io.tlb.resp.bits.ptwBack 628 s1_out.rsIdx := s1_in.rsIdx 629 s1_out.rep_info.debug := s1_in.uop.debugInfo 630 s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf 631 s1_out.lateKill := s1_late_kill 632 633 when (!s1_late_kill) { 634 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 635 // af & pf exception were modified 636 s1_out.uop.cf.exceptionVec(loadPageFault) := io.tlb.resp.bits.excp(0).pf.ld 637 s1_out.uop.cf.exceptionVec(loadAccessFault) := io.tlb.resp.bits.excp(0).af.ld 638 } .otherwise { 639 s1_out.uop.cf.exceptionVec(loadAddrMisaligned) := false.B 640 s1_out.uop.cf.exceptionVec(loadAccessFault) := s1_late_kill 641 } 642 643 // pointer chasing 644 val s1_try_ptr_chasing = RegNext(s0_do_try_ptr_chasing, false.B) 645 val s1_ptr_chasing_vaddr = RegEnable(s0_ptr_chasing_vaddr, s0_do_try_ptr_chasing) 646 val s1_fu_op_type_not_ld = WireInit(false.B) 647 val s1_not_fast_match = WireInit(false.B) 648 val s1_addr_mismatch = WireInit(false.B) 649 val s1_addr_misaligned = WireInit(false.B) 650 val s1_ptr_chasing_canceled = WireInit(false.B) 651 val s1_cancel_ptr_chasing = WireInit(false.B) 652 653 s1_kill := s1_late_kill || 654 s1_cancel_ptr_chasing || 655 s1_in.uop.robIdx.needFlush(io.redirect) || 656 RegEnable(s0_kill, false.B, io.ldin.valid || io.replay.valid || io.l2l_fwd_in.valid || io.fast_rep_in.valid) 657 658 if (EnableLoadToLoadForward) { 659 // Sometimes, we need to cancel the load-load forwarding. 660 // These can be put at S0 if timing is bad at S1. 661 // Case 0: CACHE_SET(base + offset) != CACHE_SET(base) (lowest 6-bit addition has an overflow) 662 s1_addr_mismatch := s1_ptr_chasing_vaddr(6) || RegEnable(io.ld_fast_imm(11, 6).orR, s0_do_try_ptr_chasing) 663 // Case 1: the address is not 64-bit aligned or the fuOpType is not LD 664 s1_addr_misaligned := s1_ptr_chasing_vaddr(2, 0).orR 665 s1_fu_op_type_not_ld := io.ldin.bits.uop.ctrl.fuOpType =/= LSUOpType.ld 666 // Case 2: this is not a valid load-load pair 667 s1_not_fast_match := RegEnable(!io.ld_fast_match, s0_try_ptr_chasing) 668 // Case 3: this load-load uop is cancelled 669 s1_ptr_chasing_canceled := !io.ldin.valid 670 671 when (s1_try_ptr_chasing) { 672 s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_fu_op_type_not_ld || s1_not_fast_match || s1_ptr_chasing_canceled 673 674 s1_in.uop := io.ldin.bits.uop 675 s1_in.rsIdx := io.rsIdx 676 s1_in.isFirstIssue := io.isFirstIssue 677 s1_vaddr_lo := Cat(s1_ptr_chasing_vaddr(5, 3), 0.U(3.W)) 678 s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 679 s1_paddr_dup_dcache := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 680 681 // recored tlb time when get the data to ensure the correctness of the latency calculation (although it should not record in here, because it does not use tlb) 682 s1_in.uop.debugInfo.tlbFirstReqTime := GTimer() 683 s1_in.uop.debugInfo.tlbRespTime := GTimer() 684 } 685 when (!s1_cancel_ptr_chasing) { 686 s0_ptr_chasing_canceled := s1_try_ptr_chasing && !io.replay.fire && !io.fast_rep_in.fire 687 when (s1_try_ptr_chasing) { 688 io.ldin.ready := true.B 689 } 690 } 691 } 692 693 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 694 val s1_sqIdx_mask = RegNext(UIntToMask(s0_out.uop.sqIdx.value, StoreQueueSize)) 695 // to enable load-load, sqIdxMask must be calculated based on ldin.uop 696 // If the timing here is not OK, load-load forwarding has to be disabled. 697 // Or we calculate sqIdxMask at RS?? 698 io.lsq.forward.sqIdxMask := s1_sqIdx_mask 699 if (EnableLoadToLoadForward) { 700 when (s1_try_ptr_chasing) { 701 io.lsq.forward.sqIdxMask := UIntToMask(io.ldin.bits.uop.sqIdx.value, StoreQueueSize) 702 } 703 } 704 705 io.forward_mshr.valid := s1_valid && s1_out.forward_tlDchannel 706 io.forward_mshr.mshrid := s1_out.mshrid 707 io.forward_mshr.paddr := s1_out.paddr 708 709 XSDebug(s1_valid, 710 p"S1: pc ${Hexadecimal(s1_out.uop.cf.pc)}, lId ${Hexadecimal(s1_out.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 711 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 712 713 // Pipeline 714 // -------------------------------------------------------------------------------- 715 // stage 2 716 // -------------------------------------------------------------------------------- 717 // s2: DCache resp 718 val s2_valid = RegInit(false.B) 719 val s2_in = Wire(new LqWriteBundle) 720 val s2_out = Wire(new LqWriteBundle) 721 val s2_kill = Wire(Bool()) 722 val s2_can_go = s3_ready 723 val s2_fire = s2_valid && !s2_kill && s2_can_go 724 725 s2_kill := s2_in.uop.robIdx.needFlush(io.redirect) 726 s2_ready := !s2_valid || s2_kill || s3_ready 727 when (s1_fire) { s2_valid := true.B } 728 .elsewhen (s2_fire) { s2_valid := false.B } 729 .elsewhen (s2_kill) { s2_valid := false.B } 730 s2_in := RegEnable(s1_out, s1_fire) 731 732 val s2_pmp = WireInit(io.pmp) 733 val s2_static_pm = RegNext(io.tlb.resp.bits.static_pm) 734 when (s2_static_pm.valid) { 735 s2_pmp.ld := false.B 736 s2_pmp.st := false.B 737 s2_pmp.instr := false.B 738 s2_pmp.mmio := s2_static_pm.bits 739 } 740 val s2_prf = s2_in.isPrefetch 741 val s2_hw_prf = s2_in.isHWPrefetch 742 743 // exception that may cause load addr to be invalid / illegal 744 // if such exception happen, that inst and its exception info 745 // will be force writebacked to rob 746 val s2_exception_vec = WireInit(s2_in.uop.cf.exceptionVec) 747 when (!s2_in.lateKill) { 748 s2_exception_vec(loadAccessFault) := s2_in.uop.cf.exceptionVec(loadAccessFault) || s2_pmp.ld 749 // soft prefetch will not trigger any exception (but ecc error interrupt may be triggered) 750 when (s2_prf || s2_in.tlbMiss) { 751 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 752 } 753 } 754 val s2_exception = ExceptionNO.selectByFu(s2_exception_vec, lduCfg).asUInt.orR 755 756 val (s2_fwd_frm_d_chan, s2_fwd_data_frm_d_chan) = io.tl_d_channel.forward(s1_valid && s1_out.forward_tlDchannel, s1_out.mshrid, s1_out.paddr) 757 val (s2_fwd_data_valid, s2_fwd_frm_mshr, s2_fwd_data_frm_mshr) = io.forward_mshr.forward() 758 val s2_fwd_frm_d_chan_or_mshr = s2_fwd_data_valid && (s2_fwd_frm_d_chan || s2_fwd_frm_mshr) 759 760 // writeback access fault caused by ecc error / bus error 761 // * ecc data error is slow to generate, so we will not use it until load stage 3 762 // * in load stage 3, an extra signal io.load_error will be used to 763 val s2_actually_mmio = s2_pmp.mmio 764 val s2_mmio = !s2_prf && 765 s2_actually_mmio && 766 !s2_exception && 767 !s2_in.tlbMiss 768 769 val s2_full_fwd = Wire(Bool()) 770 val s2_mem_amb = s2_in.uop.cf.storeSetHit && 771 io.lsq.forward.addrInvalid 772 773 val s2_tlb_miss = s2_in.tlbMiss 774 val s2_fwd_fail = io.lsq.forward.dataInvalid 775 val s2_dcache_miss = io.dcache.resp.bits.miss && 776 !s2_fwd_frm_d_chan_or_mshr && 777 !s2_full_fwd 778 779 val s2_mq_nack = io.dcache.s2_mq_nack && 780 !s2_fwd_frm_d_chan_or_mshr && 781 !s2_full_fwd 782 783 val s2_bank_conflict = io.dcache.s2_bank_conflict && 784 !s2_fwd_frm_d_chan_or_mshr && 785 !s2_full_fwd 786 787 val s2_wpu_pred_fail = io.dcache.s2_wpu_pred_fail && 788 !s2_fwd_frm_d_chan_or_mshr && 789 !s2_full_fwd 790 791 val s2_rar_nack = io.lsq.ldld_nuke_query.req.valid && 792 !io.lsq.ldld_nuke_query.req.ready 793 794 val s2_raw_nack = io.lsq.stld_nuke_query.req.valid && 795 !io.lsq.stld_nuke_query.req.ready 796 // st-ld violation query 797 // NeedFastRecovery Valid when 798 // 1. Fast recovery query request Valid. 799 // 2. Load instruction is younger than requestors(store instructions). 800 // 3. Physical address match. 801 // 4. Data contains. 802 val s2_nuke = VecInit((0 until StorePipelineWidth).map(w => { 803 io.stld_nuke_query(w).valid && // query valid 804 isAfter(s2_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 805 // TODO: Fix me when vector instruction 806 (s2_in.paddr(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 807 (s2_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 808 })).asUInt.orR && !s2_tlb_miss || s2_in.rep_info.nuke 809 810 val s2_cache_handled = io.dcache.resp.bits.handled 811 val s2_cache_tag_error = RegNext(io.csrCtrl.cache_error_enable) && 812 io.dcache.resp.bits.tag_error 813 814 val s2_troublem = !s2_exception && 815 !s2_mmio && 816 !s2_prf && 817 !s2_in.lateKill 818 819 io.dcache.resp.ready := true.B 820 val s2_dcache_should_resp = !(s2_in.tlbMiss || s2_exception || s2_mmio || s2_prf || s2_in.lateKill) 821 assert(!(s2_valid && (s2_dcache_should_resp && !io.dcache.resp.valid)), "DCache response got lost") 822 823 // fast replay require 824 val s2_dcache_fast_rep = (s2_mq_nack || !s2_dcache_miss && (s2_bank_conflict || s2_wpu_pred_fail)) 825 val s2_nuke_fast_rep = !s2_mq_nack && 826 !s2_dcache_miss && 827 !s2_bank_conflict && 828 !s2_wpu_pred_fail && 829 !s2_rar_nack && 830 !s2_raw_nack && 831 s2_nuke 832 833 val s2_hint_fast_rep = !s2_mq_nack && 834 s2_dcache_miss && 835 s2_cache_handled && 836 io.l2_hint.valid && 837 io.l2_hint.bits.sourceId === io.dcache.resp.bits.mshr_id 838 839 840 val s2_fast_rep = !s2_mem_amb && 841 !s2_tlb_miss && 842 !s2_fwd_fail && 843 (s2_dcache_fast_rep || s2_hint_fast_rep || s2_nuke_fast_rep) && 844 s2_troublem 845 846 // need allocate new entry 847 val s2_can_query = !s2_mem_amb && 848 !s2_tlb_miss && 849 !s2_fwd_fail && 850 !s2_dcache_fast_rep && 851 s2_troublem 852 853 val s2_data_fwded = s2_dcache_miss && (s2_full_fwd || s2_cache_tag_error) 854 855 // ld-ld violation require 856 io.lsq.ldld_nuke_query.req.valid := s2_valid && s2_can_query 857 io.lsq.ldld_nuke_query.req.bits.uop := s2_in.uop 858 io.lsq.ldld_nuke_query.req.bits.mask := s2_in.mask 859 io.lsq.ldld_nuke_query.req.bits.paddr := s2_in.paddr 860 io.lsq.ldld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 861 862 // st-ld violation require 863 io.lsq.stld_nuke_query.req.valid := s2_valid && s2_can_query 864 io.lsq.stld_nuke_query.req.bits.uop := s2_in.uop 865 io.lsq.stld_nuke_query.req.bits.mask := s2_in.mask 866 io.lsq.stld_nuke_query.req.bits.paddr := s2_in.paddr 867 io.lsq.stld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 868 869 // merge forward result 870 // lsq has higher priority than sbuffer 871 val s2_fwd_mask = Wire(Vec((VLEN/8), Bool())) 872 val s2_fwd_data = Wire(Vec((VLEN/8), UInt(8.W))) 873 s2_full_fwd := ((~s2_fwd_mask.asUInt).asUInt & s2_in.mask) === 0.U && !io.lsq.forward.dataInvalid 874 // generate XLEN/8 Muxs 875 for (i <- 0 until VLEN / 8) { 876 s2_fwd_mask(i) := io.lsq.forward.forwardMask(i) || io.sbuffer.forwardMask(i) 877 s2_fwd_data(i) := Mux(io.lsq.forward.forwardMask(i), io.lsq.forward.forwardData(i), io.sbuffer.forwardData(i)) 878 } 879 880 XSDebug(s2_fire, "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 881 s2_in.uop.cf.pc, 882 io.lsq.forward.forwardData.asUInt, io.lsq.forward.forwardMask.asUInt, 883 s2_in.forwardData.asUInt, s2_in.forwardMask.asUInt 884 ) 885 886 // 887 s2_out := s2_in 888 s2_out.data := 0.U // data will be generated in load s3 889 s2_out.uop.ctrl.fpWen := s2_in.uop.ctrl.fpWen && !s2_exception 890 s2_out.mmio := s2_mmio 891 s2_out.uop.ctrl.flushPipe := false.B 892 s2_out.uop.cf.exceptionVec := s2_exception_vec 893 s2_out.forwardMask := s2_fwd_mask 894 s2_out.forwardData := s2_fwd_data 895 s2_out.handledByMSHR := s2_cache_handled 896 s2_out.miss := s2_dcache_miss && s2_troublem 897 s2_out.feedbacked := io.feedback_fast.valid 898 899 // Generate replay signal caused by: 900 // * st-ld violation check 901 // * tlb miss 902 // * dcache replay 903 // * forward data invalid 904 // * dcache miss 905 s2_out.rep_info.mem_amb := s2_mem_amb && s2_troublem 906 s2_out.rep_info.tlb_miss := s2_tlb_miss && s2_troublem 907 s2_out.rep_info.fwd_fail := s2_fwd_fail && s2_troublem 908 s2_out.rep_info.dcache_rep := s2_mq_nack && s2_troublem 909 s2_out.rep_info.dcache_miss := s2_dcache_miss && s2_troublem 910 s2_out.rep_info.bank_conflict := s2_bank_conflict && s2_troublem 911 s2_out.rep_info.wpu_fail := s2_wpu_pred_fail && s2_troublem 912 s2_out.rep_info.rar_nack := s2_rar_nack && s2_troublem 913 s2_out.rep_info.raw_nack := s2_raw_nack && s2_troublem 914 s2_out.rep_info.nuke := s2_nuke && s2_troublem 915 s2_out.rep_info.full_fwd := s2_data_fwded 916 s2_out.rep_info.data_inv_sq_idx := io.lsq.forward.dataInvalidSqIdx 917 s2_out.rep_info.addr_inv_sq_idx := io.lsq.forward.addrInvalidSqIdx 918 s2_out.rep_info.rep_carry := io.dcache.resp.bits.replayCarry 919 s2_out.rep_info.mshr_id := io.dcache.resp.bits.mshr_id 920 s2_out.rep_info.last_beat := s2_in.paddr(log2Up(refillBytes)) 921 s2_out.rep_info.debug := s2_in.uop.debugInfo 922 923 // if forward fail, replay this inst from fetch 924 val debug_fwd_fail_rep = s2_fwd_fail && !s2_troublem && !s2_in.tlbMiss 925 // if ld-ld violation is detected, replay from this inst from fetch 926 val debug_ldld_nuke_rep = false.B // s2_ldld_violation && !s2_mmio && !s2_is_prefetch && !s2_in.tlbMiss 927 // io.out.bits.uop.ctrl.replayInst := false.B 928 929 // to be removed 930 io.feedback_fast.valid := s2_valid && // inst is valid 931 !s2_in.isLoadReplay && // already feedbacked 932 io.lq_rep_full && // LoadQueueReplay is full 933 s2_out.rep_info.need_rep && // need replay 934 !s2_exception && // no exception is triggered 935 !s2_hw_prf // not hardware prefetch 936 io.feedback_fast.bits.hit := false.B 937 io.feedback_fast.bits.flushState := s2_in.ptwBack 938 io.feedback_fast.bits.rsIdx := s2_in.rsIdx 939 io.feedback_fast.bits.sourceType := RSFeedbackType.lrqFull 940 io.feedback_fast.bits.dataInvalidSqIdx := DontCare 941 942 // fast wakeup 943 io.fast_uop.valid := RegNext( 944 !io.dcache.s1_disable_fast_wakeup && 945 s1_valid && 946 !s1_kill && 947 !io.tlb.resp.bits.fast_miss && 948 !io.lsq.forward.dataInvalidFast 949 ) && (s2_valid && !s2_out.rep_info.need_rep && !s2_mmio) 950 io.fast_uop.bits := RegNext(s1_out.uop) 951 952 // 953 io.s2_ptr_chasing := RegEnable(s1_try_ptr_chasing && !s1_cancel_ptr_chasing, s1_fire) 954 io.prefetch_train.valid := s2_valid && !s2_in.mmio && !s2_in.tlbMiss 955 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 956 io.prefetch_train.bits.miss := io.dcache.resp.bits.miss 957 io.prefetch_train.bits.meta_prefetch := io.dcache.resp.bits.meta_prefetch 958 io.prefetch_train.bits.meta_access := io.dcache.resp.bits.meta_access 959 if (env.FPGAPlatform){ 960 io.dcache.s0_pc := DontCare 961 io.dcache.s1_pc := DontCare 962 io.dcache.s2_pc := DontCare 963 }else{ 964 io.dcache.s0_pc := s0_out.uop.cf.pc 965 io.dcache.s1_pc := s1_out.uop.cf.pc 966 io.dcache.s2_pc := s2_out.uop.cf.pc 967 } 968 io.dcache.s2_kill := s2_pmp.ld || s2_pmp.mmio || s2_kill 969 970 val s1_ld_left_fire = s1_valid && !s1_kill && s2_ready 971 val s2_ld_valid_dup = RegInit(0.U(6.W)) 972 s2_ld_valid_dup := 0x0.U(6.W) 973 when (s1_ld_left_fire && !s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x3f.U(6.W) } 974 when (s1_kill || s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x0.U(6.W) } 975 assert(RegNext((s2_valid === s2_ld_valid_dup(0)) || RegNext(s1_out.isHWPrefetch))) 976 977 // Pipeline 978 // -------------------------------------------------------------------------------- 979 // stage 3 980 // -------------------------------------------------------------------------------- 981 // writeback and update load queue 982 val s3_valid = RegNext(s2_valid && !s2_out.isHWPrefetch && !s2_out.uop.robIdx.needFlush(io.redirect)) 983 val s3_in = RegEnable(s2_out, s2_fire) 984 val s3_out = Wire(Valid(new ExuOutput)) 985 val s3_dcache_rep = RegEnable(s2_dcache_fast_rep && s2_troublem, s2_fire) 986 val s3_ld_valid_dup = RegEnable(s2_ld_valid_dup, s2_fire) 987 val s3_fast_rep = Wire(Bool()) 988 val s3_troublem = RegNext(s2_troublem) 989 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 990 s3_ready := !s3_valid || s3_kill || io.ldout.ready 991 992 // forwrad last beat 993 val (s3_fwd_frm_d_chan, s3_fwd_data_frm_d_chan) = io.tl_d_channel.forward(s2_valid && s2_out.forward_tlDchannel, s2_out.mshrid, s2_out.paddr) 994 val s3_fwd_data_valid = RegEnable(s2_fwd_data_valid, s2_valid) 995 val s3_fwd_frm_d_chan_valid = (s3_fwd_frm_d_chan && s3_fwd_data_valid) 996 val s3_nuke = VecInit((0 until StorePipelineWidth).map(w => { 997 io.stld_nuke_query(w).valid && // query valid 998 isAfter(s3_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 999 // TODO: Fix me when vector instruction 1000 (s3_in.paddr(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 1001 (s3_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 1002 })).asUInt.orR && !s3_in.tlbMiss || s3_in.rep_info.nuke 1003 1004 1005 // s3 load fast replay 1006 io.fast_rep_out.valid := s3_valid && s3_fast_rep && !s3_in.uop.robIdx.needFlush(io.redirect) 1007 io.fast_rep_out.bits := s3_in 1008 1009 io.lsq.ldin.valid := s3_valid && (!s3_fast_rep || !io.fast_rep_out.ready) && !s3_in.feedbacked && !s3_in.lateKill 1010 io.lsq.ldin.bits := s3_in 1011 io.lsq.ldin.bits.miss := s3_in.miss && !s3_fwd_frm_d_chan_valid 1012 1013 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1014 io.lsq.ldin.bits.data_wen_dup := s3_ld_valid_dup.asBools 1015 io.lsq.ldin.bits.replacementUpdated := io.dcache.resp.bits.replacementUpdated 1016 1017 val s3_dly_ld_err = 1018 if (EnableAccurateLoadError) { 1019 (s3_in.lateKill || io.dcache.resp.bits.error_delayed) && RegNext(io.csrCtrl.cache_error_enable) 1020 } else { 1021 WireInit(false.B) 1022 } 1023 io.s3_dly_ld_err := false.B // s3_dly_ld_err && s3_valid 1024 io.fast_rep_out.bits.delayedLoadError := s3_dly_ld_err 1025 io.lsq.ldin.bits.dcacheRequireReplay := s3_dcache_rep 1026 1027 val s3_vp_match_fail = RegNext(io.lsq.forward.matchInvalid || io.sbuffer.matchInvalid) && s3_troublem 1028 val s3_ldld_rep_inst = 1029 io.lsq.ldld_nuke_query.resp.valid && 1030 io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch && 1031 RegNext(io.csrCtrl.ldld_vio_check_enable) 1032 1033 val s3_rep_info = WireInit(s3_in.rep_info) 1034 s3_rep_info.wpu_fail := s3_in.rep_info.wpu_fail && !s3_fwd_frm_d_chan_valid && s3_troublem 1035 s3_rep_info.bank_conflict := s3_in.rep_info.bank_conflict && !s3_fwd_frm_d_chan_valid && s3_troublem 1036 s3_rep_info.dcache_miss := s3_in.rep_info.dcache_miss && !s3_fwd_frm_d_chan_valid && s3_troublem 1037 s3_rep_info.nuke := s3_nuke && s3_troublem 1038 val s3_rep_frm_fetch = s3_vp_match_fail || s3_ldld_rep_inst 1039 val s3_sel_rep_cause = PriorityEncoderOH(s3_rep_info.cause.asUInt) 1040 val s3_force_rep = s3_sel_rep_cause(LoadReplayCauses.C_TM) && 1041 !s3_in.uop.cf.exceptionVec(loadAddrMisaligned) && 1042 s3_troublem 1043 1044 val s3_exception = ExceptionNO.selectByFu(s3_in.uop.cf.exceptionVec, lduCfg).asUInt.orR 1045 when ((s3_exception || s3_dly_ld_err || s3_rep_frm_fetch) && !s3_force_rep) { 1046 io.lsq.ldin.bits.rep_info.cause := 0.U.asTypeOf(s3_rep_info.cause.cloneType) 1047 } .otherwise { 1048 io.lsq.ldin.bits.rep_info.cause := VecInit(s3_sel_rep_cause.asBools) 1049 } 1050 1051 // Int load, if hit, will be writebacked at s3 1052 s3_out.valid := s3_valid && !io.lsq.ldin.bits.rep_info.need_rep && !s3_in.mmio 1053 s3_out.bits.uop := s3_in.uop 1054 s3_out.bits.uop.cf.exceptionVec(loadAccessFault) := s3_dly_ld_err || s3_in.uop.cf.exceptionVec(loadAccessFault) 1055 s3_out.bits.uop.ctrl.replayInst := s3_rep_frm_fetch 1056 s3_out.bits.data := s3_in.data 1057 s3_out.bits.redirectValid := false.B 1058 s3_out.bits.redirect := DontCare 1059 s3_out.bits.debug.isMMIO := s3_in.mmio 1060 s3_out.bits.debug.isPerfCnt := false.B 1061 s3_out.bits.debug.paddr := s3_in.paddr 1062 s3_out.bits.debug.vaddr := s3_in.vaddr 1063 s3_out.bits.fflags := DontCare 1064 1065 when (s3_force_rep) { 1066 s3_out.bits.uop.cf.exceptionVec := 0.U.asTypeOf(s3_in.uop.cf.exceptionVec.cloneType) 1067 } 1068 1069 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1070 1071 io.lsq.ldin.bits.uop := s3_out.bits.uop 1072 1073 val s3_revoke = s3_exception || io.lsq.ldin.bits.rep_info.need_rep 1074 io.lsq.ldld_nuke_query.revoke := s3_revoke 1075 io.lsq.stld_nuke_query.revoke := s3_revoke 1076 1077 // feedback slow 1078 s3_fast_rep := RegNext(s2_fast_rep) && 1079 !s3_in.feedbacked && 1080 !s3_in.lateKill && 1081 !s3_rep_frm_fetch && 1082 !s3_exception 1083 1084 val s3_fb_no_waiting = !s3_in.isLoadReplay && !(s3_fast_rep && io.fast_rep_out.ready) && !s3_in.feedbacked 1085 1086 // 1087 io.feedback_slow.valid := s3_valid && !s3_in.uop.robIdx.needFlush(io.redirect) && s3_fb_no_waiting 1088 io.feedback_slow.bits.hit := !io.lsq.ldin.bits.rep_info.need_rep || io.lsq.ldin.ready 1089 io.feedback_slow.bits.flushState := s3_in.ptwBack 1090 io.feedback_slow.bits.rsIdx := s3_in.rsIdx 1091 io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull 1092 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 1093 1094 val s3_ld_wb_meta = Mux(s3_out.valid, s3_out.bits, io.lsq.uncache.bits) 1095 1096 // data from load queue refill 1097 val s3_ld_raw_data_frm_uncache = io.lsq.ld_raw_data 1098 val s3_merged_data_frm_uncache = s3_ld_raw_data_frm_uncache.mergedData() 1099 val s3_picked_data_frm_uncache = LookupTree(s3_ld_raw_data_frm_uncache.addrOffset, List( 1100 "b000".U -> s3_merged_data_frm_uncache(63, 0), 1101 "b001".U -> s3_merged_data_frm_uncache(63, 8), 1102 "b010".U -> s3_merged_data_frm_uncache(63, 16), 1103 "b011".U -> s3_merged_data_frm_uncache(63, 24), 1104 "b100".U -> s3_merged_data_frm_uncache(63, 32), 1105 "b101".U -> s3_merged_data_frm_uncache(63, 40), 1106 "b110".U -> s3_merged_data_frm_uncache(63, 48), 1107 "b111".U -> s3_merged_data_frm_uncache(63, 56) 1108 )) 1109 val s3_ld_data_frm_uncache = rdataHelper(s3_ld_raw_data_frm_uncache.uop, s3_picked_data_frm_uncache) 1110 1111 // data from dcache hit 1112 val s3_ld_raw_data_frm_cache = Wire(new LoadDataFromDcacheBundle) 1113 s3_ld_raw_data_frm_cache.respDcacheData := io.dcache.resp.bits.data_delayed 1114 s3_ld_raw_data_frm_cache.forwardMask := RegEnable(s2_fwd_mask, s2_valid) 1115 s3_ld_raw_data_frm_cache.forwardData := RegEnable(s2_fwd_data, s2_valid) 1116 s3_ld_raw_data_frm_cache.uop := RegEnable(s2_out.uop, s2_valid) 1117 s3_ld_raw_data_frm_cache.addrOffset := RegEnable(s2_out.paddr(3, 0), s2_valid) 1118 s3_ld_raw_data_frm_cache.forward_D := RegEnable(s2_fwd_frm_d_chan, s2_valid) || s3_fwd_frm_d_chan_valid 1119 s3_ld_raw_data_frm_cache.forwardData_D := Mux(s3_fwd_frm_d_chan_valid, s3_fwd_data_frm_d_chan, RegEnable(s2_fwd_data_frm_d_chan, s2_valid)) 1120 s3_ld_raw_data_frm_cache.forward_mshr := RegEnable(s2_fwd_frm_mshr, s2_valid) 1121 s3_ld_raw_data_frm_cache.forwardData_mshr := RegEnable(s2_fwd_data_frm_mshr, s2_valid) 1122 s3_ld_raw_data_frm_cache.forward_result_valid := RegEnable(s2_fwd_data_valid, s2_valid) 1123 1124 val s3_merged_data_frm_cache = s3_ld_raw_data_frm_cache.mergedData() 1125 val s3_picked_data_frm_cache = LookupTree(s3_ld_raw_data_frm_cache.addrOffset, List( 1126 "b0000".U -> s3_merged_data_frm_cache(63, 0), 1127 "b0001".U -> s3_merged_data_frm_cache(63, 8), 1128 "b0010".U -> s3_merged_data_frm_cache(63, 16), 1129 "b0011".U -> s3_merged_data_frm_cache(63, 24), 1130 "b0100".U -> s3_merged_data_frm_cache(63, 32), 1131 "b0101".U -> s3_merged_data_frm_cache(63, 40), 1132 "b0110".U -> s3_merged_data_frm_cache(63, 48), 1133 "b0111".U -> s3_merged_data_frm_cache(63, 56), 1134 "b1000".U -> s3_merged_data_frm_cache(127, 64), 1135 "b1001".U -> s3_merged_data_frm_cache(127, 72), 1136 "b1010".U -> s3_merged_data_frm_cache(127, 80), 1137 "b1011".U -> s3_merged_data_frm_cache(127, 88), 1138 "b1100".U -> s3_merged_data_frm_cache(127, 96), 1139 "b1101".U -> s3_merged_data_frm_cache(127, 104), 1140 "b1110".U -> s3_merged_data_frm_cache(127, 112), 1141 "b1111".U -> s3_merged_data_frm_cache(127, 120) 1142 )) 1143 val s3_ld_data_frm_cache = rdataHelper(s3_ld_raw_data_frm_cache.uop, s3_picked_data_frm_cache) 1144 1145 // FIXME: add 1 cycle delay ? 1146 io.lsq.uncache.ready := !s3_out.valid 1147 io.ldout.bits := s3_ld_wb_meta 1148 io.ldout.bits.data := Mux(s3_out.valid, s3_ld_data_frm_cache, s3_ld_data_frm_uncache) 1149 io.ldout.valid := s3_out.valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) || 1150 io.lsq.uncache.valid && !io.lsq.uncache.bits.uop.robIdx.needFlush(io.redirect) && !s3_out.valid 1151 1152 1153 // fast load to load forward 1154 io.l2l_fwd_out.valid := s3_out.valid && !s3_in.lateKill 1155 io.l2l_fwd_out.data := Mux(s3_ld_raw_data_frm_cache.addrOffset(3), s3_merged_data_frm_cache(127, 64), s3_merged_data_frm_cache(63, 0)) // load to load is for ld only 1156 io.l2l_fwd_out.dly_ld_err := s3_dly_ld_err // ecc delayed error 1157 1158 // trigger 1159 val last_valid_data = RegNext(RegEnable(io.ldout.bits.data, io.ldout.fire)) 1160 val hit_ld_addr_trig_hit_vec = Wire(Vec(3, Bool())) 1161 val lq_ld_addr_trig_hit_vec = io.lsq.trigger.lqLoadAddrTriggerHitVec 1162 (0 until 3).map{i => { 1163 val tdata2 = RegNext(io.trigger(i).tdata2) 1164 val matchType = RegNext(io.trigger(i).matchType) 1165 val tEnable = RegNext(io.trigger(i).tEnable) 1166 1167 hit_ld_addr_trig_hit_vec(i) := TriggerCmp(RegNext(s2_out.vaddr), tdata2, matchType, tEnable) 1168 io.trigger(i).addrHit := Mux(s3_out.valid, hit_ld_addr_trig_hit_vec(i), lq_ld_addr_trig_hit_vec(i)) 1169 io.trigger(i).lastDataHit := TriggerCmp(last_valid_data, tdata2, matchType, tEnable) 1170 }} 1171 io.lsq.trigger.hitLoadAddrTriggerHitVec := hit_ld_addr_trig_hit_vec 1172 1173 // FIXME: please move this part to LoadQueueReplay 1174 io.debug_ls := DontCare 1175 1176 // Topdown 1177 io.lsTopdownInfo.s1.robIdx := s1_in.uop.robIdx.value 1178 io.lsTopdownInfo.s1.vaddr_valid := s1_valid && s1_in.hasROBEntry 1179 io.lsTopdownInfo.s1.vaddr_bits := s1_vaddr 1180 io.lsTopdownInfo.s2.robIdx := s2_in.uop.robIdx.value 1181 io.lsTopdownInfo.s2.paddr_valid := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss 1182 io.lsTopdownInfo.s2.paddr_bits := s2_in.paddr 1183 1184 // perf cnt 1185 XSPerfAccumulate("s0_in_valid", io.ldin.valid) 1186 XSPerfAccumulate("s0_in_block", io.ldin.valid && !io.ldin.fire) 1187 XSPerfAccumulate("s0_in_fire_first_issue", s0_valid && s0_isFirstIssue) 1188 XSPerfAccumulate("s0_lsq_fire_first_issue", io.replay.fire) 1189 XSPerfAccumulate("s0_ldu_fire_first_issue", io.ldin.fire && s0_isFirstIssue) 1190 XSPerfAccumulate("s0_fast_replay_issue", io.fast_rep_in.fire) 1191 XSPerfAccumulate("s0_stall_out", s0_valid && !s0_can_go) 1192 XSPerfAccumulate("s0_stall_dcache", s0_valid && !io.dcache.req.ready) 1193 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.ldin.bits.src(0)(VAddrBits-1, 12)) 1194 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.ldin.bits.src(0)(VAddrBits-1, 12)) 1195 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.ldin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1196 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.ldin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1197 XSPerfAccumulate("s0_forward_tl_d_channel", s0_out.forward_tlDchannel) 1198 XSPerfAccumulate("s0_hardware_prefetch_fire", s0_fire && s0_hw_prf_select) 1199 XSPerfAccumulate("s0_software_prefetch_fire", s0_fire && s0_prf && s0_int_iss_select) 1200 XSPerfAccumulate("s0_hardware_prefetch_blocked", io.prefetch_req.valid && !s0_hw_prf_select) 1201 XSPerfAccumulate("s0_hardware_prefetch_total", io.prefetch_req.valid) 1202 1203 XSPerfAccumulate("s1_in_valid", s1_valid) 1204 XSPerfAccumulate("s1_in_fire", s1_fire) 1205 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 1206 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 1207 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 1208 XSPerfAccumulate("s1_stall_out", s1_valid && !s1_can_go) 1209 XSPerfAccumulate("s1_late_kill", s1_valid && s1_fast_rep_kill) 1210 1211 XSPerfAccumulate("s2_in_valid", s2_valid) 1212 XSPerfAccumulate("s2_in_fire", s2_fire) 1213 XSPerfAccumulate("s2_in_fire_first_issue", s2_fire && s2_in.isFirstIssue) 1214 XSPerfAccumulate("s2_dcache_miss", s2_fire && io.dcache.resp.bits.miss) 1215 XSPerfAccumulate("s2_dcache_miss_first_issue", s2_fire && io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1216 XSPerfAccumulate("s2_dcache_real_miss_first_issue", s2_fire && io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1217 XSPerfAccumulate("s2_full_forward", s2_fire && s2_full_fwd) 1218 XSPerfAccumulate("s2_dcache_miss_full_forward", s2_fire && s2_dcache_miss) 1219 XSPerfAccumulate("s2_fwd_frm_d_can", s2_valid && s2_fwd_frm_d_chan) 1220 XSPerfAccumulate("s2_fwd_frm_d_chan_or_mshr", s2_valid && s2_fwd_frm_d_chan_or_mshr) 1221 XSPerfAccumulate("s2_stall_out", s2_fire && !s2_can_go) 1222 XSPerfAccumulate("s2_prefetch", s2_fire && s2_prf) 1223 XSPerfAccumulate("s2_prefetch_ignored", s2_fire && s2_prf && s2_mq_nack) // ignore prefetch for mshr full / miss req port conflict 1224 XSPerfAccumulate("s2_prefetch_miss", s2_fire && s2_prf && io.dcache.resp.bits.miss) // prefetch req miss in l1 1225 XSPerfAccumulate("s2_prefetch_hit", s2_fire && s2_prf && !io.dcache.resp.bits.miss) // prefetch req hit in l1 1226 XSPerfAccumulate("s2_prefetch_accept", s2_fire && s2_prf && io.dcache.resp.bits.miss && !s2_mq_nack) // prefetch a missed line in l1, and l1 accepted it 1227 XSPerfAccumulate("s2_successfully_forward_channel_D", s2_fwd_frm_d_chan && s2_fwd_data_valid) 1228 XSPerfAccumulate("s2_successfully_forward_mshr", s2_fwd_frm_mshr && s2_fwd_data_valid) 1229 1230 XSPerfAccumulate("s3_fwd_frm_d_chan", s3_valid && s3_fwd_frm_d_chan_valid) 1231 1232 XSPerfAccumulate("load_to_load_forward", s1_try_ptr_chasing && !s1_ptr_chasing_canceled) 1233 XSPerfAccumulate("load_to_load_forward_try", s1_try_ptr_chasing) 1234 XSPerfAccumulate("load_to_load_forward_fail", s1_cancel_ptr_chasing) 1235 XSPerfAccumulate("load_to_load_forward_fail_cancelled", s1_cancel_ptr_chasing && s1_ptr_chasing_canceled) 1236 XSPerfAccumulate("load_to_load_forward_fail_wakeup_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && s1_not_fast_match) 1237 XSPerfAccumulate("load_to_load_forward_fail_op_not_ld", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && s1_fu_op_type_not_ld) 1238 XSPerfAccumulate("load_to_load_forward_fail_addr_align", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && s1_addr_misaligned) 1239 XSPerfAccumulate("load_to_load_forward_fail_set_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && !s1_addr_misaligned && s1_addr_mismatch) 1240 1241 // bug lyq: some signals in perfEvents are no longer suitable for the current MemBlock design 1242 // hardware performance counter 1243 val perfEvents = Seq( 1244 ("load_s0_in_fire ", s0_fire ), 1245 ("load_to_load_forward ", s1_fire && s1_try_ptr_chasing && !s1_ptr_chasing_canceled ), 1246 ("stall_dcache ", s0_valid && s0_can_go && !io.dcache.req.ready ), 1247 ("load_s1_in_fire ", s0_fire ), 1248 ("load_s1_tlb_miss ", s1_fire && io.tlb.resp.bits.miss ), 1249 ("load_s2_in_fire ", s1_fire ), 1250 ("load_s2_dcache_miss ", s2_fire && io.dcache.resp.bits.miss ), 1251 ) 1252 generatePerfEvent() 1253 1254 when(io.ldout.fire){ 1255 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 1256 } 1257 // end 1258}