refactor(DFT): refactor `DFT` IO (#4530)

area(ICache): split ICache meta SRAM (#4468)

As per the requirements of the physical backend, split the ICache's Tag
SRAM into smaller blocks.

fix(IPrefetchPipe): consider backend exception as part of itlb exception (#4423)

`s1_exception_out` is for prefetch s2 only, but we want backend
exception to be considered as part of itlb exception

fix(IPrefetchPipe): consider backend exception as part of itlb exception (#4423)

`s1_exception_out` is for prefetch s2 only, but we want backend
exception to be considered as part of itlb exception and sent to
waylookup, so we merge it to `s1_itlb_exception`

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fix(IFU): handle uncache corrupt (#4301)

When InstrUncache Tilelink bus gives `d.bits.corrupt` or `d.bits.denied`
(included in `d.bits.corrupt`), mark the fetch block as `access fault`,
and skips `m

fix(IFU): handle uncache corrupt (#4301)

When InstrUncache Tilelink bus gives `d.bits.corrupt` or `d.bits.denied`
(included in `d.bits.corrupt`), mark the fetch block as `access fault`,
and skips `m_resendTLB` etc..

Also:
- remove `currentIsRVC` as it's actually identical with `mmio_is_RVC`
- fix `crossPageIPFFix`, it should be valid only when `mmio_has_resend`
- rename `mmio_resend_exception` to `mmio_exception`, since it's also
used to store Tilelink corrupt before resend

Update: rebased to Feb-28-2025-66e9b546 for regression test.

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chore: fix several deprecation warning (#4352)

feat(dfx): integerate dfx components (#4312)

timing(icache): restore the relaxation of ICG for icache data (#4255)

Revert #4246

timing(icache): remove tag-related clock gating for timing (#4246)

timing(frontend): remove bad timing clock gating (#4223)

- Remove `mispred_mask` from ITTAGE update logic due to timing issues
- Remove `mispred_mask` from TAGE update logic due to timing issues
-

timing(frontend): remove bad timing clock gating (#4223)

- Remove `mispred_mask` from ITTAGE update logic due to timing issues
- Remove `mispred_mask` from TAGE update logic due to timing issues
- Disable clock gating in ICacheDataArray to improve timing

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timing(ICache): move mshr_resp selector 1 cycle ahead (#4173)

> we can latch mshr.io.resp.bits since they are set on req.fire or
acquire.fire, and keeps unchanged during response
> however, we sho

timing(ICache): move mshr_resp selector 1 cycle ahead (#4173)

> we can latch mshr.io.resp.bits since they are set on req.fire or
acquire.fire, and keeps unchanged during response
> however, we should not latch mshr.io.resp.valid, since io.flush/fencei
may clear it at any time

Old:
```
tilelink.resp.id -> | Reg |
|
v
| MSHR0 | -> | --- |
| MSHR1 | -> | Mux | -> io.resp
| ... | -> | |
| MSHRn | -> | --- |
```

New:
```
tilelink.resp.id
|
v
| MSHR0 | -> | --- |
| MSHR1 | -> | Mux | -> | Reg | -> io.resp
| ... | -> | |
| MSHRn | -> | --- |
```

Timing results are good, related path: slack -44ps -> positive.

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fix(ICacheMissUnit): clear corrupt_r when response is sent to MainPipe (#4112)

feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check

feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check & ECC inject features
- Implement ICache ECC injection
- M-state software can write `eccctrl` to trigger error injection to meta/dataArray, next read can trigger auto-recovery (implemented in #3899)
- Remove custom CSR `Sfetchctl`

# Details
## CSR
The base address of the added mmio-mapped CSR is `0x38022080` and the registers is defined as below:
```
64 10 7 4 2 1 0
0x00 eccctrl | WARL | ierror | istatus | itarget | inject | enable |

64 PAddrBits-1 0
0x08 ecciaddr | WARL | paddr |
```
| CSR | field | desp |
| --- | --- | --- |
| eccctrl | enable | ECC check enable |
| eccctrl | inject | ECC inject enable (write 1 to trigger injection, read always 0) |
| eccctrl | itarget | ECC inject target<br>0: metaArray<br>1: rsvd<br>2: dataArray<br>3: rsvd |
| eccctrl | istatus | ECC inject status (read-only)<br>0: idle: inject controller idle, goes to working when received a inject request (i.e. write 1 to eccctrl.inject)<br>1: working: inject controller working, goes to injected when finished / error when failed<br>2: injected, goes to idle after read<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: error: inject failed (check eccctl.ierror for reason), goes to idle after read |
| eccctrl | ierror | ECC error reason (read-only, valid only if `eccctrl.istatus==error`)<br>0: ECC check is not enabled (i.e. `!eccctrl.enable`)<br>1: inject target invalid (i.e. `eccctrl.itarget==rsvd`)<br>2: inject addr (i.e. `ecciaddr.paddr`) not in ICache<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: rsvd |
| ecciaddr | paddr | Physical address of the inject target |

## Inject method
```asm
$INJECT_ADDR:
# maybe do something else
ret

test:
la t0, $BASE_ADDR # load icache control base addr
la t1, $INJECT_ADDR # load inject addr
jalr ra, 0(t1) # jump to injected addr to load it i
sd t1, 8(t0) # set inject addr
la t2, (target << 2 | 1 << 1 | 1 << 0) # load inject target & inject enable & ecc enable
sd t1, 0(t0) # set inject enable & ecc enable
loop:
ld t1, 0(t0) # get ecc control state
andi t1, t1, (0b11 << (4+1)) # get high bits of inject state
beqz t1, loop # if is idle, or working, loop

addi t1, t1, -1 # t1 = inject_state[2:1] - 1
bnez t1, error # if is not injected, error or rsvd

jalr ra, 0(t1) # jump to injected addr to trigger error
j finish

error:
# handle error
finish:
# finish
```
Or, checkout https://github.com/OpenXiangShan/nexus-am/pull/48

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fix(ICache,ITLB): also flush itlb pipe when prefetchPipe s1_flush (#3996)

ITLB does not store `gpaddr` to save resources, instead it takes
`gpaddr` from L2TLB when gpf occurs, which poses a two-opt

fix(ICache,ITLB): also flush itlb pipe when prefetchPipe s1_flush (#3996)

ITLB does not store `gpaddr` to save resources, instead it takes
`gpaddr` from L2TLB when gpf occurs, which poses a two-option
requirement for the requestor (i.e. IPrefetchPipe):
1. resend the same `itlb.io.req.vaddr` until `itlb.io.resp.miss` is
pulled down
2. flush gpf entry in ITLB by pulling up `itlb.io.flushPipe`

Otherwise, ITLB is unable to handle the next gpf and the core hangs.

However, the first point cannot be guaranteed during the speculative
execution, as IPrefetchPipe sends request to ITLB at s0 stage and may
receive a flush request from BPU s3 stage, IFU or Backend at s1 stage,
then the same vaddr is never resend to ITLB.

Therefore, we must ensure that ITLB is flushed synchronously when
IPrefetchPipe s1 stage is flushed, thus satisfying the second point.
This PR implements this.

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refactor(ICache): refactor code style & eliminate IDE warnings (#3947)

- add type annotation to public members
- add private qualifier to other members
- add `asUInt` to shift results (Bits)
- fi

refactor(ICache): refactor code style & eliminate IDE warnings (#3947)

- add type annotation to public members
- add private qualifier to other members
- add `asUInt` to shift results (Bits)
- fix typo
- remove unused imports
- rename `ICacheMSHR.waymask` to `way` since it is not a mask
- use `idxBits` for `log2Up(nSets)`
- use `wayBits` for `log2Up(nWays)`
- use `foreach` instead of `map` when return value is not needed
- use `{}` instead of `()` for multi-line `foreach` and `map`

The generated verilog is checked and is identical with the original
(except `waymask` -> `way` & order changes).

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refactor(IFU,ICache): refactor interface (#3914)

Move Vec(2) inside `ICacheMainPipeResp` to eliminate unused ports. No
functional changes.

feat(ICache): re-fetch data from L2 if ECC error is detected (#3899)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)*
error recovery features.

Unlike DCache, data in ICache i

feat(ICache): re-fetch data from L2 if ECC error is detected (#3899)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)*
error recovery features.

Unlike DCache, data in ICache is always not dirty, so when it is
corrupted, we can always re-fetch from L2 cache.

Port & behavior changes:
- Add a `flush` port to metaArray, letting mainPipe be able to clear
valid_array before doing re-fetch, thereby preventing multi-hit in
ICache.
- if metaArray ECC error is detected, flush vSets in each way, since
`waymask` is unreliable.
- if dataArray ECC error is detected, flush the vSet in way specified by
`waymask`.
- metaArray / dataArray ECC errors will no longer raise access fault, as
they can be resolved by re-fetching. Raise af only when response from L2
is marked as corrupted.
- When ECC error is detected, mainPipe will send miss requests to L2
through MissUnit.

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fix(CSR): correct the width of PC pgaddr for inst fetch exception (#3795)

We found that the CSR mtval2 truncates the high bits of gpaddr when GPF
occurs in instruction fetching. Actually, there is

fix(CSR): correct the width of PC pgaddr for inst fetch exception (#3795)

We found that the CSR mtval2 truncates the high bits of gpaddr when GPF
occurs in instruction fetching. Actually, there is an GPAMem which
storages the whole 64-bit gpaddr, but it does not pass to CSR correctly,
due to incorrect width of trapPCGPA in module NewCSR and bundle
TrapEntryEventInput. This patch fixes this.

---------

Co-authored-by: ngc7331 <[email protected]>

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feat(frontend): add ClockGate at frontend SRAMTemplate (#3889)

* Add param `withClockGate` at SRAMTemplate
* when SRAM is single-port, use maskedClock for both array\.read\(\) and
array\.write\(\)

feat(frontend): add ClockGate at frontend SRAMTemplate (#3889)

* Add param `withClockGate` at SRAMTemplate
* when SRAM is single-port, use maskedClock for both array\.read\(\) and
array\.write\(\) to ensure single-port SRAM access.
* when SRAM is multi-port, the read and write ports of the multi-port
SRAM are gated using different clocks.

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docs: add acknowledgements (#3861)

refactor(Frontend): add ExceptionType.hasExcaption wrapper (#3866)

https://github.com/OpenXiangShan/XiangShan/pull/3787#discussion_r1818322915

area(DCache): reduce 8 way to 4 way (#3849)

fix(ICache): cancel prefetch when there is exception from backend (#3787)

fix(ICache): use PriorityMux instead of Mux1H for io.error (#3784)

mainPipe.io.errors is not ensured to be at-most-one-hot, ECC errors may
occur on both cachelines at the same time.

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

timing(ICache): allow send MSHR response to (pre)fetch even when io.flush (#3542)

Cut critical path `io.flush -> mainPipe/prefetchPipe s2_miss -> s2_ready
-> ftq ready` for timing.

Now missUnit

timing(ICache): allow send MSHR response to (pre)fetch even when io.flush (#3542)

Cut critical path `io.flush -> mainPipe/prefetchPipe s2_miss -> s2_ready
-> ftq ready` for timing.

Now missUnit will still send response to mainPipe/prefetchPipe/wayLookup
when `io.flush` or `io.fencei` is `true.B`, but unnecessary response
will be dropped by mainPipe/prefetchPipe/wayLookup since their
`sx_valid` is set to false at the moment, so no functional/performance
change is expected.

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